顔写真

フクシマ タカフミ
福島 誉史
Takafumi Fukushima
所属
大学院工学研究科 機械機能創成専攻 機能システム学講座(機械力学分野)
職名
准教授
学位
  • 博士(工学)(横浜国立大学)

  • 修士(工学)(横浜国立大学)

経歴 15

  • 2023年7月 ~ 継続中
    兼任 熊本大学 半導体・デジタル研究教育機構 半導体部門 クロスアポイントメント教授

  • 2023年4月 ~ 継続中
    兼任 東北大学未来科学技術共同研究センター ホリスティック三次元集積半導体開発とオープンイノベーション拠点の構築 プロジェクトリーダー

  • 2019年4月 ~ 継続中
    兼任 東北大学 大学院医工学研究科 医工学専攻 准教授

  • 2016年8月 ~ 継続中
    東北大学 大学院工学研究科 機械機能創成専攻 准教授

  • 2018年3月 ~ 2023年3月
    兼任 東北大学未来科学技術共同研究センター 情報環境(Info-Sphere)調和型 自己組織化ヘテロ集積システムの開発 プロジェクトリーダー

  • 2022年9月 ~ 2022年11月
    University of California, Los Angeles (UCLA), Visiting Faculty

  • 2016年3月 ~ 2017年7月
    University of California, Los Angeles (UCLA) Visiting Faculty

  • 2015年4月 ~ 2016年7月
    東北大学 大学院工学研究科 バイオロボティクス専攻 准教授

  • 2010年4月 ~ 2015年3月
    東北大学未来科学技術共同研究センター 准教授

  • 2010年11月 ~ 2010年12月
    Fraunhofer EMFT (Germany) Visiting Researcher

  • 2010年10月 ~ 2010年11月
    Fraunhofer IZM (Germany) Visiting Researcher

  • 2007年4月 ~ 2010年3月
    東北大学大学院工学研究科 助教

  • 2004年8月 ~ 2007年3月
    東北大学大学院工学研究科 助手

  • 2003年4月 ~ 2004年7月
    東北大学ベンチャービジネスラボラトリー 講師(中核的研究機関研究員)

  • 2001年4月 ~ 2003年3月
    株式会社ピーアイ技術研究所 技術顧問

︎全件表示 ︎最初の5件までを表示

委員歴 26

  • エレクトロニクス実装学会誌 編集委員会 委員

    2023年6月 ~ 継続中

  • IEEE CPMT Symposium Japan Committee Member

    2022年12月 ~ 継続中

  • ADMETAPlus (Advanced Metallization Conference) Committee member

    2022年12月 ~ 継続中

  • 応用物理学会 シリコンテクノロジー分科会 多層配線システム技術委員会 委員

    2022年4月 ~ 継続中

  • IEEE EPS (Electronics Packaging Society) Japan Committee Member

    2021年1月 ~ 継続中

  • 一般社団法人 電子実装工学研究所 IMSI (Institute for Advanced Micro-System Integration), 外部学界会員(2020年4月28日から現在) 外部学界会員

    2020年4月 ~ 継続中

  • IMPACT (International Microsystems, Packaging, Assembly and Circuits Technology Conference) International Advisory Board (IAB) Members

    2018年 ~ 継続中

  • The Annual International Conference on Manipulation, Automation and Robotics at Small Scales (MARSS) Program committee

    2016年4月 ~ 継続中

  • “Interconnections” Session in IEEE Electronic Components and Technology Conference (ECTC) Program Committee

    2013年7月 ~ 継続中

  • MDPIオープンアクセス誌Micromachines (IF: 2.523) Editorial Board Members

    2020年4月 ~ 2023年7月

  • 社団法人エレクトロニクス実装学会 常任理事

    2022年6月 ~ 2023年5月

  • 社団法人エレクトロニクス実装学会 エレクトロニクス実装学会誌 編集委員会 委員長

    2022年6月 ~ 2023年5月

  • 社団法人エレクトロニクス実装学会 エレクトロニクス実装学会誌 編集委員会 副委員長

    2021年6月 ~ 2022年5月

  • 社団法人エレクトロニクス実装学会 理事

    2021年6月 ~ 2022年5月

  • MDPIオープンアクセス誌Electronics (IF: 2.412) Special Issue "Microelectronics Packaging and Flexible Hybrid Electronics" Guest Editor

    2020年11月 ~ 2021年10月

  • 日本学術振興会 産学協力研究委員会 接合界面創成技術第191 委員会 委員

    2015年10月 ~ 2020年10月

  • 電子情報通信学会, エレクトロニクスソサエティ和文論文誌C 実装特集号 論文編集委員

    2011年 ~ 2020年

  • 2019 IEEE International 3D System Integration Conference Program Chair

    2018年2月 ~ 2019年10月

  • International IEEE Workshop on Low Temperature Bonding for 3D Integration Organizer

    2007年11月 ~ 2019年5月

  • 2017 MRS Fall Meeting Symposium PM4: Micro-Assembly Technologies -Fundamentals to Applications Lead organizer and Session Chair

    2016年4月 ~ 2017年12月

  • International Conference on Solid State Devices and Materials (SSDM) Area 2: Interconnection Sub-Committee and Session Chair

    2009年10月 ~ 2017年10月

  • IEEE TRANSACTIONS ON NANOTECHNOLOGY Associate Editor

    2015年5月 ~ 2017年4月

  • 平成26年度戦略的基盤技術高度化支援事業(サポイン)「研究課題名: 低消費電力半導体の貫通電極ウエハボイドレス超高速めっき装置技術の開発」 アドバイザー

    2014年8月 ~ 2017年3月

  • 電子情報通信学会, ソサイエティ論文誌編集委員会 リエゾン幹事

    2012年6月 ~ 2014年6月

  • 第27回 エレクトロニクス実装学会講演大会 実行副委員長 兼 プロモート委員

    2012年7月 ~ 2013年3月

  • IEEE EPS Heterogeneous Integration Roadmap 2019 Edition, Chapter 22: Interconnects for 2D and 3D Architectures Key Contributor

    2019年 ~

︎全件表示 ︎最初の5件までを表示

所属学協会 5

  • 日本機械学会

  • IEEE (Institute of Electrical and Electronics Engineering)

  • 応用物理学会

  • エレクトロニクス実装学会

  • 高分子学会

研究キーワード 7

  • フレキシブルデバイス

  • 自己組織化/誘導自己組織化

  • マイクロ・ナノ加工

  • 半導体パッケージング

  • 機能性高分子

  • 人工感覚デバイス

  • 三次元集積回路技術

研究分野 2

  • ものづくり技術(機械・電気電子・化学工学) / 電子デバイス、電子機器 /

  • ナノテク・材料 / 高分子材料 /

受賞 10

  1. In appreciation of sustained contribution of the ECTC (10 Years Contribution Award)

    2023年6月 IEEE Electronics Packaging Society (EPS)

  2. 田中貴金属 記念財団 貴金属に関わる研究助成 プラチナ賞 「ブロック高分子と金属ナノ粒子が創出する拡張誘導自己組織化配線に関する技術開発」

    2017年3月 田中貴金属記念財団

  3. 第25 回エレクトロニクス実装学術講演大会 研究奨励賞

    2012年3月 一般社団法人エレクトロニクス実装学会 狭ピッチ金属マイクロバンプを有するチップの自己組織化実装技術

  4. The 60th IEEE Electronic Components and Technology Conference (ECTC) Outstanding Session Paper Award

    2011年6月 IEEE CPMT (Components, Packaging and Manufacturing Technology) Society Self-Assembly Technology for Reconfigured Wafer-to-Wafer 3D Integration

  5. ドイツ・イノベーション・アワード 「ゴットフリード・ワグネル賞2009」the 2nd Prize

    2010年2月 ドイツ連邦教育研究省, フラウンホーファー研究機構, ドイツ学術交流会DAAD, ドイツ企業12社等の共催 Surface-Tension-Powered Chip Self-Assembly Technology for Three-Dimensional IC Fabrication

  6. Material Research Society (MRS) Fall Meeting Invited Speaker Award

    2008年12月 The committee of the Symposium E: Materials and Technologies for 3-D Integration Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking

  7. 財団法人 青葉工学振興会 第13回研究奨励賞

    2008年2月5日 財団法人 青葉工学振興会 研究業績名「自己組織化による次世代集積回路形成プロセスの創製」

  8. 2006 International Conference on Electronics Packaging / Outstanding Technical Paper Award

    2007年4月18日 JIEP (Japan Institute of Electronics Packaging)

  9. 第83回日本化学会春季年会 学生講演賞

    2003年3月 日本化学会

  10. 第15回エレクトロニクス実装学術講演大会 研究奨励賞

    2002年3月 エレクトロニクス実装学会

︎全件表示 ︎最初の5件までを表示

論文 436

  1. An Electronic Microsaccade Circuit with Charge-Balanced Stimulation and Flicker Vision Prevention for an Artificial Eyeball System 査読有り

    Yaogan Liang, Kohei Nakamura, Bang Du, Shengwei Wang, Bunta Inoue, Yuta Aruga, Hisashi Kino, Takafumi Fukushima, Koji Kiyoyama, ndTetsu Tanaka

    Electronics (MDPI) 12 (2836) 1-17 2023年6月

  2. チップレットの概念と 3D-IC のラピッドプロトタイピング 招待有り 査読有り

    福島誉史

    エレクトロニクス実装学会誌(特集/3D・チップレット集積化技術動向) 26 (4) 333-340 2023年4月

    DOI: 10.5104/jiep.26.333  

  3. Gapless Chip-in-Carrier Integration and Injectable Ag/AgCl-Epoxy Reference Electrode for Bilayer Lipid Membrane Sensor 招待有り 査読有り

    Hiromichi Wakebe, Yuki Susumago, Takafumi Fukushima, Tetsu Tanaka

    IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING 18 (3) 477-487 2023年3月

    DOI: 10.1002/tee.23744  

  4. 3D-IC/TSVの最新動向と自己組織化による三次元実装/ヘテロ集積 招待有り

    福島誉史

    化学工学会誌(小特集 / 次世代半導体の展望~原理と生産技術~ 87 (1) 33-36 2023年

  5. Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration with μLED 査読有り

    Yuki Susumago, Takafumi Fukushima

    IEEE Electron Device Letters 2023年1月

  6. 脂質二分子膜センサのための埋植チップ上SU;マイクロチャネル直接形成法の開発 招待有り 査読有り

    分部寛道, 福島誉史, 田中徹

    電気学会論文誌;センサ;マイクロマシン部門誌 141 (10) 327-335 2022年10月

  7. TSV形成の基礎と三次元実装の動向 招待有り 査読有り

    福島誉史

    エレクトロニクス実装学会誌(講座「三次元実装基礎講座」第1回) 25 (7) 700-708 2022年9月

    DOI: 10.5104/jiep.25.700  

  8. Electrochemical characterization of ZnO-based transparent materials as recording electrodes for neural probes in optogenetics 査読有り

    Yuki Miwa, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    Journal of Vacuum Science & Technology B 40 (5) 052202-052202 2022年9月

    出版者・発行元:American Vacuum Society

    DOI: 10.1116/6.0001836  

    ISSN:2166-2746

    eISSN:2166-2754

    詳細を見る 詳細を閉じる

    In the elucidation of brain functions, neuroscience has garnered attention in the realization of brain-machine interfaces, deep brain stimulation, and artificial intelligence. Optogenetics is a biological technique used to control neural activities via optical stimulation. It is one of the most effective approaches used to investigate brain functions. This study proposed to employ the transparent recording electrode to enhance the performance of neural probes for optogenetics. Compared with conventional metal recording electrodes, the proposed transparent recording electrodes have the potential to obtain higher signal-to-noise ratios when placed over optical stimulation points. To develop transparent recording electrodes, we used ZnO-based materials with good biocompatibility and transparency for utilization as biomedical electrodes. Considering saline as one of the main components of living organisms, we investigated the fundamental electrochemical characteristics of ZnO-based electrodes in saline through electrochemical impedance spectroscopy and cyclic voltammetry. The results showed that nondoped ZnO and Al-doped ZnO, deposited by radio frequency magnetron sputtering, exhibited a broad potential window. An electrical double layer was found to strongly act on the interface between the electrodes and solution rather than a redox reaction. In addition, this study reports the effects of crystallization and dopant on the electrochemical characteristics of the ZnO-based electrodes. The transparent ZnO-based electrode developed herein is a promising candidate to enhance the performance of neural probes for optogenetics and can be effectively applied in biological devices.

  9. Developing a Low-Temperature Flip-Chip Bonding Technology with In/Au Microbumps to Suppress the Thermal Load on Spintronics Devices 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2022 IEEE International Interconnect Technology Conference (IITC) 2022年6月27日

    出版者・発行元:IEEE

    DOI: 10.1109/iitc52079.2022.9881288  

  10. Room-Temperature Cu Direct Bonding Technology Enabling 3D Integration with Micro-LEDs 査読有り

    Yuki Susumago, Shunsuke Arayama, Tadaaki Hoshi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima

    2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) 2022年5月

    出版者・発行元:IEEE

    DOI: 10.1109/ectc51906.2022.00225  

  11. Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide Systems 査読有り

    Toshiaki Shirasaka, Tadashi Okuda, Tomoaki Shibata, Satoshi Yoneda, Daisaku Matsukawa, Murugesan Mariappan, Mitsumasa Koyanagi, Takafumi Fukushima

    2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) 2022年5月

    出版者・発行元:IEEE

    DOI: 10.1109/ectc51906.2022.00059  

  12. Tight-Pitched 10 μm-Width Solder Joints for c-2-c and c-2-w 3D-Integration in NCF Environment 査読有り

    Murugesan Mariappan, Shizu Fukuzumi, Tomoaki Shibata, Hiroyuki Hashimoto, JiChel Bea, Mitsumasa Koyanagi, Takafumi Fukushima

    2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) 2022年5月

    出版者・発行元:IEEE

    DOI: 10.1109/ectc51906.2022.00184  

  13. Cu-SiO<sub>2</sub> Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement 査読有り

    M. Murugesan, K. Mori, M. Sawa, E. Sone, M. Koyanagi, T. Fukushima

    2022 IEEE 72nd Electronic Components and Technology Conference (ECTC) 2022年5月

    出版者・発行元:IEEE

    DOI: 10.1109/ectc51906.2022.00115  

  14. Enhancement of carrier mobility in metal-oxide semiconductor field-effect transistors using negative thermal expansiongate electrodes

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    Applied Physics Express 15 (11) 111004-1-111004-5 2022年4月

    DOI: 10.35848/1882-0786/ac9d24  

  15. Design and Evaluation of Electronic-Microsaccade with Balanced Stimulation for Artificial Vision System 査読有り

    Yaogan Liana, Zhengyang Qian, Bang Du, Jinming Ye, Kohei Nakamura, Shengwei Wang, Hisashi Kino, Takafumi Fukushima, Koji Kiyoyama, Tetsu Tanaka

    2021 IEEE Biomedical Circuits and Systems Conference (BioCAS) 2021年10月7日

    出版者・発行元:IEEE

    DOI: 10.1109/biocas49922.2021.9645034  

  16. Chip-to-Chip/Wafer Three-Dimensional Integration of 2.5 mm-sized Neuron and Memory Chips by Via-Last Approach 査読有り

    M. Murugesan, H. Hashimoto, Jichel Bea, M. Koyanagi, T. Fukushima

    2021 7th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D) 2021年10月5日

    出版者・発行元:IEEE

    DOI: 10.1109/ltb-3d53950.2021.9598372  

  17. Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing 査読有り

    Koji Kiyoyama, Yoshihiko Horio, Takafumi Fukushima, Hiroyuki Hashimoto, Takemori Orima, Mitsumasa Koyanagi

    2021 IEEE International 3D Systems Integration Conference (3DIC) 2021年10月

    出版者・発行元:IEEE

    DOI: 10.1109/3dic52383.2021.9687608  

    ISSN:2164-0157

    詳細を見る 詳細を閉じる

    An analog-based CMOS neuron with crossbar configuration multiplier-adder circuit for three-dimensional chip stacking (3-D) cyclic signal processing deep neural network is presented. The circuit designed to verify the proposed concept is a total of four-layer stacked chips, consisting of two neuron chips that mainly perform analog multiply-accumulate (MAC) operations and two memory chips that store neuron potential (activation) and weight data. According to papers and conference presentations on accelerators for the neural network circuit, the analog MAC operation has the potential to achieve high efficiency by using the analog processing of the crossbar configuration. However, analog MAC circuit with compensation technique is required to overcome the decrease in computing accuracy due to electrical noise and element nonlinearity. In this study, we have designed and verified a highly linearity multiplier-adder circuit for highly efficient 3-D cyclic analog processing. In this paper, we focus on the current adder circuit with switched capacitor correlated double sampling (CDS) technique, to minimize non-linearity, noise, and circuit area. The proposed the analog adder circuit was designed with 180-nm and operation power supply voltage 1.8V CMOS technology, and the fabricated neuron chip that integrates 64 neurons and 64x64 synaptic connections. As analysis results, it was confirmed that the CDS technique apply analog adder circuit reduced the noise output voltage less than 0.1mV and the range of voltage linearity was over 1.6V.

  18. Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications 査読有り

    M. Murugesan, E. Sone, A. Simomura, M. Motoyoshi, M. Sawa, K. Fukuda, M. Koyanagi, T. Fukushima

    2021 IEEE International 3D Systems Integration Conference (3DIC) 2021年10月

    出版者・発行元:IEEE

    DOI: 10.1109/3dic52383.2021.9687604  

  19. Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing 査読有り

    Takafumi Fukushima, Shinichi Sakuyama, Masatomo Takahashi, Hiroyuki Hashimoto, Jichoel Bea, Theodorus Marcello, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi, Murugesan Mariappan

    2021 IEEE International 3D Systems Integration Conference (3DIC) 2021年10月

    出版者・発行元:IEEE

    DOI: 10.1109/3dic52383.2021.9687601  

  20. Multi-level Metallization on an Elastomer PDMS for FOWLP-based Flexible Hybrid Electronics 査読有り

    Zhe Wang, Ikumi Ozawa, Yuki Susumago, Tomo Odashima, Noriyuki Takahashi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima

    2021 IEEE International Interconnect Technology Conference, IITC 2021 2021年7月6日

    DOI: 10.1109/IITC51362.2021.9537540  

    詳細を見る 詳細を閉じる

    In order to fabricate a wearable flexible display as a flexible hybrid electronic (FHE) device with micro-LED dies, we demonstrate multi-level metallization on an elastomer using die-first fan-out wafer-level packaging (FOWLP). The elastic substrate of this display is PDMS (polydimethylsiloxane) in which the array of 3-color micro-LEDs is embedded. In this study, we address serious issues such as die shift and stress accumulation in advanced FOWLP to integrate a self-luminescent flexible micro-LED display.

  21. Development of Manganese Nitride Resistor with Near-Zero Temperature-Coefficient of Resistance to Achieve High-Thermal-Stability ICs 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2021 IEEE International Interconnect Technology Conference, IITC 2021 2021年7月6日

    DOI: 10.1109/IITC51362.2021.9537336  

    詳細を見る 詳細を閉じる

    The resistance of the metal wirings in the integrated circuits increases due to the decrease of the mean free path of electrons with the temperature increase. This thermal instability requires redundancy circuits. On the other hand, several materials have the saturation characteristics of the mean free path around room temperature. The anti-perovskite manganese nitride compound material is one of them. The anti-perovskite manganese nitride compounds show a flat resistance-temperature curve around room temperature. However, the flat resistance-temperature curves have been obtained with only the sintered bulk materials. It has not become clear the characteristics of the manganese nitride compounds in the micro/nanoscale. In this study, we proposed manganese nitride wiring for high-thermal-stability systems. Then, we fabricated and evaluated the micro/nanoscale manganese nitride compound wiring with the complementary metal-oxide-semiconductor compatible process.

  22. Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE 招待有り 査読有り

    Takafumi Fukushima

    2021 Symposium on VLSI Circuits 2021年6月13日

    出版者・発行元:IEEE

    DOI: 10.23919/vlsicircuits52068.2021.9492335  

  23. High-thermal-stability resistor formed from manganese nitride compound that exhibits the saturation state of the mean free path 査読有り

    Applied Physics Express 14, (2021), 091003 14 (8) 091003 2021年

    DOI: 10.35848/1882-0786/ac18b0  

    ISSN:1882-0778

    eISSN:1882-0786

  24. On‐wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through‐silicon via applications: Comparison to plasma‐enhanced chemical vapor deposition SiO 2 査読有り

    Takafumi Fukushima, Mariappan Murugesan, Ji‐Cheol Bea, Hiroyuki Hashimoto, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi

    Journal of Polymer Science 58 (16) 2248-2258 2020年8月15日

    出版者・発行元:Wiley

    DOI: 10.1002/pol.20200094  

    ISSN:2642-4150

    eISSN:2642-4169

    詳細を見る 詳細を閉じる

    © 2020 The Authors. Journal of Polymer Science published by Wiley Periodicals LLC. Thin-film polyimides were prepared by solvent-less vapor deposition polymerization (VDP) from pyromellitic dianhydride and 4,4′-oxydianiline at 200 °C for liner dielectric formation of vertical interconnects called through-silicon vias (TSVs) used in three-dimensionally stacked integrated circuit (3DICs). FTIR, synchrotron XPS, and TDS were employed for determining the imidization ratio, and in addition, the mechanical properties, coefficient of thermal expansion and Young's modulus, of the VDP polyimide were characterized on Si wafers. The VDP polyimide exhibited extremely high conformality, beyond 75%, toward high-aspect-ratio deep Si holes, compared with conventional SiO2 prepared by plasma-enhanced chemical vapor deposition. The adhesion between the VDP polyimide and Si wafer was enhanced by an Al-chelate promotor. Remarkably, the VDP polyimide TSV liner dielectrics showed much less thermomechanical stresses applied to the Si surrounding the TSVs than the plasma-chemical vapor deposition SiO2. The small keep-out zone is expected for scaling down highly reliable 3DICs for the upcoming real artificial intelligence society.

  25. Significant Die-Shift Reduction and mu LED Integration Based on Die-First Fan-Out Wafer-Level Packaging for Flexible Hybrid Electronics 査読有り

    Takafumi Fukushima, Yuki Susumago, Zhengyang Qian, Chidai Shima, Bang Du, Noriyuki Takahashi, Shuta Nagata, Tomo Odashima, Hisashi Kino, Tetsu Tanaka

    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 10 (8) 1419-1422 2020年8月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TCPMT.2020.3009640  

    ISSN:2156-3950

    eISSN:2156-3985

    詳細を見る 詳細を閉じる

    Typical die shift is beyond several tens micrometers or more, which is a serious problem on advanced fan-out wafer-level packaging (FOWLP), to give inevitable misalignment errors in the subsequent photolithography processes for fine-pitch redistributed wiring layer (RDL) formation. In particular, this problem is expected to grow all the more serious in chiplets and tiny dies less than 1 mm in a side. In this work, the use of an anchoring layer is proposed to fix these dies/chiplets on a double-side laminate thermo-release tape and drastically reduce the die shift. In addition, an on-nail photoplethysmogram (PPG) sensor module as a part of flexible hybrid electronics (FHE) is integrated with mu LED (270 mu m x 270 mu m) based on a die-first FOWLP methodology using a biocompatible polydimethylsiloxane (PDMS) mold resin for real-time monitoring pulse wave and percutaneous oxygen saturation (SpO(2)). The repeated bendability of fan-out Au wirings formed on the PDMS and the current-voltage (I-V) behavior of the mu LED before and after die embedment in the PDMS is characterized.

  26. Direct fabrication of SU‐8 microchannel across an embedded chip for potentiometric bilayer lipid membrane sensor 査読有り

    Hiromichi Wakebe, Takafumi Fukushima, Tetsu Tanaka

    Electronics and Communications in Japan 105 (2) 2020年6月

    出版者・発行元:Wiley

    DOI: 10.1002/ecj.12343  

    ISSN:1942-9533

    eISSN:1942-9541

  27. Laue microdiffraction evaluation of bending stress in Au wiring formed on chip-embedded flexible hybrid electronics 査読有り

    M. Murugesan, Y. Susumago, K. Sumitani, Y. Imai, S. Kimura, T. Fukushima

    Japanese Journal of Applied Physics 60 (SB) SBBC02-SBBC02 2020年5月1日

    出版者・発行元:IOP Publishing

    DOI: 10.35848/1347-4065/abdb81  

    ISSN:0021-4922

    eISSN:1347-4065

  28. High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications 査読有り

    M. Murugesan, K. Mori, J.C. Bea, M. Koyanagi, T. Fukushima

    Japanese Journal of Applied Physics 59 (SG) SGGC02-SGGC02 2020年4月1日

    出版者・発行元:IOP Publishing

    DOI: 10.35848/1347-4065/ab75b8  

    ISSN:0021-4922

    eISSN:1347-4065

  29. Development of Non-Volatile Tunnel-FET Memory as a Synaptic Device for Low-Power Spiking Neural Networks 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) 2020年4月

    出版者・発行元:IEEE

    DOI: 10.1109/edtm47692.2020.9118027  

  30. Symmetric and asymmetric spike-timing-dependent plasticity function realized in a tunnel-field-effect-transistor-based charge-trapping memory 査読有り

    Hisashi Kino, Takafumi Fukusima, Tetsu Tanaka

    Japanese Journal of Applied Physics 59 (SG) 2020年4月

    DOI: 10.35848/1347-4065/ab6867  

    ISSN:0021-4922

    eISSN:1347-4065

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    © 2020 The Japan Society of Applied Physics. Spiking neural networks are attracting significant attention because they can perform cognitive tasks with relatively low power. In addition, we proposed a tunnel field-effect transistor (TFET)-based charge trapping memory to reduce the power consumption of the flash memory-based neural network circuit. The current-voltage characteristics of the fabricated TFET based memory cell were typical of the charge trapping memory. We then measured the symmetric and asymmetric spike-timing-dependent plasticity (STDP) characteristics of the fabricated TFET-based memory cell. The obtained characteristics reproduce the STDP of a biological synapse. These results indicated that there is a possibility of applying the proposed devices to neural network circuits.

  31. Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration 査読有り

    Sungho Lee, Rui Liang, Yuki Miwa, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    JAPANESE JOURNAL OF APPLIED PHYSICS 59 (SB) 2020年2月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.7567/1347-4065/ab4f3c  

    ISSN:0021-4922

    eISSN:1347-4065

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    Thinning defects such as chipping and cracking caused by multichip lapping and chemical mechanical polishing processes were evaluated for through-silicon via formation based on via-last/backside via technologies. Two types of temporary adhesives with different Young's moduli were used in this multichip-to-wafer (MC2W) approach for comparison. Impact of the temporary bonding conditions and temporary adhesive properties on the multichip thinning failure was discussed for achieving high-yield MC2W 3D integration. When a temporary adhesive with a low Young's modulus is employed, the space between adjacent chips and the chip sidewall covered with adhesive were found to be critical parameters to the multichip thinning without chipping and cracking. (C) 2019 The Japan Society of Applied Physics

  32. Tight-Pitch Au-Sn Interconnections for 3D-ICs Integration and Packaging Applications 査読有り

    Murugesan Mariappan, Mitsumasa Koyanagi, Takafumi Fukushima

    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) 1448-1452 2020年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC32862.2020.00229  

    ISSN:0569-5503

    eISSN:2377-5726

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    Si TEG chips containing Au-Sn micro-bumps (mu-bump) with various sizes (varying from 3 to 20 mu m) and pitch values (between 6 mu m and 30 mu m) were fabricated, and the flip-chip bonded chips were characterized for micro-structure and electrical resistance of Au-Sn mu-joints. An overall mu-joint height of similar to 1.8 mu m was obtained after thermal compression bonding at 180 degrees C for the 10 mu m pitch mu-bumps with solder (Sn) height of 1.0 similar to 1.5 mu m. The elemental analysis results showed that Au has diffused into the solder layer, and not vice-versa. The formation of seemless microstructure and the obtained resistance data reveal that the Au-Sn mu-joints with minimal height have tremendous potential for its application in the tight-pitch threedimensional chip integration and packaging.

  33. 7-mu m-thick NCF technology with low-height solder microbump bonding for 3D integration 査読有り

    Yuki Miwa, Kousei Kumahara, Sungho Lee, Rui Liang, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) 1453-1458 2020年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC32862.2020.00230  

    ISSN:0569-5503

    eISSN:2377-5726

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    High-density interconnections are highly required for 3D IC such as FPGA and image sensor applications. Fine-pitch interconnects using conventional solder microbumps are still required. To meet this requirements, low-height Cu/Sn microbumps are evaluated in this study. The thermal compression bonding with the low-height solder microbumps makes it challenging to fulfill high-viscous capillary underfill (CUF) into extremely small gaps between the chips stacked in layers. Here, we demonstrate to apply a 7-mu m-thick non-conductive film (NCF) to flip-chip bonding with the low-height solder microbumps. Compared with a CUF, the electrical characterization such as electromigration (EM) and leakage current of microbump daisy chains with the ultra-thin NCF was investigated with temperature cycle test (TCT) and unbiased HAST.

  34. Low-temperature multichip-to-wafer 3D integration based on via-last TSV with OER-TEOS-CVD and microbump bonding without solder extrusion 査読有り

    Kousei Kumahara, Rui Liang, Sungho Lee, Yuki Miwa, Mariappan Murugesan, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) 1199-1204 2020年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC32862.2020.00192  

    ISSN:0569-5503

    eISSN:2377-5726

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    This paper deals with multichip-to-wafer (MC2W) 3D stacking technologies based on via-last TSV integration. In this work, we verify the effectiveness of room-temperature CVD named OER (Ozone-Ethylene Radical generation)-TEOS-CVD (R) to deposit a TSV liner SiO2 layer. The film quality including dielectric constants is evaluated alternative to plasma-enhanced (PE)-TEOS-CVD SiO2. In addition, solid-solid inter-diffusion bonding of 3-mu m-thick Sn with 0.5-mu m-thick Au is demonstrated to achieve multiple multichip bonding for retinal prosthesis system fabrication with a 3D artificial retina chip. Low-temperature bonding at 190 degrees C is realized by the Au/Sn metallurgy. Good bondability is also obtained with the Au electrodes preliminarily exposed at high temperature. There are no Sn microbump extrusion, which is highly expected to be used for 3D-ICs with fine-pitch solder microbump interconnection.

  35. Impact of Electroless-Ni Seed Layer on Cu-Bottom-up Electroplating in High Aspect Ratio (>10) TSVs for 3D-IC Packaging Applications 査読有り

    Murugesan Mariappan, Mitsumasa Koyanagi, Takafumi Fukushima

    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) 1736-1741 2020年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC32862.2020.00271  

    ISSN:0569-5503

    eISSN:2377-5726

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    The electroless (EL) Ni layer conformally formed inside the high aspect ratio (AR, >10) through-Si-via (TSV) has been investigated for its role as seed layer in bottom-up Cu electroplating. From the electro-chemical adsorption monitoring data it was found that the adsorption (or accumulation) of additives onto the EL-Ni surface for bottom-up Cu electroplating was prodoundly suppressed when compared with the Ni seed layer depositied by PVD. A simple and viable two step process was proposed and demonstrated to overcome the problem, and we were able to successfully fill the TSVs (width similar to 10 mm, AR > 10) with by Cu-electroplating using the EL-Ni as seed as well as barrier layer. Thus, this low-cost, readily-scalable (both in wafer-size and volume) and CMOS compatible EL method for the formation of Ni barrier-cum-seed layer in the high AR TSVs for integration and packaging applications has tremendous potential to replace the high-cost PVD or CVD barrier and seed layers..

  36. Multilithic 3D and Heterogeneous Integration Using Capillary Self-Assembly

    Takafumi Fukushima

    2020 IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING CONFERENCE (EDTM 2020) 2020年

    出版者・発行元:IEEE

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    We have worked on multichip-to-wafer (MC2W) 3D and heterogeneous integration and packaging using capillary self-assembly (CSA) with liquid droplets. In this work, microbump bonding and direct bonding technologies in face-up and/or face-down fashion are discussed for 3D-IC fabrication including 3D interconnect formation. Here "non-transfer 3D stacking" like flip-chip bonding and "transfer stacking" called reconfigure-wafer-to-wafer using self-assembly and electrostatic (SAE) carrier are explained. In addition, CSA application in flexible hybrid electronics (FHE) and micro-LED display is introduced.

  37. RDL-first Flexible FOWLP Technology with Dielets Embedded in Hydrogel 査読有り

    Noriyuki Takahashi, Yuki Susumago, Sungho Lee, Yuki Miwa, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima

    2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020) 811-816 2020年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC32862.2020.00132  

    ISSN:0569-5503

    eISSN:2377-5726

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    A new flexible hybrid electronics (FHE) methodology using advanced RDL-first fan-out wafer-level packaging (FOWLP) technologies with dielets and hydrogel substrates is proposed. Hydrogels mainly consisting of water have excellent biocompatibility, high adaptability, and substance permeability, and they are expected for biomedical applications. In this work, we integrate Si LSI and mini-LED dielets in a hydrogel substrate on which fine-feature Au interconnections are formed in wafer-level processing. We characterize their electrical properties of the embedded dielets for biomedical applications.

  38. Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    IEEE Journal of the Electron Devices Society 8 1266-1271 2020年

    出版者・発行元:Institute of Electrical and Electronics Engineers (IEEE)

    DOI: 10.1109/jeds.2020.3025336  

    eISSN:2168-6734

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    © 2013 IEEE. Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This article reports the I-V, programming, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.

  39. PPG and SpO<inf>2</inf> Recording Circuit with Ambient Light Cancellation for Trans-Nail Pulse-Wave Monitoring System 査読有り

    Ryosuke Yabuki, Tetsu Tanaka, Zhengyang Qian, Kar Mun Lee, Bang Du, Filipe Alves Satake, Tasuku Fukushima, Hisashi Kino, Takafumi Fukushima, Koji Kiyoyama

    BioCAS 2019 - Biomedical Circuits and Systems Conference, Proceedings 2019年10月

    DOI: 10.1109/BIOCAS.2019.8919027  

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    © 2019 IEEE. In order to efficiently record the photoplethysmography (PPG) and apply it for peripheral oxygen saturation (SpO2) measurement, we developed a trans-nail pulse-wave monitoring system, which is able to record the PPG signal on nail-Tip without discomfort and any effects from sweat. This system includes PPG and SpO2 recording circuit (PPG/SpO2-RC) with ambient light cancellation (ALC) function and was fabricated in 1P6M 0.18 μm CMOS technology. It has a small area of about 1.7 mm2. The PPG/SpO2-RC mainly consists of an LED driver circuit, a PPG readout circuit, and a 500 x 500 μm2 photodiode (PD). LED driver circuit selectively drives three different wavelength LEDs. In the PPG readout circuit, an 86/96 dBΩ I/V converter, 20-80 dB programmable gain amplifiers, and LPF ensured the PPG signal being recorded using an appropriate gain for different individuals. On top of that, an ALC circuit was integrated into the PPG readout circuit to reduce noise from ambient light and preventing these signals from saturating the circuit. The PPG/SpO2-RC was evaluated, and the PPG signal and SpO2 were measured and calculated successfully, proving that it worked as it designed. In the future, the circuit will be integrated with other elements such as a Bluetooth module (BLE) in the trans-nail pulse-wave monitoring system.

  40. Impacts of Deposition Temperature and Annealing Condition on Ozone-Ethylene Radical Generation-TEOS-CVD SiO<inf>2</inf> for Low-Temperature TSV Liner Formation 査読有り

    Rui Liang, Sungho Lee, Yuki Miwa, Kousei Kumahara, Murugesan Mariappan, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 2019年10月

    DOI: 10.1109/3DIC48104.2019.9058843  

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    © 2019 IEEE. Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-Temperature process for TSV liner formation in the multichip-To-wafer (MCtW) process, we applied the low-Temperature SiO2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO2liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.

  41. Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal Processing 査読有り

    Koji Kiyoyama, Qian Zhengy, Hiroyuki Hashimoto, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 2019年10月

    DOI: 10.1109/3DIC48104.2019.9058856  

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    © 2019 IEEE. This paper describes a highly parallel analog signal processing method with three-dimensional (3-D) stacked neural network chip for convolutional and deep neural networks (CNNs and DNNs). The proposed chip has a stacked structure, which enables highly parallel mixed-signal operations like human brains with low power consumption. The product-sum operation using analog circuit in highly parallel calculation with low power supply current, but repeated calculations result in excessive noise (e.g.The offset voltage of the amplifier and 1/f noise, kT/C noise etc.) accumulation and degraded calculation accuracy. Therefore, analog signal processing with 3-D stacked multiple layers neural network chip require the noise reduction technique. In this design, correlated double sampling (CDS) is used to noise reduction technique with which reduce noise generated in the circuit. The proposed CDS circuit is designed with CMOS 0.18nm technology. As results of simulation analysis, it was confirmed that the CDS circuit reduced the offset voltage of composing amplifier and the noise voltages of the circuits placed before the CDS circuit to less than 1.25mV.

  42. Characterization of Low-Height Solder Microbump Bonding for Fine-Pitch Inter-Chip Connection in 3DICs 査読有り

    Yuki Miwa, Sungho Lee, Rui Liang, Kousei Kumahara, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 2019年10月

    DOI: 10.1109/3DIC48104.2019.9058841  

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    © 2019 IEEE. We have fabricated microbump daisy chains with a low-height solder thickness of 2.5 μm in order to evaluate flip-chip bonding capabilities. Electrical characteristics of the bonded microbumps in three-dimensionally stacked chips were compared between a very thin non-conductive film (NCF) and capillary underfill (CUF). The resulting I-V behaviors showed that the resistance of the daisy chain with the NCF was lower than that with the CUF, inDICating that the low-height solder microbumps with combination of the thin NCF can be a promising candidate for future fine-pitch inter-chip connection in 3DICs.

  43. Development of 3D-IC Embedded Flexible Hybrid System 査読有り

    Sungho Lee, Yuki Susumago, Zhengyang Qian, Noriyuki Takahashi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima

    IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 2019年10月

    DOI: 10.1109/3DIC48104.2019.9058880  

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    © 2019 IEEE. We have fabricated a new 3D-IC embedded flexible hybrid system (FHS) based on a Fan-Out Wafer-Level Packaging (FOWLP). The unique FHS structure is consisting of PDMS as a flexible substrate in which the 3D-IC with through-Si vias (TSVs) and microbumps are embedded. The mechanical and electrical properties of the 3D-IC embedded FHS are characterized by using repeated bending test with the TSV/microbump daisy chains. The new FHS can be expected to be used as high-performance wearable device systems for biomedical applications.

  44. Investigation of the Underfill with Negative-Thermal-Expansion Material to Suppress Mechanical Stress in 3D Integration System 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    IEEE 2019 International 3D Systems Integration Conference, 3DIC 2019 2019年10月

    DOI: 10.1109/3DIC48104.2019.9058838  

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    © 2019 IEEE. The three-dimensional (3D) integration process is a promising candidate to enhance electron-device performance. Typical 3D integration systems consist of vertically stacked several thin IC chips that are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, the coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect the CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. To suppress the local bending stress, we have proposed a novel underfill with negative-Thermal-expansion material. In this study, we investigated the characteristics of the negativethermal-expansion material surrounded by the matrix of the underfill.

  45. X-ray computed tomography studies on directed self-assembly formed vertical nanocylinders containing metals for 3D LSI applications—characterization technique-dependent reliability issues 査読有り

    M. Murugesan, A. Takeuchi, T. Fukushima, M. Koyanagi

    Japanese Journal of Applied Physics 58 (SB) SBBC05-SBBC05 2019年4月1日

    出版者・発行元:IOP Publishing

    DOI: 10.7567/1347-4065/ab02e2  

    ISSN:0021-4922

    eISSN:1347-4065

  46. Noise Propagation through TSV in Mixed-Signal 3D-IC and Investigation of Liner Interface with Multi-Well Structured TSV 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 222-224 2019年3月

    DOI: 10.1109/EDTM.2019.8731161  

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    © 2019 IEEE. The effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC, which has a stacked structure of digital and analog IC chips. The noise propagation through the TSV was measured with a ring-oscillator as a noise source. To investigate in detail, TSV-liner interface states were evaluated along depth direction using unique multi-well-structured TSVs and charge-pumping method. It was considered that the interface traps and non-conformal thickness of TSV liner increased the noise propagation among stacked chips.

  47. High-Thermoresistant Temporary Bonding Technology for Multichip-to-Wafer 3-D Integration With Via-Last TSVs

    Hideto Hashiguchi, Takafumi Fukushima, Mariappan Murugesan, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE Transactions on Components, Packaging and Manufacturing Technology 9 (1) 181-188 2019年1月

    出版者・発行元:Institute of Electrical and Electronics Engineers (IEEE)

    DOI: 10.1109/tcpmt.2018.2871764  

    ISSN:2156-3950

    eISSN:2156-3985

  48. Mechanical Characterization of FOWLPBased Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application 査読有り

    Yuki Susumago, Achille Jacquemond, Noriyuki Takahashi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima

    2019 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP 2019) 265-267 2019年

    出版者・発行元:IEEE

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    A new flexible hybrid electronics (FHE) approach is studied for integrating high-performance and scalable flexible systems at the wafer level. The unique structure is consisting of monocrystalline semiconductor dielets embedded in flexible substrates such as elastomers. Stress buffer layers (SBL) as a key material are inserted between inter-dielet wirings and the substrates to enhance wire reliability. The impact of the SBL properties on the bendability of the FHE systems is described in this work.

  49. Development of Eccentric Spin Coating of Polymer Liner for Low-Temperature TSV Technology With Ultra-Fine Diameter 査読有り

    Miao Xiong, Zhiming Chen, Yingtao Ding, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    IEEE ELECTRON DEVICE LETTERS 40 (1) 95-98 2019年1月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2018.2884452  

    ISSN:0741-3106

    eISSN:1558-0563

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    Through-silicon-vias (TSVs) with a diameter of 3 mu m and high aspect ratio of 15 are successfully fabricated based on a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget. A novel eccentric spin coating technique is proposed for liner formation, which greatly improves the wafer-level uniformity and reduces the bottom dielectric thickness of the vias located close to the center of the wafer. The measured results show that the fabricated TSVs exhibit low depletion capacitance of 33 fF, low leakage current of 2.2 pA at 20 V, and good barrier property against Cu diffusion even after annealing at 400 degrees C, indicating the feasibility of the proposed technique in high density and low area penalty 3-D large-scale integrated circuits.

  50. Development of eccentric spin coating of polymer liner for low-temperature TSV technology with ultra-fine diameter 査読有り

    Miao Xiong, Zhiming Chen, Yingtao Ding, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    IEEE Electron Device Letters 40 (1) 95-98 2019年1月

    DOI: 10.1109/LED.2018.2884452  

    ISSN:0741-3106

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    © 1980-2012 IEEE. Through-silicon-vias (TSVs) with a diameter of 3μm and high aspect ratio of 15 are successfully fabricated based on a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget. A novel eccentric spin coating technique is proposed for liner formation, which greatly improves the wafer-level uniformity and reduces the bottom dielectric thickness of the vias located close to the center of the wafer. The measured results show that the fabricated TSVs exhibit low depletion capacitance of 33 fF, low leakage current of 2.2 pA at 20 V, and good barrier property against Cu diffusion even after annealing at 400°C, indicating the feasibility of the proposed technique in high density and low area penalty 3-D large-scale integrated circuits.

  51. Investigation of TSV Liner Interface with Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC 査読有り

    Hisashi Kino, Takafumi Fukusima, Tetsu Tanaka

    IEEE Journal of the Electron Devices Society 7 1225-1231 2019年

    DOI: 10.1109/JEDS.2019.2936180  

    eISSN:2168-6734

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    © 2013 IEEE. Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.

  52. Mechanical Characterization of FOWLPBased Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application 査読有り

    Yuki Susumago, Achille Jacquemond, Noriyuki Takahashi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima

    2019 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP 2019) 265-267 2019年

    出版者・発行元:IEEE

    DOI: 10.23919/ICEP.2019.8733416  

    詳細を見る 詳細を閉じる

    A new flexible hybrid electronics (FHE) approach is studied for integrating high-performance and scalable flexible systems at the wafer level. The unique structure is consisting of monocrystalline semiconductor dielets embedded in flexible substrates such as elastomers. Stress buffer layers (SBL) as a key material are inserted between inter-dielet wirings and the substrates to enhance wire reliability. The impact of the SBL properties on the bendability of the FHE systems is described in this work.

  53. Mechanical and Electrical Characterization of FOWLP-Based Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application 査読有り

    Yuki Susumago, Qian Zhengyang, Achille Jacquemond, Noriyuki Takahashi, Hisashi Kino, Tetsu Tanaka, Takafumi Fukushima

    2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 2019-May 264-269 2019年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2019.00046  

    ISSN:0569-5503

    eISSN:2377-5726

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    A new trans-nail FHE (flexible hybrid electronics) system with photoplethysmographic (PPG) sensors is proposed and characterized from both aspects of mechanical and electrical properties in this study. The unique FHE structure is consisting of an elastomer as a flexible substrate in which Si LSI dielets having photodiode and LED driver circuits etc. are embedded based on a FOWLP concept. Stress buffer layers (SBLs) as a key material are inserted between interdielet wirings and the substrate to mitigate mechanical stress and enhance wire reliability. The impact of the Young's moduli of the SBLs on the repeated bendability of the FHE systems is described. In addition, we evaluate the electrical properties of the LSI dielets between before and after bending for comparison.

  54. Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration 査読有り

    Sungho Lee, Rui Liang, Yuki Miwa, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    PROCEEDINGS OF 2019 6TH INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D) 17-17 2019年

    出版者・発行元:IEEE

    DOI: 10.23919/LTB-3D.2019.8735115  

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    Impact of temporary bonding conditions and temporary adhesive properties on mechanical stresses in multichip thinning is evaluated for high-yield multichip-to-wafer (MC2W) heterogeneous 3D integration. It turned out that no sidewall covering of chips with a temporary adhesive gives low mechanical stress to the chip edge, leading to less chipping and cracking.

  55. Continuous Peripheral Blood Pressure Measurement with ECG and PPG Signals at Fingertips 査読有り

    Kar Mun Lee, Zhengyang Qian, Ryosuke Yabuki, Bang Du, Hisashi Kino, Takafumi Fukushima, Koji Kiyovama, Tetsu Tanaka

    2018 IEEE Biomedical Circuits and Systems Conference, BioCAS 2018 - Proceedings 2018年12月20日

    DOI: 10.1109/BIOCAS.2018.8584776  

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    © 2018 IEEE. A good habit of measuring blood pressure (BP) daily is helpful for us to stay healthy or to monitor hypertensive conditions. However, the conventional method of measuring BP using a pressure cuff has many weaknesses. In order to eliminate the use of this pressure cuff, we proposed a system using the pulse arrival time (PAT) to measure BP. This PAT can be measured using time difference between the R-peaks of electrocardiogram (ECG) and photoplethysmography (PPG) signals. In our system, we obtained these two signals by using our self-designed ECG and PPG sensors. Our sensors were fabricated in 0.18 μm CMOS technology with a small recording area of about 2.53 mm 2 and 6.25 mm 2 , respectively. Our ECG sensor has variable amplifying gains and can achieve a total maximum gain of 60 dB. Besides that, it has a high pass filter with wide cutoff frequencies between 0.1-200 Hz, and low pass filter with cutoff frequencies of 0.2-10 kHz. The design of our ECG circuit allows us to obtain the ECG signals using fingertips and without using a ground electrode. This compact system has the potential to become a wireless wearable in the future. The measured PAT was fitted into a mathematical model and cuff-less BP readings were obtained. A plot of reference BP using oscillometric cuff and cuff-less BP showed a good correlation of r = 0.83 for systolic blood pressure (SBP). The SBP and diastolic blood pressure (DBP) mean absolute difference for the system are 6.75 mmHg and 6.08 mmHg respectively, which fairly passed the strict standard set by IEEE. In the future, our system will be compared with the use of sphygmomanometer, which is the gold standard, to further evaluate its accuracies.

  56. Process Integration for FlexTrate <sup>TM</sup> 査読有り

    Tak Fukushima, Yuki Susumago, Hisashi Kino, Tetsu Tanaka, Arsalan Alam, Amir Hanna, Subramanian S. Iyer

    2018 International Flexible Electronics Technology Conference, IFETC 2018 2018年12月19日

    DOI: 10.1109/IFETC.2018.8584029  

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    © 2018 IEEE. We fabricate FlexTrate TM that is highly integrated bendable and/or rollable electronic systems in which various Si and/or III-V chips are embedded in elastomers and interconnected at the wafer level. This paper describes the process integration of the FlexTrate TM using massively parallel capillary self-assembly and a new single stress buffer layer technologies to form fine-pitch interconnection between the embedded neighboring chips and characterize the electrical/mechanical properties.

  57. Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration 査読有り

    Takafumi Fukushima, Arsalan Alam, Amir Hanna, Siva Chandra Jangam, Adeel Ahmad Bajwa, Subramanian S. Iyer

    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 8 (10) 1738-1746 2018年10月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TCPMT.2018.2871603  

    ISSN:2156-3950

    eISSN:2156-3985

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    A technological platform is established for scalable flexible hybrid electronics based on a novel fan-out wafer-level packaging (FOWLP) methodology. Small dielets are embedded in flexible substrates we call FlexTrate. These dielets can be interconnected through high-density wirings formed in wafer-level processing. We demonstrate homogeneous integration of 625 (25 by 25) 1-mm(2) Si dielets and heterogeneous integration of GaAs and Si dielets with various thicknesses in a biocompatible polydimethylsiloxane (PDMS). In this paper, 8-mu m-pitch die-to-die interconnections are successfully implemented over a stress buffer layer formed on the PDMS. In addition, coplanarity between the PDMS and embedded dielets, die shift concerned in typical die-first FOWLP, and the bendability of the resulting FlexTrate are characterized.

  58. TSV liner dielectric technology with spin-on low-k polymer 査読有り

    S. Lee, Y. Sugawara, M. Ito, H. Kino, T. Fukushima, T. Tanaka

    2018 International Conference on Electronics Packaging and iMAPS All Asia Conference, ICEP-IAAC 2018 346-349 2018年6月6日

    出版者・発行元:Institute of Electrical and Electronics Engineers Inc.

    DOI: 10.23919/ICEP.2018.8374320  

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    In this paper, a BCB (benzocyclobutene) resin is employed as a spin-on low-k polymer for TSV liner dielectrics. The BCB is perfectly covered on the sidewall of deep Si holes with a diameter of 8 μm and depth of 40 μm (aspect ratio: 5). The step coverage of the BCB is high and controllable by conditioning the spin rotation speed, spin-coating time, and deforming pressure to eliminate bubbles formed in the deep Si holes prior to spin-coating. Cu-TSVs with the BCB liner dielectric are successfully formed by the subsequent electro-less plated and electroplated Cu technologies. This cost-effective spin-on BCB technology will be applied to via-last TSV fabrication at low temperature below 250 C to give low-capacitance TSVs.

  59. Development of integrated photoplethysmographic recording circuit for trans-nail pulse-wave monitoring system 査読有り

    Zhengyang Qian, Yoshiki Takezawa, Kenji Shimokawa, Hisashi Kino, Takafumi Fukushima, Koji Kiyoyama, Tetsu Tanaka

    Japanese Journal of Applied Physics 57 (4) 2018年4月1日

    出版者・発行元:Japan Society of Applied Physics

    DOI: 10.7567/JJAP.57.04FM11  

    ISSN:1347-4065 0021-4922

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    Health monitoring and self-management have become increasingly more important because of health awareness improvement, the aging of population, and other reasons. In general, pulse waves are among the most useful physiological signals that can be used to calculate several parameters such as heart rate and blood pressure for health monitoring and self-management. To realize an automatic and real-time pulse-wave monitoring system that can be used in daily life, we have proposed a trans-nail pulse-wave monitoring system that was placed on the fingernail to detect photoplethysmographic (PPG) signals as pulse waves. In this study, we designed a PPG recording circuit that was composed of a 600 × 600 μm2 photodiode (PD), an LED driver with pulse wave modulation (PWM) and a low-frequency ring oscillator (RING), and a PPG signal readout circuit. The proposed circuit had a very small area of 2.2 × 1.1 mm2 designed with 0.18 μm CMOS technology. The proposed circuit was used to detect pulse waves on the human fingernail in both the reflection and transmission modes. Electrical characteristics of the prototype system were evaluated precisely and PPG waveforms were obtained successfully.

  60. Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    Japanese Journal of Applied Physics 57 (4) 2018年4月1日

    出版者・発行元:Japan Society of Applied Physics

    DOI: 10.7567/JJAP.57.04FE07  

    ISSN:1347-4065 0021-4922

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    Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. ATFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

  61. Capillary Self-Assembly Based Multichip-to-Wafer System Integration Technologies

    Takafumi Fukushima

    2018 INTERNATIONAL CONFERENCE ON MANIPULATION, AUTOMATION AND ROBOTICS AT SMALL SCALES (MARSS) 2018年

    出版者・発行元:IEEE

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    We have proposed and developed 3D integration technologies based on self-assembly using surface tension of liquid from 2005. In this paper, microbump bonding and bumpless bonding in face-up and/or face-down configurations are introduced for fine-pitch interconnect formation. In addition, "non-transfer stacking", in other word, flip-chip self-assembly and "transfer stacking" called reconfigure-wafer-to-wafer using SAE (Self-Assembly and Electrostatic) carrier are explained.

  62. Self-Assembly Technologies for FlexTrate (TM) 査読有り

    Takafumi Fukushima, Yuki Susumago, Hisashi Kino, Tetsu Tanaka, Arsalan Alam, Amir Hanna, Subramanian S. Iyer

    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) 1836-1841 2018年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2018.00275  

    ISSN:0569-5503

    eISSN:2377-5726

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    We have developed new flexible hybrid electronics (FHE) systems called FlexTrate (TM) that is high-performance and scalable flexible substrates embedding heterogeneous inorganic monocrystalline semiconductor dielets. In this work, a modified die-first FOWLP technology with surface tension driven multichip self-assembly is used for the fabrication of FlexTrate (TM). The detailed self-assembly for the FlexTrate (TM) application is described to precisely and highly integrate heterogeneous dielets embedded in PDMS as a flexible substrate in wafer-level processing.

  63. Study of Al-doped ZnO transparent stimulus electrode for fully implantable retinal prosthesis with three-dimensionally stacked retinal prosthesis chip 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    Sensors and Materials 30 (2) 225-234 2018年

    出版者・発行元:M Y U Scientific Publishing Division

    DOI: 10.18494/SAM.2018.1741  

    ISSN:0914-4935

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    To realize a three-dimensionally (3D) stacked retinal prosthesis chip having a large stimulus electrode area and a large photodiode area, the fundamental properties of an Al-doped ZnO transparent stimulus electrode were investigated in detail. The test samples were fabricated, and thin film property and stimulus electrode characteristics were also evaluated using several methods. It was clearly observed that both the crystallinity and transmittances of an Al-doped ZnO thin film were dependent on the substrate temperature during thin-film formation. A better crystallinity and a transmittance of more than 85% in the visible range were achieved for the Al-doped ZnO thin film with a substrate temperature of 200 ℃. Furthermore, good electrochemical impedance characteristics and adequate charge injection capacity (CIC) values of 0.07 mC/cm2 were obtained to elicit visual sensations. Consequently, Al-doped ZnO has the possibility of becoming the transparent stimulus electrode for a 3D stacked retinal prosthesis chip.

  64. Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs 査読有り

    Hisashi Kino, Sungho Lee, Yohei Sugawara, Takafumi Fukushima, Tetsu Tanaka

    2018 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC) 135-137 2018年

    出版者・発行元:IEEE

    DOI: 10.1109/IITC.2018.8430390  

    ISSN:2380-632X

    eISSN:2380-6338

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    Through-silicon-via (TSV) with polymer liner has attracted considerable attention because a polymer liner has low dielectric constant and good step coverage along the TSV surface, and it can suppress the TSV-induced stress. A polyimide (PI) is used as the polymer liner of TSV. However, there is a modulation of the parasitic capacitance present between TSV metal and Si substrate due to its high polar character. Therefore, in this paper, we propose the deployment of benzocyclobutene (BCB) and polybenzoxazole (PBO) which consists of no-polar groups as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structures with PI, BCB or PBO liners were fabricated and evaluated. In the case of BCB and PBO liners, remarkable hysteresis suppressions of the C-V curves was observed as compared to that of the PI liner. These results indicate that polar character is one of the most important characters for suppression of the capacitance modulation around TSVs and the detrapped-charge-induced signal noise. Then, BCB and PBO is a promising liner material of TSV for realizing highperformance and high-reliability three-dimensional stacked ICs.

  65. Self-Assembly and Electrostatic Carrier Technology for Via-Last TSV Formation Using Transfer Stacking-Based Chip-to-Wafer 3-D Integration 査読有り

    Hideto Hashiguchi, Takafumi Fukushima, Hiroyuki Hashimoto, Ji-Cheol Bea, Mariappan Murugesan, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 64 (12) 5065-5072 2017年12月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2017.2767598  

    ISSN:0018-9383

    eISSN:1557-9646

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    A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion.

  66. Temporary Bonding and De-Bonding for Multichip-to-Wafer 3D Integration Process Using Spin-on Glass and Hydrogenated Amorphous Si 査読有り

    M. Murugesan, T. Fukushima, M. Koyanagi

    Proceedings - Electronic Components and Technology Conference 1237-1242 2017年8月1日

    出版者・発行元:Institute of Electrical and Electronics Engineers Inc.

    DOI: 10.1109/ECTC.2017.253  

    ISSN:0569-5503

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    Temporary bonding and de-bonding techniques using respectively spin-on glass (SOG) and hydrogenated amorphous-Si (a-Si:H) have been examined for multichip-to-wafer three-dimensional (3D) integration process. In this study, a 280 um-thick known good dies of 5 mm × 5 mm in size were temporarily bonded to a pre-deposited (a-Si:H (100 nm) and SOG (400 nm)) support glass wafer. After completing the die thinning and TSV formation processes, the dies were de-bonded using 248 nm excimer laser. The surfaces of de-bonded chip/wafer and glass substrate were meticulously investigated using x-ray photoelectron spectroscopy (XPS). From C1s, O1s, and Si1s XPS data, it is inferred that the de-bonding occurs in the a-Si:H layer. It reveals that the interface between the SOG and a-Si:H layer was highly intact, and the bonding strength is good enough to withstand the harsh environment during die/wafer thinning and TSV formation processes.

  67. Remarkable Suppression of Local Stress in 3D IC by Manganese Nitride-Based Filler with Large Negative CTE 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    Proceedings - Electronic Components and Technology Conference 1523-1528 2017年8月1日

    出版者・発行元:Institute of Electrical and Electronics Engineers Inc.

    DOI: 10.1109/ECTC.2017.209  

    ISSN:0569-5503

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    A local bending stress is induced by coefficient of thermal expansion (CTE) mismatch between underfill material and metal microbumps in three-dimensional IC (3D IC). A high concentration of filler in underfill is effective to suppress the local bending stress. However, it is difficult to apply high concentration of filler due to fine pitch microbumps. On the other hand, manganese nitride-based compound has large negative CTE compared with conventional negative-CTE materials. In this study, we have investigated the effect of manganese nitride-based filler on local bending stress induced by CTE mismatch between underfill and metal microbumps in 3D IC. We observed that manganese nitride-based filler can decrease CTE of underfill compared with conventional silica-based filler. This result indicated that manganese nitride-based filler can reduce keep-out-zone (KOZ) in 3D IC by local bending stress suppression.

  68. Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2016 IEEE International 3D Systems Integration Conference, 3DIC 2016 2017年7月5日

    出版者・発行元:Institute of Electrical and Electronics Engineers Inc.

    DOI: 10.1109/3DIC.2016.7970031  

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    Three-dimensional IC (3D IC) is a promising method to enhance IC performance. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we propose a novel underfill with negative-CTE filler which can suppress the local bending stress in 3D IC.

  69. Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission 査読有り

    Hisashi Kino, Masataka Tashiro, Yohei Sugawara, Seiya Tanikawa, Takafumi Fukushima, Tetsu Tanaka

    IITC 2017 - 2017 IEEE International Interconnect Technology Conference 2017年7月5日

    出版者・発行元:Institute of Electrical and Electronics Engineers Inc.

    DOI: 10.1109/IITC-AMC.2017.7968936  

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    Through-Si-via (TSV) with polymer liner formation has attracted considerable attention because a polymer liner can be formed easily by spin coating, and it has low dielectric constant and good coverage along the TSV surface. A polyimide (PI) was used as the polymer liner of TSV. However, there is a high charge-trap density in the PI layer. These charge traps leads to modulation of the parasitic capacitance present between the TSV metal and the Si substrate. Therefore, in this paper, we propose the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structure was fabricated with PBO and PI liners. Further, capacitance-voltage (C-V) characteristics of the fabricated MOS capacitor were evaluated. In case of the PBO liner, remarkable suppression of the C-V curve shift was observed as compared to that of the PI liner. These results indicate that the PBO is a promising TSV liner material for realizing high-performance, high-reliability, and low-cost three-dimensional stacked ICs.

  70. 3-D Sidewall Interconnect Formation Climbing Over Self-Assembled KGDs for Large-Area Heterogeneous Integration 査読有り

    Takafumi Fukushima, Akihiro Noriki, Jichoel Bea, Mariappan Murugesan, Hisashi Kino, Koji Kiyoyama, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 64 (7) 2912-2918 2017年7月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2017.2705562  

    ISSN:0018-9383

    eISSN:1557-9646

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    Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately 20 mu m) climbing over 100-mu m-thick self-assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly 10 mu m are successfully formed across polyimide slopes formed on the sidewall of self-assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-assembled chips.

  71. FlexTrateTM Characterization 査読有り

    T. Takafumi, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, S. S. Iyer

    2017 FLEX 2017年6月

  72. Directed Self-Assembly Patterning for 3D LSI 招待有り

    Takafumi Fukushima, Mitsumasa Koyanagi

    INC13 Workshop 2017年5月9日

  73. Heterogeneous Integration with High-Performance and Scalable Substrates: Si-IF (Interconnect Fabric) and FlexTrateTM 査読有り

    T. Fukushima, A. Bajwa, S. S. Iyer

    Advancing Microelectronics Magazine 44 (2) 6-11 2017年5月

  74. Development of Si neural probe with piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces 査読有り

    Takuya Harashima, Takumi Morikawa, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    Japanese Journal of Applied Physics 56 (4) 04CM04-1-04CM04-4 2017年4月1日

    出版者・発行元:Japan Society of Applied Physics

    DOI: 10.7567/JJAP.56.04CM04  

    ISSN:1347-4065 0021-4922

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    A Si neural probe is one of the most important tools for neurophysiology and brain science because of its various functions such as optical stimulation and drug delivery. However, the Si neural probe is not robust compared with a metal tetrode, and could be broken by mechanical stress caused by insertion to the brain. Therefore, the Si neural probe becomes more useful if it has a stress sensor that can measure mechanical forces applied to the probe so as not to be broken. In this paper, we proposed and fabricated the Si neural probe with a piezoresistive force sensor for minimally invasive and precise monitoring of insertion forces. The fabricated piezoresistive force sensor accurately measured forces and successfully detected insertion events without buckling or bending in the shank of the Si neural probe. This Si neural probe with a piezoresistive force sensor has become one of the most versatile tools for neurophysiology and brain science.

  75. Evaluation of insertion characteristics of less invasive Si optoneural probe with embedded optical fiber 査読有り

    Takumi Morikawa, Takuya Harashima, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    JAPANESE JOURNAL OF APPLIED PHYSICS 56 (4) 04CM08-1-04CM08-4 2017年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.7567/JJAP.56.04CM08  

    ISSN:0021-4922

    eISSN:1347-4065

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    A less invasive Si optoneural probe with an embedded optical fiber was proposed and successfully fabricated. The diameter of the optical fiber was completely controlled by hydrogen fluoride etching, and the thinned optical fiber can propagate light without any leakage. This optical fiber was embedded in a trench formed inside a probe shank, which causes less damage to tissues. In addition, it was confirmed that the optical fiber embedded in the probe shank successfully irradiated light to optically stimulate gene transfected neurons. The electrochemical impedance of the probe did not change despite the light irradiation. Furthermore, probe insertion characteristics were evaluated in detail and less invasive insertion was clearly indicated for the Si optoneural probe with the embedded optical fiber compared with conventional optical neural probes. This neural probe with the embedded optical fiber can be used as a simple and easy tool for optogenetics and brain science. (C) 2017 The Japan Society of Applied Physics

  76. Improving the barrier ability of Ti in Cu through-silicon vias through vacuum annealing 査読有り

    Murugesan Mariappan, JiChel Bea, Takafumi Fukushima, Eiji Ikenaga, Hiroshi Nohira, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 56 (4) 2017年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.7567/JJAP.56.04CC08  

    ISSN:0021-4922

    eISSN:1347-4065

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    Suppressing leak current and blocking Cu diffusion into active Si from Cu through-silicon vias (TSVs) are important requirements for enhancing three-dimensional (3D) LSI performance and reliability. We have proposed and confirmed a cost effective means of enhancing the barrier property of sputtered Ti in high-aspect-ratio Cu-TSVs by simple vacuum annealing at 400 degrees C for 20 min. The self-formed amorphous TiSi2 at the interface between dielectric SiO2 (along the TSV side-wall) and barrier Ti layer is found to play a positive role in improving the leak current characteristics. As-formed TiSix was partially converted into TiO2 and SiO2 during the vacuum annealing above 200 degrees C, and nearly vanished after annealing at 400 degrees C. The immense importance of 400 degrees C vacuum-annealing is not only in terms of the improvement in the barrier characteristics of the Ti layer, but also it is being a prerequisite for preventing Cu popup in 3D-LSI. Both the X-ray photoelectron spectroscopy (XPS) and current-voltage (I-V) data clearly reveal that this simple vacuum annealing of Cu-TSVs at 400 degrees C has tremendous potential for implementation in cost-effective via-last 3D integration. (C) 2017 The Japan Society of Applied Physics

  77. 半導体微細加工技術を用いた高機能シリコン神経プローブの開発

    原島 卓也, 森川 拓実, 木野 久志, 福島 誉史, 坂本 一寛, 片山 統裕, 虫明 元, 田中 徹

    平成28年度文部科学省新学術領域研究 学術研究支援基盤形成 先端モデル動物支援プラットフォーム 成果発表会 プログラム・抄録 66-66 2017年2月6日

  78. 光ファイバ埋め込みシリコンオプト神経プローブの開発

    森川 拓実, 原島 卓也, 木野 久志, 福島 誉史, 坂本 一寛, 片山 統裕, 虫明 元, 田中 徹

    平成28年度文部科学省新学術領域研究 学術研究支援基盤形成 先端モデル動物支援プラットフォーム 成果発表会 プログラム・抄録集 68-68 2017年2月6日

  79. 経爪型集積化光電式容積脈波計測システムの開発 査読有り

    銭 正ヨウ, 竹澤 好樹, 下川 賢士, 伊藤 圭汰, 西野 悟, 清山 浩司, 田中 徹

    生体医工学 55 (5) 464-464 2017年

    出版者・発行元:公益社団法人 日本生体医工学会

    DOI: 10.11239/jsmbe.55Annual.464  

    詳細を見る 詳細を閉じる

    <p>"脈拍は健康状態の指標として非常に重要であり、日常的に脈拍を計測できることが望ましい。現在、指輪型や腕時計型など種々のウェアラブルPPG (Photoplethysmography)計測装置が提案されている[1,2]。これはLEDを光源とする光を生体表面に入射し、脈拍に応じて変化する血量を光の反射・吸収量の変化としてフォトダイオード(PD)で検出することで脈拍の情報を得るものである。本研究はLED ドライバ回路、光電変換用PD、PPG信号処理回路を1チップに集積し、小面積と可搬性を兼ね備えた集積化PPG計測システムを開発することを目的とする。また、本システムを用いて爪下の血管から正確かつ簡便な脈波計測を実現することを目指す。今回設計した計測回路には、LEDドライバ、600μm角のPD、I/V コンバータ、20~40 dBまで4段階増幅可能な増幅器、高周波ノイズを除去するLPF、デジタル信号に変換するADCを搭載している。この計測回路を0.18μmCMOS技術を用いて試作し、要素回路が正常動作していることを確認した。回路の詳細な測定結果等は学会大会にて発表する。[1] 石井他, 第55回日本生体医工学会大会3T6-2-9 (2016)。[2] Yu Sun et. al., IEEE Trans. on Biomed. Eng., Vol. 63, No. 3, 2016."</p>

  80. Feasibility Study on Ultrafine-Pitch Cu-Cu Bonding Using Directed Self-Assembly (DSA) 査読有り

    M. Murugesan, T. Fukushima, K. Mori, H. Hashimoto, Jichel Bea, M. Koyanagi

    2017 5TH INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D) 44-44 2017年

    出版者・発行元:IEEE

    DOI: 10.23919/LTB-3D.2017.7947440  

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    A feasibility study was carried out for self-formation of metal wiring between LSI chips containing ultrafine-pitch Cu landing pads by employing a new concept of directed self-assembly (DSA) phenomena. Preliminary results suggest that it is highly feasible to electrically interconnect two LSI chips having Cu landing pads at 3 mu m pitch interval. Electrical contact between the flip-chip bonded dies was self-formed by dispersed Sn nano-dots in PS-b-PMMA (2:1) copolymer mixture after vacuum annealing at 280 degrees C.

  81. “FlexTrate®” - Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Using FOWLP 査読有り

    Tak Fukushima, Arsalan Alam, Saptadeep Pal, Zhe Wan, Siva Jangam, Goutham Ezhilarasu, Adeel Bajwa, Subramanian Iyer

    ECTC 2017, The 67th Electronic Components and Technology Conference 649-654 2017年

    出版者・発行元:None

    DOI: 10.1109/ECTC.2017.226  

    ISSN:0569-5503

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    ECTC 2017, The 67th Electronic Components and Technology Conference

  82. Heterogeneous Integration at Fine Pitch (2-10 μm) Using Thermal Compression Bonding 査読有り

    Adeel Ahmad Bajwa, SivaChandra Jangam, Saptadeep Pal, Niteesh Marathe, Tingyu Bai, Takafumi Fukushima, Mark Goorsky, Subramanian Iyer

    ECTC 2017, The 67th Electronic Components and Technology Conference 1276-1284 2017年

    出版者・発行元:None

    DOI: 10.1109/ECTC.2017.240  

    ISSN:0569-5503

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    ECTC 2017, The 67th Electronic Components and Technology Conference

  83. A New Flexible Device Integration Technology Based on Fan-Out Wafer-Level Packaging 査読有り

    T. Takafumi, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, S. S. Iyer

    Printed Electronics USA in IDTechEx show 2016年11月16日

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    Printed Electronics USA in IDTechEx show, Nov. 16-17, 2016, Santa Clara, CA, Academic Posters

  84. FlexTrate™: High Interconnect Density Fan-Out Wafer Level Processing for Flexible Bio-compatible Electronics 招待有り

    T. Fukushima, A. Alam, S. Pal, Z. Wan, S. C. Jangam, G. Ezhilarasu, A. Bajwa, S. S. Iyer

    NBMC (Nano-Bio Manufactuuring Consortium) Workshop: Blood, Sweat and Tears III 2016年11月2日

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    NBMC (Nano-Bio Manufactuuring Consortium) Workshop: Blood, Sweat and Tears III

  85. Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration 査読有り

    Takafumi Fukushima, Hideto Hashiguchi, Hiroshi Yonekura, Hisashi Kino, Mariappan Murugesan, Ji-Chel Bea, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    Micromachines 7 (10) 184-1-184-18 2016年10月

    出版者・発行元:MDPI AG

    DOI: 10.3390/mi7100184  

    ISSN:2072-666X

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    Plasma-and water-assisted oxide-oxide thermocompression direct bonding for a self-assembly based multichip-to-wafer (MCtW) 3D integration approach was demonstrated. The bonding yields and bonding strengths of the self-assembled chips obtained by the MCtW direct bonding technology were evaluated. In this study, chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PE-CVD) as a MCtW bonding interface was mainly employed, and in addition, wafer-to-wafer thermocompression direct bonding was also used for comparison. N-2 or Ar plasmas were utilized for the surface activation. After plasma activation and the subsequent supplying of water as a self-assembly mediate, the chips with the PE-CVD oxide layer were driven by the liquid surface tension and precisely aligned on the host wafers, and subsequently, they were tightly bonded to the wafers through the MCtW oxide-oxide direct bonding technology. Finally, a mechanism of oxide-oxide direct bonding to support the previous models was discussed using an atmospheric pressure ionization mass spectrometer (APIMS).

  86. Development of Si Neural Probe with Piezoresistive Force Sensor for Insertion Force Monitoring 査読有り

    Takuya Harashima, Takumi Morikawa, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    JSAP 2016 International Conference on Solid State Devices and Materials 409-410 2016年9月29日

  87. Insertion Characteristics Evaluation of Si Opto-Neural Probe with Embedded Optical fiber 査読有り

    Takumi Morikawa, Takuya Harashima, Takafumi Fukushima, Hisashi Kino, Tetsu Tanaka

    JSAP 2016 International Conference on Solid State Devices and Materials 389-390 2016年9月28日

  88. Evaluation of Depth-dependent TSV-liner Interface States Using Multi-well Structure TSV and Charge Pumping Technique 査読有り

    Yohei Sugawara, Hisashi Kino, Takahumi Fukushima, Kang-Wook Lee, Mitsumasa Koyanagi, Tetsu Tanaka

    JSAP 2016 International Conference on Solid State Devices and Materials 467-468 2016年9月27日

  89. 半導体ウエハへの三次元配線加工:TSVと狭ピッチ電極を中心に 招待有り 査読有り

    福島誉史, 李康旭, 田中徹, 小柳光正

    表面技術 小特集: シリコンウエハの表面処理 67 (8) 414-420 2016年8月1日

    DOI: 10.4139/sfj.67.414  

  90. Heterogeneous 3-D Integration Using Self-Assembly and Electrostatic Bonding 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka

    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 6 (7) 1002-1008 2016年7月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TCPMT.2016.2575070  

    ISSN:2156-3950

    eISSN:2156-3985

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    To overcome various concerns caused by scaling down the device size in future Large Scale Integrated Circuits (LSIs), it is indispensable to introduce a new concept of heterogeneous 3-D integration in which various kinds of device chips with different sizes, different devices, and different materials are vertically stacked. To achieve such heterogeneous 3-D integration, a key technology of self-assembly and electrostatic bonding has been developed. Exploring new devices for the Internet of Things, we have fabricated several kinds of heterogeneous 3-D LSIs called superchip by stacking compound semiconductor device chip, photonic device chip, and spintronic device chip on CMOS device chips using self-assembly and electrostatic bonding. Furthermore, a new system integration technology using a large-area substrate has been developed to reduce the cost of 2.5-D/3-D system module. A 3-D-stacked image sensor system module for automatic driving vehicle has been fabricated using this technology.

  91. Influence of Cu-TSVs, CuSnand PI- Microbumps on Vertically Stacked 20 Micron-Thick DRAM Chips 査読有り

    Murugesan Mariappan, JiChel Bea, Hiroyuki Hashmoto, KangWook Lee, Mitsumasa Koyanagi, Takafumi Fukushima, Seiya Tanikawa, Tetsu Tanaka

    Proceedings of the ECTC 2016 50-55 2016年6月1日

  92. Capacitance characteristics of low-k low-cost CVD grown polyimide liner for high-density Cu through-Si-via in three-dimensional LSI 査読有り

    Mariappan Murugesan, Fukushima Takafumi, Bea Ji-Chel, Hashimoto Hiroyuki, Koyanagi Mitsumasa

    Jpn. J. Appl. Phys. 55 (4S) 04EC12-04EC12 2016年4月1日

    出版者・発行元:Institute of Physics

    DOI: 10.7567/jjap.55.04ec12  

    ISSN:0021-4922

    eISSN:1347-4065

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    Minimization of the parasitic capacitance arising from Cu–through-Si-vias (TSVs) has been rigorously considered in order to enhance the performances of three-dimensional (3D) LSIs. We have systematically investigated the role of chemical vapor deposited (CVD) polyimide (PI) liner in Cu-TSVs in reducing the TSV capacitance. It is confirmed that CVD grown PI greatly helps to reduce the TSV capacitance as compared to the conventional PECVD-SiO<inf>2</inf>liner. In addition to that the presence of very small hysteresis and a negligible flat-band voltage shift along the voltage axis confirms the suitability of PI liner as dielectric in the Cu-TSVs, if it were operated below the bias voltages of ±20 V. In over all, the large reduction in capacitance along with the conformal deposition of PI in the TSVs having less than 3 µm-width with aspect ratios greater than 10 reveals that CVD grown PI has the potential application in the future 3D-LSIs with highly scaled TSV.

  93. Evaluation of in-plane local stress distribution in stacked IC chip using dynamic random access memory cell array for highly reliable three-dimensional IC 査読有り

    Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    JAPANESE JOURNAL OF APPLIED PHYSICS 55 (4) 2016年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.7567/JJAP.55.04EC07  

    ISSN:0021-4922

    eISSN:1347-4065

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    As three-dimensional (3D) ICs have many advantages, IC performances can be enhanced without scaling down of transistor size. However, 3D IC has mechanical stresses inside Si substrates owing to its 3D stacking structure, which induces negative effects on transistor performances such as carrier mobility changes. One of the mechanical stresses is local bending stress due to organic adhesive shrinkage among stacked IC chips. In this paper, we have proposed an evaluation method for in-plane local stress distribution in the stacked IC chips using retention time modulation of a dynamic random access memory (DRAM) cell array. We fabricated a test structure composed of a DRAM chip bonded on a Si interposer with dummy Cu/Sn microbumps. As a result, we clarified that the DRAM cell array can precisely evaluate the in-plane local stress distribution in the stacked IC chips. (C) 2016 The Japan Society of Applied Physics

  94. Study of Vacuum-Assisted Spin Coating of Polymer Liner for High-Aspect-Ratio Through-Silicon-Via Applications 査読有り

    Yangyang Yan, Yingtao Ding, Takafumi Fukushima, Kang-Wook Lee, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 6 (4) 501-509 2016年4月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TCPMT.2016.2514365  

    ISSN:2156-3950

    eISSN:2156-3985

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    This paper provides a new approach for the formation of polymer liner for low-k high-aspect-ratio through-silicon-vias involved in via-last backside-via 3-D integration applications. The approach mentioned, referred to as vacuum-assisted spin coating technique in this paper, is formed by combining a conventional spin coating technique and a vacuum treatment. Silicon blind vias with a diameter of 6 mu m and an aspect ratio of similar to 8 were conformably coated on their sidewall with polyimide liner with the minimum step coverage similar to 30% by this approach. Impacts of via geometric parameters and wafer sizes on step coverage were investigated. Electrical characteristics were evaluated with a trench capacitor structure of which the insulator layer was formed by the vacuum-assisted spin coating technique. The minimum capacitance density of 5.3 nF/cm(2) and the leakage current density of similar to 3 nA/cm(2) at a biased voltage of 5 V were obtained. The proposed vacuum-assisted spin coating technique is a simple, feasible, and cost-effective approach for 3-D integration applications.

  95. Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC 査読有り

    Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Youhei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    JAPANESE JOURNAL OF APPLIED PHYSICS 55 (4) 04EC03-1-04EC03-4 2016年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.7567/JJAP.55.04EC03  

    ISSN:0021-4922

    eISSN:1347-4065

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    A three-dimensional stacked IC (3D IC) is a one of the promising structures for enhancing IC performances. A 3D IC consists of several materials such as a Si substrate, metal for through Si via (TSV) and microbump, organic adhesive called the underfill, and so on. These materials generate a coefficient of thermal expansion (CTE) mismatch. On the other hand, heat is generated in the Si substrate during circuit operation and in the environment outside 3D IC, for example. Both the CTE mismatch and heat generation induce local stress caused by expansion of the underfill injected around metal microbumps. In this paper, we report our investigation results of the effects of adhesive expansion on transistor performances by finite element method (FEM) simulation and measurement of transistor characteristics. (C) 2016 The Japan Society of Applied Physics

  96. Evaluation of In-plane Local Bending Stress Distribution with DRAM Cell Array for Highly Reliable 3D IC 査読有り

    Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    Japanese Journal of Applied Physics 55 (4S) 04EC07-1-04EC07-4 2016年3月17日

    DOI: 10.7567/JJAP.55.04EC07  

  97. Impact of Chip-Edge Structures on Alignment Accuracies of Self-Assembled Dies for Microelectronic System Integration 査読有り

    Yuka Ito, Takafumi Fukushima, Hisashi Kino, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    JOURNAL OF MICROELECTROMECHANICAL SYSTEMS 25 (1) 91-100 2016年2月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/JMEMS.2015.2480787  

    ISSN:1057-7157

    eISSN:1941-0158

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    The self-assembly of known good dies on hosting substrates using liquid surface tension is a promising technology to create highly integrated 3-D and heterogeneous microelectronic systems. In this paper, we investigate the effects of the edge structures of self-assembled chips on alignment accuracies. Nine types of 100-mu m-thick Si chips (3 mm x 3 mm) with and without step geometries on their hydrophilic or hydrophobic peripheries are self-assembled onto hydrophilic assembly sites formed on planar-and plateau-type host substrates. When hydrophobic peripheries with step geometries are applied to both the edges of chips and assembly sites formed on substrates, the resulting average alignment accuracy is 300 nm. Total accuracy variation within 2 mu m is realized by using either chip or substrate having 10-mu m-height step structures with hydrophobic edges. We obtain a high tolerance for initial offsets indicating positioning misalignment prior to chip release, with the plateau-type substrates and the chips having hydrophobic step structures at the edges. These chips are precisely self-assembled, even under a large initial offset of 1.5 mm in a horizontal direction to both the substrates. The extremely large offset is comparable with 50% of the side length of the 3-mm-square chip. On the other hand, the chips formed by an accurate saw dicing that gives high chip-size accuracies as designed exhibit high alignment accuracies and tolerances when compared with the chips with the hydrophobic step structures and the chips formed by plasma dicing, which offer a large pseudo step with a height of 100 mu m. [2014-0298]

  98. New multichip-to-wafer 3D integration technology using Self-Assembly and Cu nano-pillar hybrid bonding 査読有り

    M. Koyanagi, K. W. Lee, T. Fukushima, T. Tanaka

    2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings 338-341 2016年

    出版者・発行元:Institute of Electrical and Electronics Engineers Inc.

    DOI: 10.1109/ICSICT.2016.7998914  

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    New 3D integration technology using self-assembly and Cu nano-pillar hybrid bonding are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Many known good dies (KGDs) are simultaneously self-assembled with a high alignment accuracy making use of liquid surface tension in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier and electrostatically bonded by applying a voltage to bipolar electrodes on the SAE carrier. The self-assembled dies on the carrier are simultaneously transferred to another wafer or interposer wafer by electrostatically debonding the carrier wafer after Cu nano-pillar hybrid bonding of self-assembled dies.

  99. Impact of Interconnections on Vertically Stacked 20 mu m-thick DRAM Chips 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, H. Hashimoto, M. Koyanagi, S. Tanikawa, T. Tanaka

    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 50-55 2016年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC.2016.255  

    ISSN:0569-5503

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    Effect of thermo-mechanical stress (TMS) originating from CuSn micro-bumps (mu-bumps) and Cu through-Si-vias (TSVs) on the retention characteristics of 20 mu m-thick, vertically stacked dynamic random access memory (DRAM) chip has been investigated. At cumulative probability of 50 %, the retention period decreased nearly 47% for the DRAM chip having thickness value of 20 mu m as compared to the retention period of 200 mu m-thick DRAM chip. Annealing at 300 degrees C, a compressive stress value of -200 MPa caused by Cu-TSVs was observed as the remnant stress at the periphery of the keep-out-zone, and faded quickly by moving away from the keep-out-zone. We did observe tle dependency of DRAM retention time on the TMS caused by TSVs. In the case of mu-bump, we observed a large amount of tensile stress (&gt; +300 MPa) on the back-side of DRAM chip at right above the CuSn mu-bumps, and it led to a crack in the DRAM chip. As compared to CuSn mu-bumps, the polyimide dummy mu-bumps present in between two chip layers induced less amount of residual stress in the DRAM chip.

  100. Non-Conductive Film Underfill for 3D Integration of 20 mu m-Thick LSI Wafers with Fine Cu-TSVs 査読有り

    M. Murugesan, J. C. Bea, M. Koyanagi, Y. Ito, T. Fukushima, T. Tanaka

    2016 27TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC) 466-471 2016年

    出版者・発行元:IEEE

    ISSN:1078-8743

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    The beneficial role played by non-conductive film (NCF) under-fill (UF) compared with the conventional capillary under fill (CUF) is meticulously investigated for the reliability issues in high-density 3D-integration at die/wafer-level. The NCF with co-efficient of thermal expansion (CTE) value of 35 ppm/degrees C tremendously reduces the local deformation of 20 mu m-thick three-dimensionally (3D)-stacked LSI die/wafer. This reduces the local mechanical stress in thinned 3D-LSI by nearly 5 times as against the CUF with the CTE value of 60 - 70 ppm/degrees C. Both mu-RS and mu-XRD data showed only similar to 250 MPa of tensile stress on the back surface of 20 mu m-thick stacked die/wafer with NCFUF, whereas it was more than five-times larger (similar to 1400 MPa) for CUF. mu-XRD data illustrates that the cause for residual stress in the bump-space region and above the mu-bump are respectively due to the lattice tilt and change in lattice space.

  101. Back-Via 3D Integration Technologies by Temporary Bonding with Thermoplastic Adhesives and Visible-Laser Debonding 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, H. Hashimoto, S. H. Lee, M. Motoyoshi, T. Tanaka, K. W. Lee, M. Koyanagi

    2016 International Conference on Electronics Packaging (ICEP) 265-269 2016年

    出版者・発行元:IEEE

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    Back-via three-dimensional (3D) integration using multiple thin-wafer transfer processes has been developed at GINTI, Tohoku University, where visible laser was employed for wafer debonding. The potential advantages of laser debonding are (i) the realization of ultra-thin wafer releasing with less stress as compared to the conventional thermal and chemical debonding methods, and (ii) no adhesive residues were left on the thinned wafer surface owing to their excellent solubility in solvents. The edge-trimming width and depth for Si before temporary bonding and the temporary bonding parameters using thermo-plastic adhesives were carefully investigated and optimized, in order to avoid any undesirable effects in background thin wafers. Through-Si-Vias with a diameter of 5-15 mu m were formed by masking the via patterns (using i-line, back-side-alignment) on the SiO2 surface of the back-ground side of 30 - 50 mu m-thick LSI wafer that was temporarily bonded to the support glass, followed by selective deep-reactive-ion-etching of SiO2, Si, and bottom SiO2, and subsequently barrier and seed layers deposition and via filling. Using laser debonding technique, the thinned Si wafers with Cu-vias were transferred to the other glass with different temporary adhesive. The observed low resistance values from the I-V data for 5000 Cu-via daisy chain reveals that the proposed back-via 3D integration using laser debonding is now ready for industrial use.

  102. Novel Hybrid Bonding Technology Using Ultra-High Density Cu Nano-Pillar for Exascale 2.5D/3D Integration 査読有り

    Kangwook Lee, Jichel Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE ELECTRON DEVICE LETTERS 37 (1) 81-83 2016年1月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2015.2502584  

    ISSN:0741-3106

    eISSN:1558-0563

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    We propose a novel hybrid bonding technology with a high stacking yield using ultra-high density Cu nanopillar (CNP) for exascale 2.5D/3D integration. To solve the critical issues of a current standard hybrid bonding technology, we developed scaled electrodes with slightly extruded structure and unique adhesive layer of anisotropic conductive film composed of ultra-high density CNP. Test element group (TEG) dies with 7-mm x 23-mm size are bonded to interposer wafer by a new hybrid bonding technology. Scaled electrodes with 3-mu m diameter and 6-mu m pitch are formed in each TEG chip. We confirmed for the first time that a huge number of electrodes of 4 309 200 are successfully connected in series with the joining yield of 100% due to the ultra-high density CNP.

  103. DRAMリテンション測定を用いた3DIC局所曲げ応力の影響評価

    谷川星野, 木野久志, 福島誉史, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 63rd 11-130 2016年

  104. 応力センサ集積シリコン神経プローブの開発

    原島卓也, 谷卓治, 鈴木雄策, 森川拓実, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 63rd 10-311-10-311 2016年

  105. 脳深部刺入可能なフレキシブルケーブル一体化シリコン神経プローブの開発

    森川拓実, 谷卓治, 原島卓也, 鈴木雄策, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 63rd 2016年

  106. Capillary Self-Assebly for 3D Heterogeneous System Integration and Packaging 招待有り

    Yuka Ito, Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    MRS ADVANCES 1 (34) 2355-2366 2016年

    出版者・発行元:CAMBRIDGE UNIV PRESS

    DOI: 10.1557/adv.2016.528  

    ISSN:2059-8521

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    The self-assembly of known good dies (KGDs) on substrates using the liquid capillary method is shown to be a promising technology to achieve three-dimensional (3D) heterogeneous system integration and packaging. Firstly, the effects of the edge structures of self-assembled substrates and chips on alignment accuracies were investigated. When hydrophobic sidewalls with 10-pm-height steps were applied to both chips and assembly sites formed on substrates, the alignment accuracy within 1.0 urn was realized. The alignment accuracies were within 2.0 pm using either substrates or chips having 10-um-height step structures with hydrophobic sidewalls. Self-assembly of 12-ch vertical-cavity surface-emitting lasers (VCSELs) with a long rectangle shape on glass substrates were also demonstrated. Separation of assembly sites into twelve areas enhanced the resultant force acting on the VCSEL short edge. The enhanced resultant force provided the high alignment accuracies within 2.0 pm. After the self-assembly of the VCSEL and the subsequent thermal compression, the chips successtnlly exhibited no degradation of their current voltage (I I") characteristics and appropriate 850-nm light emission. We demonstrated self-assembly and microhump bonding using non-conductive film (NCE)-covered dies with Cu/Sn microbumps tier high-throughput and high-yield multichip-to-wafer 3D integration. The self-assembly of the NCE-covered dies provided high alignment accuracy within 1.1 pin on average. After the self-assembly of NCE-coved dies and thermal compression, microbump chains composed of 7396 bump joints were successfully obtained; resulting in good electrical properties of 32 mil/joint without any bridge shorts and failures. The variations of microbump joint resistance were maintained within 5% of the initial value atter thennal cycle testing of even 1000 cycles.

  107. Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip 査読有り

    S. Tanikawa, H. Kino, T. Fukushima, K-W. Lee, M. Koyanagi, T. Tanaka

    2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) 6B-1-1-6B-1-6 2016年

    出版者・発行元:IEEE

    DOI: 10.1109/IRPS.2016.7574561  

    ISSN:1541-7026

    詳細を見る 詳細を閉じる

    The effect of local stresses on memory retention characteristics has been characterized in detail. A retention time of memory cells in a DRAM chip with 200-mu m thick was largely changed after under-fill shrinkage with Cu/Sn bumps. Meanwhile, after thinned down to 40-mu m thick, the retention time of memory cell was not significantly changed in the whole area even with Cu/Sn bumps due to decreased stress. We showed that the local stress generated by under-fill shrinkage with the dummy Cu/Sn bumps gave larger effects on the memory retention characteristics than the stress generated by the Si thinning until 40-mu m thick.

  108. Transfer and Non-Transfer 3D Stacking Technologies Based on Multichip-to-Wafer Self-Assembly and Direct Bonding 査読有り

    T. Fukushima, H. Hashiguchi, H. Kino, T. Tanaka, M. Murugesan, J. Bea, H. Hashimoto, K. Lee, M. Koyanagi

    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 289-294 2016年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC.2016.298  

    ISSN:0569-5503

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    Non-transfer and transfer based 3D integration technologies are developed to achieve high-throughput and high-precision multichip-to-wafer stacking. Both the stacking approaches employ KGD self-assembly technologies using liquid surface tension. In the former stacking scheme, a large number of chips having CMP-treated plasma-TEOS SiO2 on their top surface are directly self-assembled in a face-down configuration on an interposer wafer. On the other hand, in the latter stacking scheme, the many chips having the plasma-TEOS SiO2 are self-assembled in a face-up configuration on a carrier wafer, called SAE (Self-Assembly and Electrostatic) carrier, with bipolar electrodes for electrostatic adhesion. The latter chips are transferred from the carrier to another interposer in wafer-level processing. From the point of view of alignment accuracies and direct bonding strengths, the two stacking approaches are compared.

  109. Novel W2W/C2W hybrid bonding technology with high stacking yield using ultra-fine size, ultra-high density Cu nano-pillar (CNP) for exascale 2.5D/3D integration 査読有り

    K. W. Lee, C. Nagai, J. C. Bea, T. Fukushima, T. Tanaka, M. Koyanagi, R. Suresh, X. Wu

    2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 350-355 2016年

    出版者・発行元:IEEE COMPUTER SOC

    DOI: 10.1109/ECTC.2016.10  

    ISSN:0569-5503

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    We propose a novel hybrid bonding technology with a high stacking yield using ultra-high density Cu nano-pillar (CNP) for exascale 2.5D/3D integration. To solve the critical issues of current standard hybrid bonding technology, we developed scaled electrodes with slightly extruded structure and unique adhesive layer of anisotropic conductive film composed of ultra-fine size, ultra-high density CNP. Multi-numbers of TEG dies with 7mm x 23mm size are bonded to an interposer wafer by a new hybrid bonding technology. A huge number of electrodes of 4,309,200 composed of scaled electrodes with 3 mu m diameter and 6 mu m pitch are formed in each TEG die. We confirmed for the first time that 4,309,200 electrodes per die are successfully connected in series with the joining yield of 100% due to ultra-high density CNP.

  110. Accuracy Enhancement of Sub-mm Chip Self-Alignment Using Liquid Surface Tension for Hybrid Integration 査読有り

    Shinya Kikuta, Satohiko Hoshino, Yoshiki Yamanishi, Takafumi Fukushima, Kangwook Lee, Mitsumasa Koyanagi

    2016 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO) 350-355 2016年

    出版者・発行元:IEEE

    ISSN:2160-9020

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    A self-alignment process of sub-mm chips is studied for hybrid integration toward silicon photonics applications. Capillary forces by liquid surface tension drive the tiny chips to precisely and quickly align on silicon wafers. Self-alignment behaviors and the resulting high accuracies of the sub-mm chips are discussed in this work.

  111. Highly Sensitive Pressure Sensor with Silicon-On-Nothing (SON) MOSFET for Sensor Integrated Heterogeneous System 査読有り

    Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka

    2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW) 186-187 2016年

    出版者・発行元:IEEE

    DOI: 10.1109/SNW.2016.7578043  

    詳細を見る 詳細を閉じる

    MOSFETs have the potential to become a highly sensitive pressure sensor compared with conventional piezoresistive device such as doped Si. In this study, we have proposed a novel pressure sensor composed of silicon-on-nothing (SON) MOSET. It was clearly indicated that the SON-MOSFET had high gauge factor of 230 which was more than twice as high as conventional values. These results expedite developments and realization of sensor integrated heterogeneous system.

  112. マルチウェル構造TSVを用いたTSV側壁Si-SiO<sub>2</sub>界面準位の評価

    菅原陽平, 木野久志, 福島誉史, LEE K.-W., 小柳光正, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 77th 12-340-12-340 2016年

  113. 網膜下刺激人工網膜におけるAZO透明刺激電極の基礎評価

    下川賢士, 後藤大輝, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 77th 11-408-11-408 2016年

  114. 光ファイバ埋め込みシリコンオプト神経プローブの刺入特性評価

    森川拓実, 原島卓也, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 77th 11-416-11-416 2016年

  115. Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration 査読有り

    T. Fukushima, K. W. Lee, T. Tanaka, M. Koyanagi

    SEMICONDUCTOR WAFER BONDING: SCIENCE, TECHNOLOGY AND APPLICATIONS 14 75 (9) 285-290 2016年

    出版者・発行元:ELECTROCHEMICAL SOC INC

    DOI: 10.1149/07509.0285ecst  

    ISSN:1938-5862

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    We have proposed and developed 3D integration technologies based on self-assembly using surface tension of liquid in this decade. In this paper, microbump bonding and bumpless bonding in face-up and/or face-down configuration are introduced for fine-pitch interconnect formation. In addition, "non-transfer stacking", in other word, flip-chip self-assembly and "transfer stacking" called reconfigure-wafer-to-wafer using SAE carrier are explained.

  116. Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration 招待有り

    T. Fukushima, K. W. Lee, T. Tanaka, M. Koyanagi

    SEMICONDUCTOR WAFER BONDING: SCIENCE, TECHNOLOGY AND APPLICATIONS 14 75 (9) 285-290 2016年

    出版者・発行元:ELECTROCHEMICAL SOC INC

    DOI: 10.1149/07509.0285ecst  

    ISSN:1938-5862

    詳細を見る 詳細を閉じる

    We have proposed and developed 3D integration technologies based on self-assembly using surface tension of liquid in this decade. In this paper, microbump bonding and bumpless bonding in face-up and/or face-down configuration are introduced for fine-pitch interconnect formation. In addition, "non-transfer stacking", in other word, flip-chip self-assembly and "transfer stacking" called reconfigure-wafer-to-wafer using SAE carrier are explained.

  117. 三次元集積用テンポラリー接着剤の特性とウエハエッジの影響 査読有り

    福島誉史, 福島誉史, MURUGESAN Mariappan, BEA Jicheol, LEE Sanghoon, LEE Kang-Wook, 田中徹, 田中徹, 小柳光正

    電子情報通信学会論文誌 C(Web) J99-C (11) 493-500 2016年

    ISSN:1881-0217

  118. New Concept of TSV Formation Methodology Using Directed Self-Assembly (DSA) 査読有り

    Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    2016 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2016年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2016.7970022  

    ISSN:2164-0157

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    A new TSV formation methodology based on advanced Directed Self-Assembly (DSA) with nanocomposites consisting of nano metal particles and block-co-polymers is proposed in this paper. Cylindrical nano-ordered structures are formed in Si deep holes through phase separation of polystyrene-block-poly methyl methacrylate polymers (PS-b-PMMA). The impact of molecular weight of the polymers, composition (PS/PMMA ratio), and phase separation temperature on the morphologies is discussed. In addition, simulation results using Self-Consistent Field (SCF) theory are introduced to make fine-pitch TSV.

  119. Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications 査読有り

    Kangwook. Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi

    2016 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2016年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2016.7970027  

    ISSN:2164-0157

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    We propose nanoscale Cu direct bonding technology using ultra-high density Cu nano-pillar (CNP) with for high stacking yield exascale 2.5D/3D integration. We clarified the joining mechanism of nanoscale Cu direct bonding using CNP. Nanoscale Cu pillar easily bond with Cu electrode by recrystallization of CNP due to the solid phase diffusion and by morphology change of CNP to minimize interfacial energy at relatively lower temperature and pressure compared to conventional microscale Cu direct bonding. We confirmed for the first time that 4.3 million electrodes per die are successfully connected in series with the joining yield of 100%. The joining resistance of CNP bundle with 80 mu m height is around 30 m Omega for each pair of 10 mu m electrode diameter. Normalized capacitance of CNP bundle with 80um height is 0.2 fF per tm wire length.

  120. Improving the Integrity of Ti Barrier Layer in Cu-TSVs Through Self-Formed TiSix for Via-Last TSV Technology 査読有り

    Murugesan Mariappan, JiChel Bea, Takafumi Fukushima, Makoto Motoyoshi, Tetsu Tanaka, Mitsumasa Koyanagi

    2016 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2016年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2016.7970017  

    ISSN:2164-0157

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    With in the process temperature limit of less than 400 degrees C for via last technology, a simple method to improve the barrier ability of Ti layer in through Si via (TSV) has been studied. After annealing the TSV structures in vacuum at temperatures up to 400 degrees C, we did observe a tremendous improvement in leak current characteristics for SiO2 dielectric. It was found that the self-formed TiSix at the interface between Cu and SiO2 during the sputter deposition of Ti barrier layer was converted into an amorphous TiOx and SiOx upon vacuum annealing. This simple vacuum annealing of Cu-TSVs is a promising approach for using Ti as barrier layer in via-last 3D-integration.

  121. 電気/薬液/光による高度脳操作を可能にするシリコン神経プローブの開発

    原島 卓也, 谷 卓治, 鈴木 雄策, 森川 拓実, 木野 久志, 福島 誉史, 田中 徹

    平成27年度 包括型脳科学研究推進支援ネットワーク冬のシンポジウム 60-60 2015年12月17日

  122. 柔軟性を有するフレキシブルケーブル一体化シリコン神経プローブの開発-多機能集積化脳神経プローブシステムの開発1-

    鈴木 雄策, 谷 卓治, 原島 卓也, 森川拓実, 木野 久志, 福島 誉史, 田中 徹

    平成27年度 包括型脳科学研究推進支援ネットワーク 冬のシンポジウム 60-60 2015年12月17日

  123. Evaluation of 2-D Local Stress Distribution in Stacked IC Chip Using Stress-induced Retention Time Modulation od DRAM Cell Array 査読有り

    Seiya Tanikawa, Hideto Hashiguchi, Yohei Sugawara, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials 790-791 2015年9月30日

  124. Electroless Nickel Barrier/Seed Layer Deposition on Dielectric Liners for Advanced Cu-TSV Applications 査読有り

    Takafumi Fukushima, Kazuko Taniguchi, Shigeru Watariguchi, Mariappan Murugesan, Chisato Nagai, Ai Nakamura, Hiroyuki Hashimoto, Ji-Chel Bea, Tetsu Tanaka, Mitsumasa Koyanagi, Kang-Wook Lee

    Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials 70-71 2015年9月29日

  125. Capacitance Characteristics of Low-k Low-Cost CVD Grown Polyimide Liner for High-Density Cu-TSVs in 3D-LSI 査読有り

    Murugesan Mariappan, Ji-Chel Bea, Takafumi Fukushima, Hiroyuki Hashimoto, Kang-Wook Lee, Mitsumasa Koyanagi

    Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials 64-65 2015年9月29日

  126. Local Stress Effect due to Operation-Heating-Induced Adhesive Expansion on Transistor Performances in 3D IC 査読有り

    Hisashi Kino, Hideto hashiguchi, Seiya Tanikawa, Youhei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    Extended Abstracts of the 2015 International Conference on Solid State Devices and Materials 56-57 2015年9月27日

  127. 高分子材料を用いた三次元集積技術 招待有り

    福島誉史

    第41回 よこはま高度実装技術コンソーシアム(YJC)実装技術セミナー 2015年6月11日

  128. Die-to-Wafer Self-Assembly by Droplet Surface Tension for 3D LSI & Advanced System Integration 招待有り

    Takafumi Fukushima

    Proc. EMN Meeting on Droplets 2015年5月10日

  129. Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration 査読有り

    Yuka Ito, Takafumi Fukushima, Hisashi Kino, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 54 (3) 030206-1-030206-6 2015年3月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.7567/JJAP.54.030206  

    ISSN:0021-4922

    eISSN:1347-4065

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    Twelve-channel vertical-cavity surface-emitting laser (12-ch VCSEL) chips are heterogeneously self-assembled on Si and glass wafers using water surface tension as a driving force. The VCSEL chips have a high length-to-width aspect ratio, that is, 3 mm long and 0.35 mm wide. The VCSEL chips are precisely self-assembled with alignment accuracies within 2 mu m even when they are manually placed on liquid droplets provided on the host substrate. After the self-assembly of the VCSEL chips and the subsequent thermal compression, the chips successfully emit 850 nm light and exhibit no degradation of their current-voltage (I-V) characteristics. (C) 2015 The Japan Society of Applied Physics

  130. Applications of three-dimensional LSI 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka

    MRS BULLETIN 40 (3) 242-247 2015年3月

    出版者・発行元:CAMBRIDGE UNIV PRESS

    DOI: 10.1557/mrs.2015.33  

    ISSN:0883-7694

    eISSN:1938-1425

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    To overcome various concerns due to scaling-down device size in future large-scale integration (LSI), it is indispensable to introduce a new concept of heterogeneous three-dimensional (3D) integration in which various kinds of device chips with different sizes, devices, and materials are vertically stacked. To achieve such heterogeneous 3D integration, the key technology of self-assembly and electrostatic (SAE) bonding has been developed. The heterogeneous 3D integration technology with the SAE bonding method has enabled 3D heterogeneous stacking of different types of chips such as the compound semiconductor device chip, photonic device chip, and spintronic device chip on complementary metal oxide semiconductor chips. A 3D image sensor with extremely fast processing speed and a 3D microprocessor with a self-test and self-repair function for future automatic driving vehicles are typical examples of heterogeneous 3D LSIs which we fabricated by the SAE bonding method.

  131. Applications of three-dimensional LSI 招待有り 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka

    MRS BULLETIN 40 (3) 242-247 2015年3月

    出版者・発行元:CAMBRIDGE UNIV PRESS

    DOI: 10.1557/mrs.2015.33  

    ISSN:0883-7694

    eISSN:1938-1425

    詳細を見る 詳細を閉じる

    To overcome various concerns due to scaling-down device size in future large-scale integration (LSI), it is indispensable to introduce a new concept of heterogeneous three-dimensional (3D) integration in which various kinds of device chips with different sizes, devices, and materials are vertically stacked. To achieve such heterogeneous 3D integration, the key technology of self-assembly and electrostatic (SAE) bonding has been developed. The heterogeneous 3D integration technology with the SAE bonding method has enabled 3D heterogeneous stacking of different types of chips such as the compound semiconductor device chip, photonic device chip, and spintronic device chip on complementary metal oxide semiconductor chips. A 3D image sensor with extremely fast processing speed and a 3D microprocessor with a self-test and self-repair function for future automatic driving vehicles are typical examples of heterogeneous 3D LSIs which we fabricated by the SAE bonding method.

  132. Advanced 2.5D/3D Hetero-Integration Technologies at GINTI, Tohoku University 査読有り

    K. W. Lee, J. C. Bea, M. Koyanagi, T. Fukushima, T. Tanaka

    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) 2015年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    The Global Integration Initiative (GINTI) is 8/12-inch R&D foundry fab for the research and development of new 2.5D/3D integration technologies and creative applications. GINTI offers a broad range of services to meet the mounting R&D needs of the semiconductor industry and related industries. GINTI provides a cost-competitive process development infrastructure in a manufacturing-like fab environment and a low-cost, short TAT prototyping of proof of concepts using commercial/customized 2D chip/wafer, and a base-line process set-up for the pilot production of creative 3D systems. GINTI aims to provide Tohoku University's advanced 2.5D/3D integration technologies into electronic industries to accelerate the commercialization of innovative 3D technologies and applications into real, manufacturing-ready technology solutions with FAST. This paper introduces advanced 2.5D/3D hetero-integration technologies developed by GINTI/Tohoku University.

  133. Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM 査読有り

    Kang-Wook Lee, Ji-Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) 2015年

    出版者・発行元:IEEE

    ISSN:1541-7026

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    Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip were evaluated. The retention characteristics of memory cells were degraded depending on the decreased chip thickness, especially dramatically degraded below 40-mu m thickness in the case with under-fill, meanwhile, the retention characteristics were relatively not so degraded until to 30-mu m thickness, but suddenly degraded below 20-mu m thickness in the case without under-fill. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 degrees C annealing. Meanwhile, the retention characteristics in the thinned DRAM chip which was DP-treated did not degrade regardless of the well structure. The retention characteristics of some memory cell arrays with Cu TSV arrays began to degrade after annealing at 300 degrees C for 30min. As the annealing temperature increase higher than 400 degrees C, Cu atoms more spread out into larger area in the DRAM chip via poor barrier layers.

  134. Yield Enhancement and Mitigating the Si-Chipping and Wafer Cracking in Ultra-Thin 20 mu m-Thick 8-and 12-Inch LSI Wafer 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, K. W. Lee, M. Koyanagi

    2015 26TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC) 435-439 2015年

    出版者・発行元:IEEE

    ISSN:1078-8743

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    We have meticulously investigated several pregrinding parameters such as edge trimming width, depth, and edge-back rinse of smeared glue to mitigate the Si chipping and cracking and to enhance the yield in ultra-thin LSI wafer thinning for the thickness value of up to 20 mu m, with respect to different types of temporary bonding glue and the glue thickness. After optimizing several pre-grinding and the post-grinding parameters, we found that an intermediate edge-backrinse process before the final grinding tremendously reduces the Si chipping and wafer cracking, which enhances the yield of ultra-thin wafer grinding.

  135. 高分子材料を用いた三次元集積技術 I:セルフアセンブリによるNCF被覆ダイ・オン・ウェーハ

    伊藤有香, 伊藤有香, 福島誉史, MURUGESAN Mariappan, 裴志哲, 李康旭, 田中徹, 田中徹, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 29th 408-409 2015年

    ISSN:1880-4616

  136. 高分子材料を用いた三次元集積技術 II:ビアラストTSV形成のための高耐熱テンポラリー無機接着層

    橋口日出登, 福島誉史, 裴志哲, MURUGESAN Mariappan, 李康旭, 田中徹, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 29th 410-412 2015年

    ISSN:1880-4616

  137. 高分子材料を用いた三次元集積技術 III:気相堆積ポリイミドTSVライナーの形成と特性評価

    福島誉史, MURUGESAN Mariappan, 裴志哲, 橋本宏之, 佐藤優, 李康旭, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 29th 413-415 2015年

    ISSN:1880-4616

  138. Novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using ultra-high density nano-Cu filaments for exascale 2.5D/3D integration

    K-W Lee, C. Nagai, J-C Bea, T. Fukushima, R. Suresh, X. Wu, T. Tanaka, M. Koyanagi

    2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 260-263 2015年

    出版者・発行元:IEEE

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    In order to solve the critical issues of current standard chip-to-wafer (C2W)/wafer-to-wafer (W2W) hybrid bonding technologies, we propose novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using three types of scaled tiny electrodes with slightly extruded structure and unique adhesive layers for ultra-high density 2.5D/3D integration applications. Especially, we developed a high stacking yield hybrid bonding technology using unique anisotropic conductive film composed of ultra-high density nano-Cu filaments for exascale 2.5D/3D integration. Multi numbers of TEG die with 7mm x 23mm size are simultaneously aligned with high accuracy around 1 um by chip self-assembly method and thermal-compression bonding in wafer-level. Totally 3,898,000 of 4,309,200 electrodes with 3um diameter/6um pitch in each TEG chip are well intact-bonded by new hybrid bonding technology using ultra-high density nano-Cu filaments which gives rise to the joining yield of 90%.

  139. Improved C-V, I-V Characteristics for Co-Polymerized Organic Liner in the Through-Silicon-Via for High Frequency Applications by Post Heat Treatment 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, H. Hashimoto, Y. Sato, K. W. Lee, M. Koyanagi

    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 73-77 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2015.7159574  

    ISSN:0569-5503

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    The effect of post-heat treatment of chemical-vapor-deposited polyimide (PI) liner along the Cu-TSV side-wall in the 3D-LSI chips was investigated for leakage current, parasitic capacitance and thermal stability by analyzing current-voltage (I-V), capacitance-voltage (C-V), and x-ray photo-electron spectroscopy (XPS) data. From the I-V data it is inferred that the post heat treatment of 250 nm-thick PI at 200 degrees C has tremendously suppressed the leak current as compared to the leak current in the pristine PI film. In the case of annealed PI the leak current was minimized to nearly half for the stress voltage of up to +/- 20 V, whereas it was reduced by nearly three (3) orders for the stress value of +/- 40 V. The post annealing process also suppresses the hysteresis, and this effect is pronounced for the thicker film.

  140. Development of Highly-Reliable Microbump Bonding Technology using Self-Assembly of NCF-Covered KGDs and Multi -Layer 3D Stacking Challenges 査読有り

    Yuka Ito, Mariappan Murugesan, Hisashi Kino, Takafumi Fukushima, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi

    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 336-341 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2015.7159614  

    ISSN:0569-5503

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    We have proposed a new multichip-to-wafer 3D stacking method with high throughput and high yield based on a capillary self-assembly method using liquid droplets. In this paper, we optimized conditions in self-assembly and microbump bonding using non-conductive film (NCF)-covered known good dies (KGDs). Self-assembly of the NCF-covered KGDs provided high chip alignment accuracy within approximately 1 jun. After the self-assembly and a subsequent thermal compression, resultant microbump chains composed of over 7,000 microbump joints exhibited good electrical properties of 32 mQ/joint without bridge short and open failures. The microbump joint resistance varied within 5% of the initial values after thermal cycle test (TCT) of 1,000 cycles. In addition, we demonstrated a multi-layer 3D stacking by the self-assembly method with the NCF-covered KGDs.

  141. Challenges of High-Robustness Self-Assembly with Cu/Sn-Ag Microbump Bonding for Die-to-Wafer 3D Integration 査読有り

    Taku Suzuki, Kazushi Asami, Yasuhiro Kitamura, Takafumi Fukushima, Chisato Nagai, Jichoel Bea, Yutaka Sato, Mariappan Murugesan, Kang-wook Lee, Mitsumasa Koyanagi

    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 342-347 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2015.7159615  

    ISSN:0569-5503

    eISSN:2377-5726

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    We demonstrated surface tension-driven self-assembly of chips with Cu/Sn-Ag microbumps in order to satisfy requirements for both high throughput and high alignment accuracy toward 3D system integration. The chips were singulated with different dicing methods: standard single-cut, precise single-cut, and modified step-cut. The alignment accuracies were compared among the three methods. The chips obtained by modified step-cut were precisely aligned within approximately 2 jtm and comparable to that obtained by precise single-cut. By optimizing liquid volumes, the step cut chips having Cu/Sn-Ag microbumps were accurately self assembled irrespective of microbump densities. The self assembled chips were successfully bonded at 280 C by thermal compression. The Cu/Sn-Ag daisy chains indicated good electrical characteristics with a resistance of 35 oint.

  142. Impact of Deep-Via Plasma Etching Process on Transistor Performance in 3D-IC with Via-Last Backside TSV 査読有り

    Yohei Sugawara, Hideto Hashiguchi, Seiya Tanikawa, Hisashi Kino, Kang-Wook Lee, Takafumi Fukusima, Mitsumasa Koyanagi, Tetsu Tanaka

    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 822-827 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2015.7159687  

    ISSN:0569-5503

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    3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during via-hole etching have been investigated using test structures flip-chip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.

  143. Characterization of 3D Stacked High Resistivity Si Interposers with Polymer TSV liners for 3D RF Module

    Kwang-Seong Choi, Haksun Lee, Hyun-Cheol Bae, Yong-Sung Eom, Kangwook Lee, Takafumi Fukushima, Mitsumasa Koyanagi, Jin Ho Lee

    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 928-933 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2015.7159705  

    ISSN:0569-5503

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    The material designs of the Si interposers are optimized for a 3D RF module. The high resistivity Si wafers are used for the Si interposer fabrication: 1,000 Omega.cm similar to 10,000 Omega.cm. To reduce the capacitance and mechanical stress between Cu-filled TSV and Si substrate, a polyimide insulation layer is applied as a TSV liner. We designs several types of the transmission line structures and measures their electrical properties. For the 3D interconnection between the Si interposers, fluxing underfill material is developed and used as a pre-applied underfill for the thermocompression bonding process. With these optimizations of materials design of the Si interposers, the microstrip line shows the electrical loss of 0.065 dB/mm at 10 GHz, and the insertion loss of the vertical transition is 0.4 dB at 10 GHz.

  144. Plasma Assisted Multichip-to-Wafer Direct Bonding Technology for Self-Assembly Based 3D Integration 査読有り

    H. Hashiguchi, H. Yonekura, T. Fukushima, M. Murugesan, H. Kino, K. -W. Lee, T. Tanaka, M. Koyanagi

    2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 1458-1463 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2015.7159789  

    ISSN:0569-5503

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    We demonstrated plasma-assisted multichip-to-wafer direct bonding for self-assembly based 3D integration processes. We mainly evaluated the bonding yields and bonding strengths of dies obtained by multichip-to-wafer direct oxide-oxide bonding, and compared with wafer-to-wafer direct oxide oxide bonding in their bonding properties. In this study, we employed thermal oxide and chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate (TEOS) as bonding interfaces, and in addition, N2 or Ar plasmas were used for the surface activation. We finally introduce multichip-to-wafer direct oxide-oxide bonding between self-assembled dies and wafers having the PECVDoxide layer.

  145. Novel Local Stress Evaluation Method in 3D IC Using DRAM Cell Array with Planar MOS Capacitors 査読有り

    Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) 59-61 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2015.7334557  

    ISSN:2164-0157

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    Three-dimensional integrated circuit (3D IC) is one of the promising ways to enhance IC performance. Each IC chip is mechanically connected by organic adhesive and metal microbumps. Coefficient of thermal expansion (CTE) mismatch between materials causes local bending stress in IC chips, leading to negative effects in IC performance. In this study, we have fabricated a test structure with DRAM cell array having planar MOS capacitors. Using the test structure, we measured both DRAM chip bending profiles and retention time modulations of DRAM cell array. Consequently, we have successfully demonstrated that the local bending stress in IC chips can be two dimensionally evaluated using the DRAM cell array with planar MOS capacitances. This evaluation methods leads to realization of 3D IC with high reliability.

  146. Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers 査読有り

    K. W. Lee, C. Nagai, A. Nakamura, H. Aizawa, J. C. Bea, M. Koyanagi, H. Hashiguchi, T. Fukushima, T. Tanaka

    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) 31-34 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2015.7334471  

    ISSN:2164-0157

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    High yield reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology is proposed for ultra-high density 2.5D/3D integration applications. New mCoW hybrid bonding technology use shallow-recess oxide structure, electro-less plated capping layers, and thin glue adhesive layer below 1 um to avoid the issues of current standard CoW bonding technology. Multi numbers of TEG die with 7mm x 23mm size are simultaneously aligned with high accuracy around lum using chip self-assembly technology and thermal-compression bonded by in batch. In the TEG chip, totally 684,000 electrode daisy chain comprising of 3um diameter/6um pitch tiny Cu electrodes are well intact joined by new reconfigured mCoW hybrid bonding technology.

  147. Consideration of Micro bump Layout for Reduction of Local Bending Stress Due to CTE Mismatch in 3D IC 査読有り

    Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) 260-263 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2015.7334596  

    ISSN:2164-0157

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    Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.

  148. Transfer and Non-Transfer Stacking Technologies Based on Chip-to-Wafer Self-Asembly for High-Throughput and High-Precision Alignment and Microbump Bonding 査読有り

    Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang-Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi

    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) 134-137 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2015.7334578  

    ISSN:2164-0157

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    Two types of high-throughput and high-precision multichip-to-wafer 3D stacking approaches are demonstrated: one is non-transfer stacking and the other one is transfer stacking. Both the stacking approaches employ a self-assembly technologies using liquid surface tension. In the former stacking scheme, large number of chips having 20-mu m-square Cu/SnAg microbumps are directly self-assembled face-down on an interposer wafer, like flip-chip bonding. On the other hand, in the latter stacking scheme, the many chips having the microbumps are self-assembled face-up on a carrier wafer with bipolar electrodes for electrostatic chucking. Then, the latter chips are transferred from the carrier to another interposer in wafer-level processing. The alignment accuracies are evaluated and compared between the two stacking approaches. The resulting daisy chains show good electrical properties comparable to conventional flip-chip bonding.

  149. Vacuum-Assisted-Spin-Coating of Polyimide Liner for High-Aspect-Ratio TSVs Applications 査読有り

    Yangyang Yan, Yingtao Ding, Qianwen Chen, Kangwook Lee, Takafumi Fukushima, Mitsu Koyanagi

    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) 84-88 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2015.7334568  

    ISSN:2164-0157

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    In this paper, by combining conventional spin coating method with vacuum treatment, a relatively simple and feasible process technique referred to as vacuum-assisted spin coating technique was proposed to get uniform polyimide liner along sidewalls of high aspect ratio Through-Silicon-Vias (TSVs) for three-dimensional (3D) integration applications. Details about the proposed technique were illustrated and test structures of silicon blind vias with diameter of about 6 mu m and depth of about 51 mu m were successfully sidewall coated with polyimide liner with step coverage around 30% utilizing the technique proposed. For thermal reliability investigations of the cured polyimide liner, X-ray photoelectron spectroscopy (XPS) analysis was performed to get the chemical state information of the cured polyimide liner. Also, planar metal insulator-semiconductor (MIS) capacitor which involves polyimide as insulator was built to investigate electrical properties of polyimide liner formed. Electrical characteristics such as capacitance-voltage(C-V) curve and leakage current under biased voltage up to 20V were measured. All these results showed the potential of the technique proposed to be applied to high aspect ratio TSVs for 3D integration.

  150. Mitigating Thermo Mechanical Stress in High Density 3D-LSI Through Dielectric Liners in Cu-Through Silicon Via _ mu-RS and mu-XRD Study 査読有り

    M. Murugesan, J. C. Bea, H. Hashimoto, K. W. Lee, M. Koyanagi, T. Fukushima, T. Tanaka

    2015 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC 2015) 179-183 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2015.7334579  

    ISSN:2164-0157

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    3D-LSI chip containing through-silicon-via (TSV, diameters ranging from 5 mu m to 30 mu m) with two different dielectric liners has been investigated for thermo-mechanical stress (TMS) in Si via micro-Raman spectroscopy and micro-X-ray diffraction analysis. Both the micro-Raman and micro-X-ray diffraction results revealed that the low-k CVD-grown dielectric polyimide (PI) liner tremendously reduces the TMS in the vicinal Si as well as the Si sandwiched between TSVs. It can be explained that the observed smaller TMS values for TSVs with PI is owing to the partial accommodation of the expanded Cu during thermal cycling by the low modulus, soft PI.

  151. 回路動作の発熱によって三次元集積回路内に生成される局所応力の影響に関する研究

    木野久志, 橋口日出登, 谷川星野, 菅原陽平, 池ヶ谷俊介, 福島誉史, 福島誉史, 小柳光正, 田中徹, 田中徹

    マイクロエレクトロニクスシンポジウム論文集 25th 355-358 2015年

    ISSN:2434-396X

  152. DRAMセルアレイの電荷保持特性を用いた3DICにおける局所曲げ応力の影響評価

    谷川星野, 木野久志, 福島誉史, 小柳光正, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 76th 12-124 2015年

  153. 3D IC用ビアラスト/バックサイドビアプロセスにおける高アスペクト比ビア形成がトランジスタに与える影響評価

    菅原陽平, 木野久志, 福島誉史, LEE K.-W., 小柳光正, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 76th 12-123-12-123 2015年

  154. チップ集積・フレキシブルケーブル一体化シリコン神経プローブの開発(集積化脳神経プローブシステムの開発 1)

    鈴木雄策, 谷卓治, 原島卓也, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 76th 11-379 2015年

  155. 大脳皮質層別光刺激のための反射ミラー集積シリコン神経プローブの開発

    原島卓也, 谷卓治, 鈴木雄策, 森川拓実, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 76th p11-381-p11-381 2015年

  156. 気相堆積重合によるポリイミド薄膜の形成とシリコン貫通配線への応用

    福島誉史, 福島誉史, MURUGESAN Mariappan, BEA Jichoel, LEE Kangwook, 小柳光正

    高分子学会予稿集(CD-ROM) 64 (2) 2015年

  157. 三次元積層型LSI作製のための高耐熱テンポラリー接着剤技術

    福島誉史, 福島誉史, MURUGESAN Mariappan, BEA Jichoel, LEE Kangwook, 小柳光正

    高分子学会予稿集(CD-ROM) 64 (2) 2015年

  158. シリコン貫通配線(TSV)と三次元集積化技術の研究開発動向 招待有り

    福島誉史, LEE Kang-Wook, 田中徹, 小柳光正

    センサ・マイクロマシンと応用システムシンポジウム(CD-ROM) 32nd 28pm3-D-1-1-28pm3-D-1-6 2015年

  159. 三次元集積化技術におけるチップ薄化に伴う局所曲げ応力のDRAMセルアレイを用いた評価

    谷川星野, 木野久志, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学会東北支部学術講演会講演予稿集(Web) 70th 2015年

  160. Novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using ultra-high density nano-Cu filaments for exascale 2.5D/3D integration 査読有り

    K-W Lee, C. Nagai, J-C Bea, T. Fukushima, R. Suresh, X. Wu, T. Tanaka, M. Koyanagi

    2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 185-188 2015年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2015.7409652  

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    In order to solve the critical issues of current standard chip-to-wafer (C2W)/wafer-to-wafer (W2W) hybrid bonding technologies, we propose novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using three types of scaled tiny electrodes with slightly extruded structure and unique adhesive layers for ultra-high density 2.5D/3D integration applications. Especially, we developed a high stacking yield hybrid bonding technology using unique anisotropic conductive film composed of ultra-high density nano-Cu filaments for exascale 2.5D/3D integration. Multi numbers of TEG die with 7mm x 23mm size are simultaneously aligned with high accuracy around 1 um by chip self-assembly method and thermal-compression bonding in wafer-level. Totally 3,898,000 of 4,309,200 electrodes with 3um diameter/6um pitch in each TEG chip are well intact-bonded by new hybrid bonding technology using ultra-high density nano-Cu filaments which gives rise to the joining yield of 90%.

  161. Mechanical Characteristics of Thin Die/Wafers in Three-Dimensional Large-Scale Integrated Systems 査読有り

    Murugesan Mariappan, Takafumi Fukushima, Jichoel C. Bea, Kang-Wook Lee, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 27 (3) 341-346 2014年8月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TSM.2014.2316917  

    ISSN:0894-6507

    eISSN:1558-2345

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    A thickness value of less than 50 m for die/wafers is a must meet criteria in 3-D large-scale silicon device integration, in order to reduce interconnect lengths and resistive-capacitive delays. The mechanical properties of such ultra-thin die/wafers, namely, Young's modulus, hardness, etc., with respect to 1) different die thinning processes (chemical mechanical polishing, plasma etching, dry polishing, kai-dry polishing, poly grinding, ultra-poly grinding, #2000, etc.); 2) various wafer thicknesses (10, 20, 30, 40, 50, 100, and 200 m); and 3) different wafer types (P/P+, P/P-, and wafers with internal-gettering layers) were investigated by using a nano-indenter. The mechanical characteristic data obtained for the thin die/wafers were well supported by their corresponding residual stress values (obtained by laser micro-Raman spectroscopy) and the crystal mis-orientation results (obtained via electron back-scatter diffraction). The chemically-mechanically polished ultrathin dies/wafers were found to be extremely good from the perspective of both mechanical strength and residual stress when compared to their counter parts fabricated by all other die thinning methods considered in this study.

  162. Self-Assembly Based 3D and Heterointegration 査読有り

    Takafumi Fukushima, Jicheol Bea

    Handbook of 3D Integration 3 325-334 2014年7月21日

    出版者・発行元:Wiley Blackwell

    DOI: 10.1002/9783527670109.ch24  

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    In order to improve assembly throughput and production yield in chip-on-wafer 3D integration, surface tension-driven chip self-assembly technologies have been proposed. Small volume of liquid droplets can precisely assemble a large number of known good dies on host wafers at the sub-micrometer accuracy level. Here, impact of several parameters on alignment accuracies are described. In addition, this chapter introduces interconnect technologies of self-assembled chips in a face-up or face-down bonding fashion to the host wafers with metal microbumps.

  163. Impacts of Cu Contamination on Device Reliabilities in 3-D IC Integration 査読有り

    Kang-Wook Lee, Ji-Chel Bea, Yuki Ohara, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 14 (1) 451-462 2014年3月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TDMR.2013.2258022  

    ISSN:1530-4388

    eISSN:1558-2574

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    The impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate, shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by postgrinded dry polish (DP) treatment shows good Cu retardation characteristics compared with other postgrinded treatments. The minimal 30-nm-thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60 min at 300 degrees C. However, it is not enough at 400 degrees C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5 min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300 degrees C.

  164. Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM 査読有り

    Kang-Wook Lee, Seiya Tanikawa, Mariappan Murugesan, Hideki Naganuma, Ji-Choel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 61 (2) 379-385 2014年2月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2013.2295244  

    ISSN:0018-9383

    eISSN:1557-9646

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    The impacts of 3-D integration processes on memory retention characteristics in thinned DRAM chip were evaluated. The retention characteristics of DRAM cell in a DRAM chip which was face-down bonded to an interposer with under-fill degraded depending on the decreased chip thickness, especially dramatically degraded below 40-mu m thickness. Meanwhile, the retention characteristics of DRAM cell in a DRAM chip which was bonded without under-fill relatively not so degraded until to 30-mu m thickness, but suddenly degraded below 20-mu m thickness. The retention characteristics of DRAM cell in the thinned DRAM chip which was CMP-treated dramatically degraded after intentional Cu diffusion from the backside surface at 300 degrees C annealing, regardless of the well structure. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip which was DP-treated not degraded even after Cu diffusion at 300 degrees C annealing.

  165. Reconfigured-Wafer-to-Wafer 3-D Integration Using Parallel Self-Assembly of Chips With Cu-SnAg Microbumps and a Nonconductive Film 査読有り

    Takafumi Fukushima, Jichoel Bea, Hisashi Kino, Chisato Nagai, Mariappan Murugesan, Hideto Hashiguchi, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 61 (2) 533-539 2014年2月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2013.2294831  

    ISSN:0018-9383

    eISSN:1557-9646

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    A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 mu m when 3 x 3-, 5 x 5-, 4 x 9,- or 10 x 10-mm(2) chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-mu m-pitch Cu-SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu-SnAg microbumps exhibited ohmic contacts, and the resistance of similar to 40 m Omega/bump was sufficiently low for 3-D large-scale integration application.

  166. Deteriorated Device Characteristics in 3D-LSI Caused by Distorted Silicon Lattice 査読有り

    Murugesan Mariappan, Yasuhiko Imai, Shigeru Kimura, Takafumi Fukushima, Ji-Choel Bea, Hisashi Kino, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 61 (2) 540-547 2014年2月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2013.2295463  

    ISSN:0018-9383

    eISSN:1557-9646

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    Silicon-lattice distortion in the 50-mu m-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn mu-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45 degrees and -0.25 degrees, respectively, over the mu-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced similar to 1000 MPa of tensile stress and similar to-200 MPa of compressive stress, respectively, over the mu-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

  167. Impacts of Cu Contamination in 3D Integration Process on Memory Retention Characteristics in Thinned DRAM Chip 査読有り

    Kangwook Lee, Seiya Tanikawa, Hideki Naganuma, Jichel Bea, Mariappine Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM 2014年

    出版者・発行元:IEEE

    ISSN:1541-7026

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    The influences of Cu contamination on 3D DRAM memory cell retention are characterized for Cu migration from the ground backside surface of a chip and Cu filled TSVs. The DRAM cell retention characteristics in chips thinned to 50-mu m thickness then CMP polished are dramatically degraded, regardless of the well structure, after intentional Cu diffusion from the grinded backside surface at 300 degrees C, 30 min. Meanwhile, the retention characteristics of DRAM cell in the thinned DRAM chip, which was DP-treated, is not degraded even after annealing. The retention characteristics of some memory cells separated by 20-mu m similar to 50-mu m from arrays of 10-mu m diameter Cu TSVs began to degrade after post-annealing at 300 degrees C, 30 min owing to the insufficient blocking property of the sputtered-Ta barrier layers in TSV array. The CVD Mn oxide layer formed as a barrier layer in the TSVs shows better barrier property results compared with the sputtered Ta barrier layer.

  168. Via-Last/Backside-Via 3D Integration Using a Visible-Light Laser Debonding Technique 査読有り

    T. Fukushima, M. Mariappan, J. -C. Bea, H. Hashimoto, Y. Sato, M. Motoyoshi, K. -W. Lee, M. Koyanagi

    2014 4TH IEEE INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D) 13-13 2014年

    出版者・発行元:IEEE

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    A visible-light laser debonding technique is introduced for via-last/backside-via 3D integration. Temporary bonding of 12-inch wafers with a temporary glue and the subsequent wafer thinning processes give small TTV within 1 mu m by using an auto-TTV functions. Cu-TSV daisy chains with TSV diameters of 5 mu m are formed in 50-mu m-thick thinned Si wafers.

  169. Barrier Properties of CVD Mn Oxide Layer to Cu Diffusion for 3-D TSV 査読有り

    Kang-Wook Lee, Hao Wang, Ji-Cheol Bea, Mariappan Murugesan, Yuji Sutou, Takafumi Fukushima, Tetsu Tanaka, Junichi Koike, Mitsumasa Koyanagi

    IEEE ELECTRON DEVICE LETTERS 35 (1) 114-116 2014年1月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2013.2287879  

    ISSN:0741-3106

    eISSN:1558-0563

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    The effect of CVD Mn oxide layer as a barrier layer to Cu diffusion for 3-D TSV was characterized. The impact of oxide substrate on the barrier property of a planar Mn oxide was evaluated by XPS method. Planar Mn oxide layer of 20-nm thickness formed over thermal oxide showed an excellent barrier property to Cu diffusion after annealing at 500 degrees C, whereas the Mn oxide over P-TEOS oxide was good enough up to 400 degrees C annealing. On the other hand, the barrier property of Mn oxide upon O3-TEOS oxide was not as good as thermal and P-TEOS oxides. The effect of a vertical Mn oxide layer as a barrier layer to Cu diffusion from Cu TSV was evaluated by C-t analysis. Vertical Mn oxide layer with 20-nm thickness formed on P-TEOS oxide liner in TSV showed better barrier property, when compared with the sputtered Ta barrier layer, up to 400 degrees C annealing condition. However, the barrier property of CVD Mn oxide layer was degraded after annealing at 500 degrees C.

  170. Highly Beneficial Organic Liner with Extremely Low Thermal Stress for Fine Cu-TSV in 3D-Integration 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, Y. Sato, H. Hashimoto, K. W. Lee, M. Koyanagi

    2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 374-377 2014年

    出版者・発行元:IEEE

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    The constructive role played by the Thermal-chemical vapor deposited (CVD) organic polyimide (PI) liner in the Cu-TSVs with diameter or width (phi) varying from 3 mu m to 30 mu m has been studied meticulously for its thermal stability, leakage current (LC), capacitance, TSV-chain resistance, stress absorbing ability, and the Si-lattice distortion arising from thermo-mechanical stress (TMS). The measured LC values for the CVD deposited PI liner is in the order of 10(-13) to 10(-15) A, which is on par with the value obtained for the conventional SiO2 liner. The extremely low modulus value of PI liner helps not only to reduce the amount of Cu extrusion, but also maintain an uniform Cu-extrusion. We were able to achieve a conformal deposition of PI liner even in phi = 3 mu m via having the aspect ratio of 10 with the step coverage values of more than 0.8 (80%) at the TSV bottom corner. It was found that the d-space changing and thus the lattice stress is nearly five times smaller for the TSV with PI liner (similar to 200 MPa) than for the TSV with SiO2 liner (similar to 1000 MPa). Nearly zero-degradation of PI liner was confirmed from C1s, O1s, and N1s core-level x-ray photoelectron spectra taken before and after annealing at 400 degrees C. We obtained the resistance value of as low as 18 m Omega per 10 mu m-width TSV with 500 nm-thick PI liner fabricated on 12-inch wafer.

  171. Highly Dependable 3-D Stacked Multicore Processor System Module Fabricated Using Reconfigured Multichip-on-Wafer 3-D Integration Technology 査読有り

    K-W. Lee, H. Hashimoto, M. Onishi, S. Konno, Y. Sato, C. Nagai, J-C Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

    2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 669-672 2014年

    出版者・発行元:IEEE

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    A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.

  172. A Study on Positive Photosensitive Epoxy Resins Using Reaction Development Patterning (RDP) 査読有り

    Wei Min Zhou, Takafumi Fukushima, Masao Tomoi, Toshiyuki Oyama

    JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY 27 (6) 713-717 2014年

    出版者・発行元:TECHNICAL ASSOC PHOTOPOLYMERS,JAPAN

    DOI: 10.2494/photopolymer.27.713  

    ISSN:0914-9244

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    In this study, we successfully fabricated positive photosensitive epoxy resins based on the Reaction Development Patterning (RDP) by using B-staged polymers prepared by polyaddition between an epoxy base resin and an acid anhydride curing agent during mixing and prebaking processes. Application of RDP to the B-staged polymers afforded positive fine patterns by the use of 15-mol% sodium 2-aminoethoxide in ethanolamine / NMP mixtures. Furthermore, the fine epoxy patterns were not deformed after heat treatment for complete curing, indicating that the cress-linked epoxy patterns have high tolerability to thermal stresses. These results suggest the possibility of practical application of RDP-based positive photosensitive epoxy resins.

  173. Wafer Thinning for High-Density Three Dimensional Integration _ 12-Inch Wafer-Level 3D-LSI Program at GINTI 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, H. Hashimoto, Y. Sato, K. W. Lee, M. Koyanagi

    2014 25TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC) 57-61 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/ASMC.2014.6846977  

    ISSN:1078-8743

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    Thinning down large scale integrated-chip (LSI) wafers to below 50 mu m thickness is inevitable for the wafer-to-wafer (WtW) process as well as chip-to-wafer (CtW) or chip-tochip (CtC) processes in three-dimensional LSI integration. In this work we have optimized edge-trimming and back-grinding followed by chemical-mechanical polishing processes for WtW integration of 12-inch LSI wafer with thickness &lt;= 50 mu m. After optimization, we were able to achieve the total thickness variation (TTV) of less than 200 nm in the 50 mu m-thick LSI wafers. Also, it was found that the smaller TTV value of temporarily bonded wafer before wafer thinning greatly helps to reduce the TTV in the back-ground and polished wafers. We successfully integrated 50 mu m-thick 8- and 12-inch LSI wafers to their respective passive interposers using Cu-TSVs, and the electrical properties of TSVs were evaluated.

  174. A New Temporary Bonding Technology with Spin-on Glass and Hydrogenated Amorphous Si for 3D LSIs 査読有り

    H. Hashiguchi, T. Fukushima, H. Kino, K. -W. Lee, T. Tanaka, M. Koyanagi

    2014 INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING (ICEP) 74-77 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/ICEP.2014.6826664  

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    A new temporary bonding technology has been demonstrated, where both spin-on glass (SOG) and hydrogenated amorphous silicon (a-Si: H) were used as a bonding layer and as a debonding layer, respectively. Square chips were bonded to a glass wafer through the SOG layer and a-Si: H layer. The SOG bonding was capable of withstanding chip thinning and high-temperature chemical vapor deposition (CVD) processes. A XeCI excimer laser was irradiated to the a-Si: H layer through the glass wafers for debonding the chips. A novel via-Iast/backside-via 3D integration process using temporary SOG bonding was also proposed for advanced multichip-to-wafer 3D integration with self-assembly.

  175. A Resilient 3-D Stacked Multicore Processor Fabricated Using Die-level 3-D Integration and Backside TSV Technologies 査読有り

    K-W. Lee, H. Hashimoto, M. Onishi, Y. Sato, M. Murugesan, J-C Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 304-308 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2014.6897303  

    ISSN:0569-5503

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    A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a non-destructive failure analysis method to characterize highdensity TSVs integration, and bump joining qualities in the 3-D stacked multicore processor.

  176. Replacing the PECVD-SiO2 in the Through-Silicon Via of High-Density 3D LSIs with Highly Scalable Low Cost Organic Liner: Merits and Demerits 査読有り

    Murugesan Mariappan, Takafumi Fukushima, JiChel Beatrix, Hiroyuki Hashimoto, Yutaka Sato, Kangwook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 636-640 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2014.6897353  

    ISSN:0569-5503

    eISSN:2377-5726

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    A novel approach to suppress the conventional Cu-TSV induced thermo-mechanical stress in 3D-LSI chip is proposed, fabricated and tested. In this approach, a thermal-chemical-vapor-deposition grown organic poly-imide based polymer is conformally deposited along the side wall of the TSV. As-grown polymer was tested for its physical properties and mechanical properties, and was also evaluated for their role in minimizing the thermo-mechanical stress in vicinal and via-space Si. It was found that replacing the conventional SiO2 dielectric liner (sandwiched between the via-metal and Si) with organic polymer greatly helps in suppressing the thermo-mechanical stress, and thus the keep-out zone.

  177. Temporary Spin-on Glass Bonding Technologies for Via-Last/Backside-Via 3D Integration Using Multichip Self-Assembly 査読有り

    H. Hashiguchi, T. Fukushima, A. Noriki, H. Kino, K. -W. Lee, T. Tanaka, M. Koyanagi

    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 856-861 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2014.6897386  

    ISSN:0569-5503

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    In this study, we proposed and demonstrated self-assembly-based via-last/backside-via 3D integration using a temporary spin-on glass (SOG) bonding technology. A hydrogenated amorphous silicon (a-Si:H) was employed as a debonding layer. Known good dies (KGDs) were precisely self-assembled right side up on an electrostatic carrier wafer by surface tension of water, and then, the KGDs were fixed by applying DC voltage to the carrier. After that, the KGDs were temporarily bonded and transferred to another support glass wafer on which the a-Si:H and SOG layers were deposited. After multichip thinning, Cu-TSVs were formed on the KGDs. The resulting TSV daisy chains showed good electrical characteristics. The KGDs can be debonded with a 308-nm laser and transferred again to target interposer wafers.

  178. Minimization of Keep-Out-Zone (KOZ) in 3D IC by Local Bending Stress Suppression with Low Temperature Curing Adhesive 査読有り

    Hisashi Kino, Hideto Hashiguchi, Yohei Sugawara, Seiya Tanikawa, Takafumi Fukushima, Kangwook Lee, Mitsumasa Koyanagi, Tetsu Tanaka

    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 1110-1115 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2014.6897428  

    ISSN:0569-5503

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    Three dimensional IC (3D IC) has lots of through-Si vias (TSVs) and metal microbumps for electrical connection between stacked IC chips, and also has organic adhesives to enhance the mechanical strength of 3D IC. However, the coefficient of thermal expansion (CTE) mismatch between microbumps and organic adhesives generate the local bending stress in thinned IC chips. Therefore, Keep-Out-Zone (KOZ) for transistors must be considered in 3D IC design to eliminate characteristic fluctuations and degradations due to the local bending stress. In this study, for the first time, we evaluated the effects of low temperature curing adhesive on both the local bending stress and the resultant transistor characteristics for decrease in KOZ of 3D IC.

  179. Direct Multichip-to-Wafer 3D Integration Technology Using Flip-Chip Self-Assembly of NCF-Covered Known Good Dies 査読有り

    Yuka Ito, Mariappan Murugesan, Takafumi Fukushima, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi

    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 1148-1153 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2014.6897434  

    ISSN:0569-5503

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    We demonstrated surface tension-driven self-assembly and microbump bonding using NCF (non-conductive film)-covered chips with Cu/Sn-Ag microbumps for high-throughput and high-yield direct multichip-to-wafer 3D integration. The NCF is a promising candidate to completely fill gaps between fine-pitch microbumps, and is essential for realizing highly-reliable microbump-to-microbump interconnections. Here, by applying the self-assembly method with strong water surface tension, the NCF-covered chips were precisely aligned to hydrophilic assembly sites defined on host Si substrates in a face-down manner with alignment accuracies of approximately 1 mu m. The self-assembled chips having Cu/Sn-Ag microbumps covered with NCF were thermally compressed to obtain electrical joints between the chips and substrate after the self-assembly process. The resulting daisy chains showed good electrical characteristics with contact resistance of 53 m Omega/joint.

  180. Via-last/backside-via 3D integration using a visible-light laser debonding technique 査読有り

    T. Fukushima, M. Mariappan, J. C. Bea, H. Hashimoto, Y. Sato, M. Motoyoshi, K. W. Lee, M. Koyanagi

    Proceedings of 2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2014 13-70 2014年

    出版者・発行元:IEEE Computer Society

    DOI: 10.1109/LTB-3D.2014.6886152  

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    A visible-light laser debonding technique is introduced for via-last/backside-via 3D integration. Temporary bonding of 12-inch wafers with a temporary glue and the subsequent wafer thinning processes give small TTV within 1 μm by using an auto-TTV functions. Cu-TSV daisy chains with TSV diameters of 5 μm are formed in 50-μm-thick thinned Si wafers. © 2014 IEEE.

  181. Highly Thermoresistant Temporary Bonding/Debonding System without Organic Adhesives for 3D Integration 査読有り

    H. Hashiguchi, T. Fukushima, M. Murugesan, J. -C. Bea, H. Kino, K. -W. Lee, T. Tanaka, M. Koyanagi

    2014 4TH IEEE INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D) 14-14 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/LTB-3D.2014.6886153  

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    This study introduces a highly thermoresistant temporary bonding/debonding system. Known Good Dies (KGDs) were bonded through SOG to a support wafer. The KGDs were thinned, and Cu-TSVs were formed by via-last/backside-via processes. These KGDs can be readily debonded from the wafer by excimer laser irradiation to the a-Si: H layer on the wafer.

  182. Surface-Tension Driven Self-Assembly for VCSEL Chip Bonding to Achieve 3D and Hetero Integration 査読有り

    Y. Ito, T. Fukushima, K. -W. Lee, K. Choki, T. Tanaka, M. Koyanagi

    2014 4TH IEEE INTERNATIONAL WORKSHOP ON LOW TEMPERATURE BONDING FOR 3D INTEGRATION (LTB-3D) 15-15 2014年

    出版者・発行元:IEEE

    DOI: 10.1109/LTB-3D.2014.6886154  

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    Self-assembly with liquid surface tension was applied to tiny chips that were difficult to manipulate. Dummy chips that mimics VCSEL were aligned toward hydrophilic sites surrounding a hydrophobic area on an Si interposer. The alignment accuracies were 0 and -2.0 mu m in X and Y directions.

  183. Characterization of Vapor Deposited Polyimides and Process Integration with the Polymeric Liner for Via-Last/Backside-Via Cu-TSV Formation 査読有り

    Takafumi Fukushima, Murugesan Mariappan, Jichoel Bea, Kang-Wook Lee, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 720-721 2014年

  184. Stress Distribution Pattern in Cross-Sectional 3D-LSI Examined by u-XRD 査読有り

    M. Mariappan, J.C. Bea, T. Fukushima, K.W. Lee, M. Koyaangi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 724-725 2014年

  185. Investigation of the Plasma Damage by Etching Process for TSV Formation in Via-last Backside-via 3D IC 査読有り

    Y. Sugawara, H. Hashiguchi, S. Tanikawa, H. Kino, K. Lee, T. Fukushima, M. Koyanagi, T. Tanaka

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 726-727 2014年

  186. Tiny VCSEL Chip Self-Assembly for Advanced Chip-to-Wafer 3D and Hetero Integration 査読有り

    Takafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kangwook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi

    2014 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) O4 2014年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    A 12-channel vertical cavity surface emitting laser (VCSEL) chip was heterogeneously self-assembled to a glass interposer wafer by liquid surface tension as a driving force. The size of the VCSEL chip was 0.35 mm wide and 3 mm long. From the square dummy chips having structurally similar periphery to the VCSEL, the step structure at the chip edge was found to be significantly dependent on the alignment accuracies. From the rectangular dummy chips having the same sizes to the long VCSEL, the tiny chips were precisely self-assembled with alignment accuracies within 2 mu m even when they were manually placed on water droplets provided on host Si wafers. After self-assembly of the VCSEL chip and the subsequent thermal compression, the VCSEL was accurately positioned, successfully emitted 850-nm light, and exhibited no degradation of the I-V characteristics. This paper also presents our recent progress on the hybrid integration of chip-scale photonic devices with 3D/TSV technologies for optical interconnections.

  187. Effects of Electro-less Ni Layer as Barrier/Seed Layers for High Reliable and Low Cost Cu TSV 査読有り

    K. W. Lee, C. Nagai, A. Nakamura, J. C. Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

    2014 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) O13 2014年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    Effects of electro-less Ni layer as barrier/seed layers were evaluated for high reliable and low cost Cu TSVs. To electrically characterize the effectiveness of a Ni layer as barrier/seed layers for TSV application, we fabricated the trench MOS capacitor with 5 mu m dia. and 50 mu m depth TSV array. Via holes were successfully filled by Cu electro-plating by using Ni seed layer. To characterize the blocking property of the Ni layer to Cu diffusion, Cu atoms were intentionally diffused from Cu TSV by annealing at 300 degrees C and 400 degrees C. X-ray spectrometer (EDX) and C-t analysis results shows that Cu atoms not diffuse into the Si substrate via the Ni layer even after annealing at 400 degrees C. The Ni barrier layer has good blocking properties compared to a PVD barrier layer.

  188. Micro-XRD Investigation of Fine-Pitch Cu-TSV Induced Thermo-Mechanical Stress in High-Density 3D-LSI 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, K. W. Lee, M. Koyanagi, Y. Imai, S. Kimura, T. Tanaka

    2014 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) O18 2014年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    3D-LSI stack containing diametrically highly-scaled through-silicon-vias (TSVs) with diameter 2. m as well as conventional 20. m-width Cu-TSVs were carefully studied for the thermo-mechanical stress induced by Cu-TSVs via micro-X-ray diffraction using synchrotron radiation at Spring-8. It was observed that the TSV diameter has huge impact on the magnitude of resultant thermo-mechanical stress. The 20. m-width Cu-TSV has induced more than -1500 MPa of stress in the vicinal Si, while the 2. mwidth Cu-TSV induced less than -10 MPa of compressive stress in the surrounding Si. Therefore by decreasing the TSV diameter, one can virtually eliminate the thermo-mechanical stress induced by TSV.

  189. Die-Level 3-D Integration Technology for Rapid Prototyping of High-Performance Multifunctionality Hetero-Integrated Systems 査読有り

    Kang-Wook Lee, Yuki Ohara, Kouji Kiyoyama, Ji-Cheol Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 60 (11) 3842-3848 2013年11月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2013.2280273  

    ISSN:0018-9383

    eISSN:1557-9646

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    We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, fine-sized backside through silicon via (TSV) and novel detachable technologies are developed. In this paper, we demonstrated a prototype 3-D stacked image sensor system using the die-level 3-D integration technology. Three different functional chips of CMOS image sensor, correlated double sampling, and analog-to-digital converter, which were fabricated by different technologies, were processed to form fine-sized backside Cu TSV of 5-mu m diameter and metal microbumps in die level. Each chip was sequentially stacked after evaluating the basic function to form a known-good-die 3-D stacked system. The fundamental characteristics of each functional chip were successfully evaluated in the fabricated prototype 3-D stacked image sensor system.

  190. Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration 査読有り

    Kangwook Lee, Seiya Tanikawa, Mariappine Murugesan, Hideki Naganuma, Haro Shimamoto, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE ELECTRON DEVICE LETTERS 34 (8) 1038-1040 2013年8月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2013.2265336  

    ISSN:0741-3106

    eISSN:1558-0563

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    The Young's modulus (E) of Si substrate begin to noticeably decrease below 50-mu m thickness. The Young's modulus in 30-mu m thick Si substrate decreased by 30% compared to the modulus of 50-mu m thickness. In 30-mu m thick Si substrate, the lattice structure of Si atom is highly distorted. Large distortion of the lattice structure induces the Young's modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-mu m thickness is bonded to a Si interposer and thinned down to 50/40/30/20-mu m thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreasing of the chip thickness, especially dramatically degraded below 50-mu m thickness. The retention time of DRAM cell in the 20-mu m thick chip is shortened by similar to 40% compared to the 50-mu m thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects carrier recombination rates, consequently a shortening retention time of DRAM cell.

  191. Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration 査読有り

    Hisashi Kino, Ji Cheol Bea, Mariappan Murugesan, Kang, Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    Japanese Journal of Applied Physics 52 (4) 04CB11-1-04CB11-5 2013年4月

    DOI: 10.7567/JJAP.52.04CB11  

    ISSN:0021-4922 1347-4065

  192. Reductant-Assisted Self-Assembly with Cu/Sn Microbump for Three-Dimensional Heterogeneous Integration 査読有り

    Yuka Ito, Takafumi Fukushima, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 52 (4) 04CB09-1-04CB09-6 2013年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.7567/JJAP.52.04CB09  

    ISSN:0021-4922

    eISSN:1347-4065

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    To establish liquid-assisted assembly processes applicable to heterogeneous system integrations, we present flip-chip self-assembly of dies with Cu/Sn microbumps using the difference in droplet wetting between hydrophilic and hydrophobic areas. Flip-chip self-assembly is assisted by a water-soluble flux that has high surface tension comparable to that of pure water and contains an additive of a reducing agent for metal oxides. Control of the additive concentration in the flux provides high wettability contrast that enable spontaneous and precise alignment of chips to hydrophilic areas formed on substrates within 5 mu m in alignment accuracy. In the subsequent chip bonding process, the reductant can eliminate the metal oxide layer and improve the solder wettability of Sn to the corresponding electrode pads formed on the chips. In addition, we confirm, through electrical characteristic evaluation after thermal compression bonding, that the resulting daisy chain formed between the substrates and self-assembled chips with the flux shows sufficiently low contact resistance of below 20m Omega/bump without disconnection. (C) 2013 The Japan Society of Applied Physics

  193. 3D Hetero-Integration Technology with Backside TSV and Reliability Challenges 査読有り

    Kang-Wook Lee, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

    2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) 2013年

    出版者・発行元:IEEE

  194. Challenges in 3D Integration 査読有り

    Mitsumasa Koyanagi, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka

    SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 3 53 (3) 237-244 2013年

    出版者・発行元:ELECTROCHEMICAL SOC INC

    DOI: 10.1149/05303.0237ecst  

    ISSN:1938-5862

    eISSN:1938-6737

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    Three-dimensional (3D) LSIs using TSVs are indispensable to achieve high performance and low power LSIs with smaller form factor. A wafer-to-wafer (WtW) technology is suitable for stacking chips with high production yield such as DRAM since the overall yield after stacking rapidly decreases as the number of stacking layers increases. The chip-to-wafer (CtW) is suitable for stacking known good dies (KGDs). In addition, chips with different size which are fabricated using different process technologies can be stacked in the CtW technology. The inherent problem in the CtW technology, however, is low production throughput. To solve these problems, we have proposed a new 3D heterogeneous integration technology called a super-chip technology using self-assembly and electrostatic (SAE) bonding method.

  195. Revisiting the Silicon-Lattice in the High-Density 3D-LSIs - In the Perspective of Device Reliability 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, K. W. Lee, T. Tanaka, M. Koyanagi

    2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 172-175 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2013.6724578  

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    The dependence of device reliability on the lattice perfectness of the active silicon in the high-density 3D-LSIs containing through-silicon via (TSV) and micro-bump (mu-bump) is extensively investigated using hard X rays at SPring8. The reciprocal lattice space (RLS) data revealed that the Si-lattice structure is highly deteriorated owing to the thermo-mechanical (TM) stress exerted by Cu-TSVs and CuSn mu-bumps, and the local mechanical (LM) stress caused by local deformation. The TM stress caused by 20 mu m-width Cu-TSV at 300 degrees C has introduced (i) similar to 3 degrees of lattice-tilt (mis-orientation) and (ii) similar to 8.3 % reduction in lattice space (d) values for Si(004) lattice planes in the 3D-LSI chip. This d change has caused a maximum strain of -0.96 %, which corresponds to -1300 MPa of compressive stress. After the curing, the locally deformed upper thin LSI die with 30 mu m thickness witnessed as high as 4.9 % increase in d value, and the lattice tilt amount to 0.65 degree. More importantly, the lower 300 mu m-thick active/passive interposer has also experienced the lattice tilt and the change in d to the magnitude of around 0.2 degree and 0.4 %, respectively. We have also observed a degradation in the retention time for the stacked memory chip with a decrease in the chip thickness. The median retention time in the 30 mm-thick DRAM-chip was reduced to one-half the retention period for the 100 mu m-thick DRAM chip. We explain this phenomenon by deteriorated Young's modulus values and distorted lattice structures in the ultra-thin LSI Si chip. We were able to minimize the TM stress in the active Si to one-third from that of the initial value by sandwiching an organic stress-absorbing polymer between the dielectric layer and the Ta barrier layer, and the polymer is stable up to 400 degrees C.

  196. Characterization and Reliability of 3D LSI and SiP 査読有り

    K-W. Lee, M. Murugesan, Jichel Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 176-179 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2013.6724579  

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    Reliability challenges in 3D LSI associated with mechanical constraints induced by Cu TSVs, mu-bumps and crystal defects, crystallinity in thinned Si wafer and metal contamination induced by Cu diffusion from TSVs and thinned backside surface are mainly discussed. Mechanical stresses induced by Cu TSVs and mu-bumps are strongly dependent on design rules and process parameters. DRAM retention characteristics were severely degraded by Si thinning, especially below 30 mu-m thickness. Minority carrier lifetime was seriously degraded by Cu diffusion from Cu TSVs as the blocking property of barrier layer in TSV is not sufficient. A dry polish (DP) treatment produced a superior extrinsic gettering (EG) layer to Cu diffusion at the backside. We suggest the nondestructive failure analysis using X-ray CT-scan to characterize TSVs connection and mu-bumps joining in 3D stacked LSIs.

  197. 3次元システムLSI開発のためのチップレベルTSVプロセス 査読有り

    朴澤一幸, 古田太, 花岡裕子, 青木真由, 長田健一, 武田健一, LEE Kang Wook, 福島誉史, 小柳光正

    電子情報通信学会論文誌 C J96-C (11) 335-343 2013年

    ISSN:1345-2827

  198. Chip-to-Wafer 3D Stacking Using Self-Assembly and Electrostatic Temporary Bonding/Debonding 査読有り

    H. Hashiguchi, T. Fukushima, J. Bea, H. Kino, K.-W. Lee, T. Tanaka, M. Koyanagi

    Proceedings of International Conference on Electronics Packaging (ICEP) 502-505 2013年

  199. 3D Integration technologies using self-assembly and electrostatic temporary multichip bonding 査読有り

    T. Fukushima, H. Hashiguchi, J. Bea, M. Murugesan, K. W. Lee, T. Tanaka, M. Koyanagi

    Proceedings - Electronic Components and Technology Conference 58-63 2013年

    DOI: 10.1109/ECTC.2013.6575550  

    ISSN:0569-5503

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    We developed a new chip-to-wafer 3D integration technology using self-assembly and electrostatic (SAE) bonding. High-throughput multichip self-assembly with a high alignment accuracy within 1 μm was achieved by the SAE bonding technique. Self-assembled known good dies (KGDs) were temporarily bonded on SAE carriers by electrostatic bonding force. We implemented multichip transfer processes twice and then formed through-silicon vias (TSVs) for the self-assembled KGDs to fabricate 3D-stacked chips with Cu-TSVs and Cu/SnAg microbumps. By using the new multichip-to-wafer 3D integration process with SAE bonding, we obtained good electrical characteristics from the self-assembled KGDs having Cu-TSVs and Cu/SnAg microbumps. © 2013 IEEE.

  200. Impacts of static and dynamic local bending of thinned Si chip on MOSFET performance in 3-D stacked LSI 査読有り

    H. Kino, J. C. Bea, M. Murugesan, K. W. Lee, T. Fukushima, M. Koyanagi, T. Tanaka

    Proceedings - Electronic Components and Technology Conference 360-365 2013年

    DOI: 10.1109/ECTC.2013.6575596  

    ISSN:0569-5503

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    A three-dimensional (3-D) LSI has many lots of through-Si vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first time, we investigated impacts of the static and dynamic local bending on MOSFET characteristics using a novel test structure. © 2013 IEEE.

  201. Flux-Assisted Self-Assembly with Microbump Bonding for 3D Heterogeneous Integration 査読有り

    Yuka Ito, Takafumi Fukushima, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi

    2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 891-896 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2013.6575679  

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    We demonstrated a flip-chip self-assembly with Cu/Sn microbump bonding using surface tension of water-soluble fluxes. By using the self-assembly with the fluxes, 3-mm-square chips were aligned to hydrophilic assembly sites defined on a Si substrates in face-down bonding within approximately 2 mu m alignment accuracy. The flux-assisted self-assembly can realize not only the precise chip alignment by high surface tension of the water-soluble fluxes, but also the highly reliable bump bonding with Sn solder in a sequence of self-assembly process. Here, we employed several fluxes as liquids for flip-chip self-assembly and compared the resulting alignment accuracies by changing concentrations of the fluxes. In addition, after microbump bonding, we evaluated electrical characteristics. The resulting daisy chains showed good electrical characteristics with contact resistances of 17 m Omega/bump or below without solder bridges and bonding failures.

  202. Young Modulus of Si in 3D-LSIs and Reliability 査読有り

    M. Murugesan, J.C. Bea, T. Fukushima, K.W. Lee, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 38-39 2013年

  203. Self-Assembly and Electrostatic (SAE) Carrier Technology for Via-Last Backside-Via Multichip-to-Wafer 3D Integration 査読有り

    H. Hashiguchi, T. Fukushima, J.C. Bea, K.W. Lee, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 40-41 2013年

  204. Local Bending Stress Reduction with Room-Temperature Curing Adhesive for Decrease in Keep-out-Zone (KOZ) of 3D-IC 査読有り

    H. Kino, T. Fukushima, K.-W. Lee, M. Koyanagi, T. Tanaka

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 862-863 2013年

  205. Low-Temperature and High-Step-Coverage Polyimide TSV Liner Formation by Vapor Deposition Polymerization 査読有り

    T. Fukushima, M. Murugesan, J. Bea, K.W. Lee, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 866-867 2013年

  206. Self-Assembly Study to Precisely Align Dies Having Microbump Covered with Non-Conductive Film for Advanced Chip-to-Wafer 3D Integration 査読有り

    Y. Ito, T. Fukushima, K.W. Lee, K. Choki, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 988-989 2013年

  207. Mechanical Characteristics of Thin Dies/Wafers in Three-Dimensional Large-Scale Integrated systems 査読有り

    M. Murugesan, T. Fukushima, J. C. Bea, K. W. Lee, M. Koyanagi, T. Tanaka

    2013 24TH ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC) 66-69 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/ASMC.2013.6552777  

    ISSN:1078-8743

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    Ultra-thin silicon dies/wafers with thickness less than 30 mu m are profoundly used in the 3D-integration (vertical stacking of functional chips) and in the optoelectronics, in order to reduce the interconnect length and the resistive-capacitive delay. However, to improve the quality and fabrication yield of the three-dimensional large-scale integration (3D-LSI) process, it is important to have very good mechanical properties of such ultra-thin dies. Mechanical properties of the ultra-thin dies such as Young modulus (using nano-indenter), residual stress (by laser micro-Raman spectroscopy), and also the crystal orientation (by using electron back-scatter diffraction) were investigated with respect to different die thinning processes (chemical mechanical polishing, plasma etching, dry polishing, kai-dry polishing, poly grinding, ultra-poly grinding, #2000, etc), for various wafer thicknesses (10 mu m, 30 mu m, 50 mu m, 100 mu m, 200 mu m) and for the different kinds of the wafer (P/P+, P/P-, and wafer with internal gettering (IG) layer). The chemically-mechanically polished ultra-thin dies/wafers were found to be extraordinarily good in terms of mechanical strength as well as residual stress as compared to the ultra-thin dies/wafers fabricated by all other die thinning procedures.

  208. Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory 査読有り

    K-W Lee, S. Tanikawa, M. Murugesan, H. Naganuma, J-C Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2013.6702336  

    ISSN:2164-0157

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    The Young's modulus (E) of Si substrate begins to noticeably decrease below 50-mu m thickness. The Young's modulus in 30-mu m thick Si substrate decreased by approximately 30% compared to the modulus of 50-mu m thickness. In 30-mu m thick Si substrate, the lattice structure of Si substrate is highly distorted. Large distortion of the lattice structure induces the Young's modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-mu m thickness was bonded to a Si interposer and thinned down to 50/40/30/20-mu m thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreased chip thickness, especially dramatically degraded below 50-mu m thickness. The retention time of DRAM cell in 20-mu m thick chip is shortened by approximately 40% compared to the 50-mu m thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects a minority carrier generation lifetime, consequently shortening the retention time of DRAM cell.

  209. Highly Efficient TSV Repair Technology for Resilient 3-D Stacked Multicore Processor System 査読有り

    H. Hashimoto, T. Fukushima, K. W. Lee, M. Koyanagi, T. Tanaka

    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2013.6702338  

    ISSN:2164-0157

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    Over the scaling limit, 3D LSI using Through Silicon Vias (TSVs) brings in a huge number of additional logic gates. 3D LSI technology allows LSIs to adopt redundant or spare modules in order to raise its availability, dependability or resiliency. For such 3D LSI, the one of the most important matter is to increase the connectivity of vertical connections between stacked tiers. To achieve a resilient 3-D stacked multicore processor system, it is indispensable to develop TSV self-test and self-repair circuit. Especially, it is important to reduce redundant TSVs with large-pitch because of their area cost while increasing its repairability. The processor chip for the resilient 3-D stacked multicore processor has been designed and fabricated with highly area-efficient TSV repair technology.

  210. 3D Memory Chip Stacking by Multi-Layer Self-Assembly Technology 査読有り

    T. Fukushima, J. Bea, M. Murugesan, H. -Y. Son, M. -S. Sun, K. -Y. Byun, N. -S. Kim, K. -W. Lee, M. Koyanagi

    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2013.6702360  

    ISSN:2164-0157

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    Multi-layer 3D chip stacking by a surface-tension-driven self-assembly technique is demonstrated. After multi-layer self-assembly, memory chips having Cu-SnAg mu hump and Cu-TSVs are bonded on a substrate by thermal compression to confirm electrical joining between them. In addition, we investigate the impacts of wetting properties of chip/substrate surfaces, pump shapes, and p,bump layout on alignment accuracies of self-assembly. Good electrical characteristics are obtained from the TSV-mu bump daisy chains in the stacked memory chips.

  211. A Block-Parallel ADC with Digital Noise Cancelling for 3-D Stacked CMOS Image Sensor 査読有り

    K. Kiyoyama, Y. Sato, H. Hashimoto, K-W Lee, T. Fukushima, T. Tanaka, M. Koyanagi

    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2013.6702363  

    ISSN:2164-0157

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    An ADC design with a hierarchical double correlated double sampling for a three-dimensional (3-D) stacked CMOS image sensor is presented in this paper. To realize high speed, high resolution, and high sensitivity, we have proposed a block-parallel signal processing with 3-D structure. The block-parallel analog signal processing elements which compose CMOS image sensor, correlated double sampling (CDS) with programmable gain amplifier (PGA) array, and analog-to-digital converter (ADC) array. Spatial noise is the main contributor of image distortion in CMOS image sensor. Fixed pattern noise (FPN) does not change with time, and causes fixed distortion pattern on the image, hence FPN correction is especially challenging in the high speed CMOS image sensor. In the proposed sensor system, FPN of pixel output is removed by analog CDS. The digital CDS proposed in this paper is used to eliminate FPN caused by the device variation of analog circuits. The proposed ADC was designed with 90-nm CMOS technology. The proposed ADC with digital CDS occupies a very small circuit area of 160x160 mu m(2). The block-parallel ADC performance is characterized through differential nonlinearity (DNL) and integral nonlinearity (INL) measurements. The DNL is within -1.49/+1.89 LSB, and the INL is -1.92/+2.44 LSB, respectively. FPN is reduced to the range of +/- 1LSB by using proposed hierarchical double CDS function.

  212. Effect of CVD Mn Oxide Layer as Cu Diffusion Barrier for TSV 査読有り

    M. Murugesan, J. C. Bea, K. W. Lee, T. Fukushima, T. Tanaka, M. Koyanagi, Y. Sutou, H. Wang, J. Koike

    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2013.6702364  

    ISSN:2164-0157

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    The effectiveness of thermal chemical-vapor-deposited (CVD) manganese oxide (MnOx) for their application in the copper (Cu)-through-silicon-via (TSV) structure as a barrier layer was investigated by X-ray photo-electron spectroscopy (XPS), transmission electron spectroscopy (TEM), and capacitance-voltage (C-V) measurements. TEM data revealed the conformal growth of 20 nm-thick MnOx on the surface of plasma-TEOS SiO2 in the sidewall of TSV by thermal CVD. An excellent barrier property for MnOx over the thermal SiO2 was confirmed up to the maximum annealing temperature of 500 degrees C. In the case of plasma-TEOS SiO2, the barrier property was good up to 400 degrees C, but beyond that temperature, the barrier property was found deteriorated. On the contrary, the barrier performance of MnOx grown on the surface of ozone-TEOS SiO2 was found to be negligibly small. Even at room-temperature, we did observe the Cu2p signal emanating from MnOx/SiO2 region. Therefore, care must be taken while using either MnOx as a barrier layer upon ozone-TEOS SiO2 or ozone-TEOS SiO2 itself as a dielectric liner in along the side wall of TSVs, before integrating them into 3D-LSIs.

  213. Development of Via-Last 3D Integration Technologies Using a New Temporary Adhesive System 査読有り

    T. Fukushima, J. Bea, M. Murugesan, K. -W. Lee, M. Koyanagi

    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) 2013年

    出版者・発行元:IEEE

    DOI: 10.1109/3DIC.2013.6702383  

    ISSN:2164-0157

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    We develop new via-last backside-via 3D integration technologies using a unique temporary adhesive system in which visible-light laser is employed for wafer debonding from glass carriers. The advanced 3D and TSV researches are driven in order to fabricate Si interposers with high-density TSVs and highly integrated 3D hetero chips at Global INTegration Initiative (GINTI) as a new system integration research center. High-TTV wafer thinning, notch-free backside via formation, and void-less bottom-up Cu electroplating are performed, and the resulting TSV daisy chains show good I-V characteristics.

  214. Multichip-to-Wafer Three-Dimensional Integration Technology Using Chip Self-Assembly With Excimer Lamp Irradiation 査読有り

    Takafumi Fukushima, Eiji Iwata, Yuki Ohara, Mariappan Murugesan, Jichoel Bea, Kangwook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 59 (11) 2956-2963 2012年11月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2012.2212709  

    ISSN:0018-9383

    eISSN:1557-9646

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    Self-assembly of multichips with metal microbump electrodes is demonstrated by using water surface tension to increase the stacking throughput/yield and chip alignment accuracy of conventional chip-to-wafer 3-D integration. Three-dimensional microbump interconnects are formed by self-assembly with thermal compression at 200 degrees C. Chips with In-Au microbumps with pitches of 10 and 20 mu m are tightly bonded to Si wafers after the flip-chip self-assembly process, resulting in high alignment accuracies of 0.8 and 0.2 mu m in the x- and y-directions, respectively. Selective hydrophilization by 172-nm excimer lamp irradiation gives a high wettability contrast between hydrophilic chip bonding areas and hydrophobic surrounding areas on the wafers. This assists high-precision multichip self-assembly. A 2500-In-Au-microbump daisy chain is formed with a yield of 100% by flip-chip self-assembly, and it exhibits ohmic contact. The resistance is sufficiently low for 3-D large-scale integration application, being comparable to that obtained by conventional mechanical chip alignment.

  215. Instability-driven terahertz emission and injection locking behavior in an asymmetric dual-grating-gate HEMT with a vertical cavity structure 査読有り

    T. Watanabe, T. Fukushima, Y. Kurita, A. Satou, T. Otsuji

    ICMNE: Int. Conf. on Micro and Nanoelectronics, Moscow, Russia, Oct. 1-5, 2012. 1 (1) P1-43 2012年10月3日

  216. Pillar-shaped stimulus electrode array for high-efficiency stimulation of fully implantable epiretinal prosthesis 査読有り

    Kang-Wook Lee, Yoshinobu Watanabe, Chikashi Kigure, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    JOURNAL OF MICROMECHANICS AND MICROENGINEERING 22 (10) 2012年10月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.1088/0960-1317/22/10/105015  

    ISSN:0960-1317

    eISSN:1361-6439

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    We developed a pillar-shaped microelectrode array (MEA) with varying heights for enhancing the spherical conformity of fully implantable epiretinal prosthesis comprising a 3D stacked retinal chip. The fabricated MEA is composed of 100 pillar electrodes with heights ranging from 60 to 80 mu m. The Pt-coated Cu pillar electrode with a surface diameter of 70 mu m and a height of 75 mu m and the Pt planar electrode with a surface diameter of 70 mu m have 24.6 and 125 k Omega impedances, respectively, at 1 kHz in vitro experiment. The pillar electrode shows lower impedance than the planar electrode because of a larger surface area. However, to avoid cross-talking between pillar electrodes, we developed a sidewall passivation process of the pillar electrode by using the surface tension of polyimide. The impedance of the isolated pillar electrode 116 k Omega at 1 kHz is similar to the impedance of the planar electrode, because they have similar electrode surface areas. The pillar-shaped MEA shows a better spherical conformity.

  217. Impact of Cu Contamination on Memory Retention Characteristics in Thinned DRAM Chip for 3-D Integration 査読有り

    Kangwook Lee, Takaharu Tani, Hideki Naganuma, Yuki Ohara, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE ELECTRON DEVICE LETTERS 33 (9) 1297-1299 2012年9月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2012.2202631  

    ISSN:0741-3106

    eISSN:1558-0563

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    The influence of Cu diffusion at the backside surface of a thinned dynamic random access memory (DRAM) chip for 3-D integration on memory retention characteristics was electrically evaluated. A DRAM test chip was bonded to a Si interposer at 300 degrees C for 2 min and thinned down to 30-mu m thickness. The DRAM cell characteristics, which show 50% failure at 200 mu s, were not degraded from the packaged sample (prethinning) even after chip bonding, chip thinning, and no-Cu postannealing for 30 min at 300 degrees C. Meanwhile, the DRAM cell array shows 50% failure at 70 mu s after an intentional Cu diffusion from the backside surface for 30 min at 300 degrees C. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface in active areas and cause functional failures such as increasing carrier recombination rate, consequently shortening retention time. However, the NMOS transistor characteristics show no significant change even after Cu diffusion. The on-current performance characterized by majority carriers is not an effective criterion to characterize sensitively the Cu contamination effect.

  218. High-step-coverage Cu-lateral interconnections over 100 μm thick chips on a polymer substrate—an alternative method to wire bonding 査読有り

    M Murugesan, T Fukushima, K Kiyoyama, J-C Bea, T Tanaka, M Koyanagi

    JOURNAL OF MICROMECHANICS AND MICROENGINEERING 22 (8) 2012年8月

    出版者・発行元:None

    DOI: 10.1088/0960-1317/22/8/085033  

    ISSN:0960-1317

    eISSN:1361-6439

  219. Low-Resistance Cu-Sn Electroplated-Evaporated Microbumps for 3D Chip Stacking 査読有り

    M. Murugesan, Y. Ohara, T. Fukushima, T. Tanaka, M. Koyanagi

    JOURNAL OF ELECTRONIC MATERIALS 41 (4) 720-729 2012年4月

    出版者・発行元:SPRINGER

    DOI: 10.1007/s11664-012-1949-1  

    ISSN:0361-5235

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    Low-resistance copper-tin (Cu-Sn) microbumps, with sizes varying from 5 mu m x 5 mu m to 20 mu m x 20 mu m and formed by electroplating-evaporation bumping (EEB) technology for three-dimensional integration of large-scale integrated chips, have been evaluated for their microstructure and electrical resistance. It was inferred from x-ray diffraction data that the formation of low-resistance Cu3Sn intermetallic compound (IMC) is facilitated at higher bonding temperature. Electron probe microanalysis mapping showed that, even before bonding, Cu-Sn IMCs were formed at the interface between Cu and Sn, whereas they were sandwiched between the Cu of the upper and lower microbumps after bonding. Electron backscatter diffraction analysis revealed that the crystal orientation of Sn grains was sharply localized in the (100) orientation for physical vapor deposited (PVD) sample, while electroplated Sn film exhibited a mixed crystal orientation in all (100), (110), and (001) axes. A resistance value of similar to 35 m Omega per bump was obtained for Cu-Sn microbumps with area of 400 mu m(2), which is several times lower than the resistance value reported for Cu-Sn microbumps fabricated by a pure electroplating method. The low resistance value obtained for EEB-formed Cu-Sn microbumps after bonding is explained by (i) the reduced surface roughness for evaporated Sn, (ii) the high degree of crystal grain orientation resulting from layer-by-layer growth in the PVD Sn, despite their smaller grain size, and (iii) the absence of impurity segregation at grain boundaries.

  220. Impact of Data Transmission over 10 Gbps on High-Density and Low-Cost Optoelectronic Module with Polynorbornene Waveguides 査読有り

    Yuka Ito, Shinsuke Terada, Shinya Arai, Makoto Fujiwara, Tetsuya Mori, Koji Choki, Takafumi Fukushima, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 51 (4) 04DG01-1-04DG01-4 2012年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.1143/JJAP.51.04DG01  

    ISSN:0021-4922

    eISSN:1347-4065

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    We proposed a rigid/flex optoelectronic (O/E) module with 48-channel polymeric waveguides for short-distance board-level optical interconnection. A flexible O/E test module was fabricated in the following two steps by using standard packaging processes. First, two vertical cavity surface emitting laser diodes (VCSELs) and one VCSEL driver (VD) were flip-chip bonded to a completed flexible printed circuit board (PCB), and two photodiodes (PDs) and one transimpedance amplifier/limiting amplifier (TIA/LA) to another flexible PCB. Second, the two flexible PCBs were attached with a polynorbornene (PNB) sheet in which high-density PNB waveguides were formed by UV exposure. Active areas of VCSELs and PDs on the flexible PCBs were aligned to micromirrors of the waveguides with -6 mu m offset toward the signal propagation direction. We successfully demonstrated data transmission over 10 Gbps and low inter-channel crosstalk of less than -20 dB was achieved in the flexible O/E test module with 120-mm-long and 62.5-mu m-pitch waveguides. (C) 2012 The Japan Society of Applied Physics

  221. Through-Silicon Photonic Via and Unidirectional Coupler for High-Speed Data Transmission in Optoelectronic Three-Dimensional LSI 査読有り

    Akihiro Noriki, Kangwook Lee, Jicheol Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE ELECTRON DEVICE LETTERS 33 (2) 221-223 2012年2月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2011.2174608  

    ISSN:0741-3106

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    We develop Si-core through-silicon photonic via (TSPV) and unidirectional coupler for low-loss and high-speed data transmission in an optoelectronic 3-D LSI. The TSPVs, comprising a Si-core and SiO2 cladding, were fabricated simultaneously with Cu TSVs. The characteristics of light confinement of the TSPV were measured using a near-field pattern measurement. The spot light area was well confined within the TSPV without interference from the lights. The optical intensity that passed through the TSPV was 20% higher than that which passed through the Si substrate. The unidirectional optical coupler with two mirrors showed higher coupling efficiency. Laser light can be efficiently propagated to a planar Si waveguide through the TSPV and the unidirectional coupler.

  222. Heterogeneous 3D Integration Technology and New 3D LSIs 査読有り

    Mitsumasa Koyanagi, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka

    2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012) 240-243 2012年

    出版者・発行元:IEEE

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    A new 3-D integration technology and heterogeneous integration technology called a super-chip integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip integration. Possibilities for new system-on-a chip and heterogeneous LSIs by 3D super-chip integration such as 3D stacked multicore processor with self-test and self-repair function, GPU stacked 3D image sensor with extremely fast processing speed and 3D stacked reconfigurable processor with spin memory are discussed.

  223. Chip-Based Hetero-Integration Technology for High-Performance 3D Stacked Image Sensor 査読有り

    Yuki Ohara, Kang Wook Lee, Koji Kiyoyama, Shigehide Konno, Yutaka Sato, Shuichi Watanabe, Atsushi Yabata, Harufumi Kobayashi, Tadashi Kamada, Jichel Bea, Mariappan Murugesan, Hiroyuki Hashimoto, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2012 2ND IEEE CPMT SYMPOSIUM JAPAN 2012年

    出版者・発行元:IEEE

    ISSN:2373-5449

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    We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

  224. Minimizing the Local Deformation Induced around Cu-TSVs and CuSn/InAu-Microbumps in High-Density 3D-LSIs 査読有り

    M. Murugesan, H. Kobayashi, H. Shimamoto, F. Yamada, T. Fukushima, J. C. Bea, K. W. Lee, T. Tanaka, M. Koyanagi

    2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 657-660 2012年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2012.6479124  

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    One of the most serious reliability issues, the local deformation produced in the stacked LSI die/wafer with respect to the die thickness and the sub-surface structures formed after several stress-relief methods are systematically and extensively studied. From the electron backscatter diffraction (EBSD) analysis, a more than one degree (&gt;1 degrees) of local misorientation is created in the stacked LSI Si around mu-bump region. This induces a large tensile stress above the mu-bump region and relatively small compressive stress in the bump-space region, which leads to an enhancement in the n-MOSFET mobility in the mu-bump region and decrease in mobility at bump-space region. As compared to CuSn system, the InAu mu-bump induced huge amount of tensile stress (&gt;300 MPa) in the stacked LSI die even for the bonding temperature of 200 degrees C. The groove structures or scratches found at the background surface after stress relief by plasma etching (PE) or Dry Polishing (DP) severely deteriorates the device characteristics after stacking, owing to the enhanced local deformation as against the stress relief method of chemical mechanical polishing (CMP). Even after 500 cycles of temperature cycle (TC) test, a 20 mu m-width Cu-TSV array with 40-mu m pitch values induces not only around -570 MPa of compressive stress in the stacked LSI die, but also a large variation in the induced stress values between different TSVs in the same array. For the LSI die/wafer thickness of anything less than 50 mu m, the Young modulus (E) and Hardness (H) of the thinned die no longer behaves like a bulk single crystal Si, which severely increases the reliability risks in the highly integrated 3D-LSIs.

  225. Characterization of Chip-level Hetero-Integration Technology for High-Speed, Highly Parallel 3D-Stacked Image Processing System 査読有り

    K-W Lee, Y. Ohara, K. Kiyoyama, S. Konno, Y. Sato, S. Watanabe, A. Yabata, T. Kamada, J-C Bea, H. Hashimoto, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

    2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 785-788 2012年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2012.6479156  

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    We demonstrate the chip-based 3D heterogeneous integration technology for realizing highly parallel 3D-stacked image sensor. Three kinds of chips, CMOS image sensor chip, analog circuit chip, and ADC array chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.

  226. New Chip-to-Wafer 3D Integration Technology Using Hybrid Self-Assembly and Electrostatic Temporary Bonding 査読有り

    T. Fukushima, H. Hashiguchi, J. Bea, Y. Ohara, M. Murugesan, K. -W. Lee, T. Tanaka, M. Koyanagi

    2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 789-792 2012年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2012.6479157  

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    We proposed a new chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding. In the hybrid self-assembly-based chip-to-wafer 3D integration (HSA-CtW), liquid surface-tension-driven chip self-assembly is combined with high-speed robotic pick-and-place chip assembly and electrostatic multichip temporary bonding. Hybrid self-assembly can realize high-throughput chip assembly of above 10,000 chips/hour with a high alignment accuracy of &lt; 1 mu m. The electrostatic multichip temporary bonding technique enabled stress-free direct bonding of self-assembled chips. We obtained good electrical characteristics from 3D stacked chips fabricated by HSA-CtW using Cu/SnAg microbumps and Cu-TSVs.

  227. Impact of Cu Diffusion from Cu Through-Silicon Via (TSV) on Device Reliability in 3-D LSIs Evaluated by Transient Capacitance Measurement 査読有り

    Kangwook Lee, Jichel Bea, Yuki Ohara, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) 2B.4.1-2B.4.6 2012年

    出版者・発行元:IEEE

    DOI: 10.1109/IRPS.2012.6241777  

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    The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the wafer surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. Meanwhile, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min at 300 degrees C, but show significant degradation after the initial annealing for 5min at 400 degrees C. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

  228. Thermomechanical reliability challenges induced by high density Cu TSVs and metal micro-joining for 3-D ICs 査読有り

    Kangwook Lee, Itakafumi Fukushima, Tetsu Tanaka, Imitsumasa Koyanagi

    2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) 5F.2.1-5F.2.4 2012年

    出版者・発行元:IEEE

    DOI: 10.1109/IRPS.2012.6241860  

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    The thermo-mechanical reliability challenges induced by high-density Cu TSVs and metal micro-joining are discussed. Cu TSV with the diameter of 20-mu m induced the maximum compressive stress of similar to 1 GPa at the Si substrate adjacent to them after annealed at 300 degrees C. Depart from Cu TSV, the stress/strain in Si substrate changed to tensile stress and finally going to zero, where the TSV pitch is larger than twice of TSV size. However, in high density Cu TSV array with small TSV pitch, the Si substrate within small TSV spacing keep large compressive stress, which will seriously affect the mobility in active Si area, and thus device characteristics. Also, these large compressive stress leads to not only extrusion and peeling of Cu TSV, but also die cracking. The thermo-mechanical stress was produced during the bonding using high-density metal bumps. CuSn bump of 20-mu m size has induced compressive stress of 140MPa beneath Si wafer surface, and it penetrates deeper area with large stress value after the bonding. The drain current and electron mobility of n-MOSFET which was located 15 mu m distance from microbump are changed by similar to 10 % due to the local tensile stress of 500 MPa induced by microbump. Electron mobility changed varying with the distance from microbump. Influences of mechanical stress induced by Cu TSVs and microbump-underill joining on device characteristics were also evaluated.

  229. Self-assembly-based 3D integration technologies 査読有り

    T. Fukushima, J. Bea, M. Murugesan, K. W. Lee, T. Tanaka, M. Koyanagi

    Proceedings of 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2012 151-152 2012年

    DOI: 10.1109/LTB-3D.2012.6238075  

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    We have proposed and developed massively parallel chip self-assembly technologies using surface tension of liquid for advanced chip-to-wafer 3D integration. Here, we introduce flip-chip self-assembly in batch processing and reconfigured wafer-to-wafer 3D integration as a new chip-to-wafer 3D integration approach using self-assembly. © 2012 IEEE.

  230. Non-Conductive Film and Compression Molding Technology for Self-Assembly-Based 3D Integration 査読有り

    T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K. -W. Lee, T. Tanaka, M. Koyanagi

    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 393-398 2012年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2012.6248860  

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    Two key technologies consisting of chip-to-wafer bonding through a non-conductive film (NCF) and wafer-level packaging using compression molding were studied for self-assembly-based 3D integration, especially reconfigured wafer-to-wafer stacking. 4-mm-by-5-mm chips having 20-mu m-pitch Cu-SnAg microbumps were successfully bonded to wafers through NCF. The resulting daisy chain obtained from the chip-to-wafer structure showed low contact resistance of approximately 50 m Omega/bump. Compression molding was implemented to a chip-on-wafer structure. Grinding of the chip-on-wafer structure gave low total thickness variation (TTV) within 1 mu m and the following CMP led good planarization capability.

  231. Locally Induced Stress in Stacked Ultrathin Si wafers: XPS and mu-Raman study 査読有り

    M. Murugesan, H. Nohira, H. Kobayashi, T. Fukushima, T. Tanaka, M. Koyanagi

    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 625-629 2012年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2012.6248896  

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    Induced local stress arising from local deformation of top silicon die in the vertically stacked LSI die has been investigated via x-ray photoelectron spectroscopy (XPS) and micro-Raman spectroscopy (mu RS). The large positive shift in the core level Si-2s and Si-2p XP spectra for the thinned die revealed that thinned dies were under heavy stress/strain even before stacking. The core level binding energy shift, Delta Eb for Si-1s core level and the relative chemical shift Delta Er for Si in the vertically integrated die system showed that the stacked Si dies were under different stresses in the mu-bump and the bump-space regions. It was also inferred from the mu RS results that the stacked 10 mu m-thick-Si dies were under large tensile strain of &gt;1.5 GPa and a relatively small compressive stress of similar to 0.5 GPa in the mu-bump and bump-space region, respectively.

  232. Optical interconnect technology for 3-D LSI and neural engineering applications 査読有り

    T. Tanaka, A. Noriki, T. Kukushima, K-W Lee, M. Koyanagi

    2012 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC) 2012年

    出版者・発行元:IEEE

  233. Demonstration of inter-chip data transmission in a three-dimensional stacked chip fabricated by chip-level TSV integration 査読有り

    Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Osada, Kenichi Takeda, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi

    Digest of Technical Papers - Symposium on VLSI Technology 175-176 2012年

    DOI: 10.1109/VLSIT.2012.6242518  

    ISSN:0743-1562

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    Successful 3D integration of a stacked chip fabricated by a "chip-level through-silicon-via (TSV)" process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance, and wiring capacitance of the surrounding Cu/low-k interconnections. © 2012 IEEE.

  234. 10μm-Pitch In-Au Microbump Interconnection by Chip Self-Assembly with Excimer Lamp Irradiation for 3D LSI Applications 査読有り

    Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 46-47 2012年

  235. Grapho-Assembly Technology for Sub-Micron Accuracy 3D Chip Stacking with High-Density Through-Si Vias and Metal Microbumps 査読有り

    Takafumi Fukushima, Masaki Onishi, Jichoel Bea, Sayuri Hioki, Mariappan Murugesan, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 48-49 2012年

  236. The Influence of Cu Diffusion from Cu Through-Silicon Via(TSV) on Device Reliability in the 3D LSI by Using C–V and C–t Measurements 査読有り

    Jichoel Bea, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 50-51 2012年

  237. Analysis of Local Bending Stress Effect on CMOS Performance Fabricated in Thinned Si Chip for Chip-to-Wafer 3D Integration 査読有り

    H. Kino, J-C. Bea, M. Murugesan, K-W. Lee, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 52-53 2012年

  238. Optoelectronic Heterogeneous Integration Technology, Using Reductant-Assisted Self-Assembly with Cu/Sn Microbump 査読有り

    Yuka Ito, Takafumi Fukushima, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1176-1177 2012年

  239. Electrostatic Temporary Bonding Technology and TSV Formation for Reconfigured Wafer-to-Wafer 3D Integration 査読有り

    Hideto Hashiguchi, Jichoel Bea, Yuki Ohara, Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1183-1184 2012年

  240. Reliability Challenges in High-Density 3D-Integration 査読有り

    M. Murugesan, H. Kobayashi, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1185-1186 2012年

  241. Cu Contamination Assessment and Control in 3-D Integration 査読有り

    Mitsumasa Koyanagi, Kang Wook Lee, Jicheol Bea, Takafumi Fukushima, Tetsu Tanaka

    The 222nd ECS Meeting: PRiME (Pacific Rim Meeting) 2012年

  242. Long Term Retention Characteristics of MOS Memory Devices with Self-Assembled Tungsten Nano-Dot Dispersed in Silicon Nitride 査読有り

    Y. Pei, T. Fukushima, T. Tanaka, M. Koyanagi

    Materials Research Society (MRS) 2008 Spring Meeting, Symposium F: Materials Science and Technology for Nonvolatile Memories, F2.4 2012年

  243. Multichip Self-Assembly Technology for Advanced Die-to-Wafer 3-D Integration to Precisely Align Known Good Dies in Batch Processing 査読有り

    Takafumi Fukushima, Eiji Iwata, Yuki Ohara, Mariappan Murugesan, Jichoel Bea, Kangwook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 1 (12) 1873-1884 2011年12月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TCPMT.2011.2160266  

    ISSN:2156-3950

    eISSN:2156-3985

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    An advanced die-to-wafer 3-D integration using a surface-tension-driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5 degrees and 115 degrees. Therefore, various sizes of chips (3 x 3 mm, 5 x 5 mm, 4 x 9 mm, and 10 x 10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch.

  244. Advanced die-to-wafer 3D integration platform: Self-assembly technology 査読有り

    Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    3D Integration for VLSI Systems 153-174 2011年9月30日

    出版者・発行元:Pan Stanford Publishing Pte. Ltd.

    DOI: 10.4032/9789814303828  

  245. Evaluation of Cu Diffusion From Cu Through-Silicon Via (TSV) in Three-Dimensional LSI by Transient Capacitance Measurement 査読有り

    Jichel Bea, Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE ELECTRON DEVICE LETTERS 32 (7) 940-942 2011年7月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2011.2141109  

    ISSN:0741-3106

    eISSN:1558-0563

    詳細を見る 詳細を閉じる

    The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI has been electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10- and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 100-nm-thick Ta layer exhibit no change after annealing up to 60min at 300 degrees C. However, the C-t curves of the trench capacitors with 10-nm-thick Ta layer were severely degraded even after the initial annealing for 5 min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.

  246. MOSFET Nonvolatile Memory with High-Density Cobalt-Nanodots Floating Gate and HfO2 High-k Blocking Dielectric 査読有り

    Yanli Pei, Chengkuan Yin, Toshiya Kojima, Ji-Cheol Bea, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON NANOTECHNOLOGY 10 (3) 528-531 2011年5月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TNANO.2010.2050331  

    ISSN:1536-125X

    詳細を見る 詳細を閉じる

    We report high-performance MOSFET nonvolatile memory with high-density cobalt-nanodots (Co-NDs) floating gate (the density is as high as 4-5 x 10(12)/cm(2) and the size is similar to 2 nm) and HfO2 high-k blocking dielectric. The device is fabricated using a gate-last process. A large memory window, high-speed program/erase (P/E), long retention time, and excellent endurance till 10(6) P/E cycles are obtained. In addition, the discrete Co-NDs make dual-bit operation successful. The high performance suggests that high work-function Co-NDs combined with high-k blocking dielectric have a potential as a next-generation nonvolatile-memory candidate.

  247. Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems 査読有り

    Kang-Wook Lee, Akihiro Noriki, Kouji Kiyoyama, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE TRANSACTIONS ON ELECTRON DEVICES 58 (3) 748-757 2011年3月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2010.2099870  

    ISSN:0018-9383

    eISSN:1557-9646

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    We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

  248. Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration 査読有り

    Takafumi Fukushima, Takayuki Konno, Eiji Iwata, Risato Kobayashi, Toshiya Kojima, Mariappan Murugesan, Ji-Chel Bea, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    MICROMACHINES 2 (1) 49-68 2011年3月

    出版者・発行元:MDPI AG

    DOI: 10.3390/mi2010049  

    ISSN:2072-666X

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    New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D) and hetero integration of complementary metal-oxide semiconductors (CMOS) and microelectromechanical systems (MEMS). By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF) aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4. m. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

  249. Electrical evaluation of Cu contamination behavior at the backside surface of a thinned wafer by transient capacitance measurement 査読有り

    K-W Lee, J-C Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    SEMICONDUCTOR SCIENCE AND TECHNOLOGY 26 (2) 2011年2月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.1088/0268-1242/26/2/025007  

    ISSN:0268-1242

    eISSN:1361-6641

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    The behavior of Cu contamination at the backside surface of a thinned wafer in a three-dimensional (3D) LSI was electrically evaluated by capacitance-time (C-t) analysis. In order to electrically evaluate Cu diffusion characteristics, MOS capacitors were fabricated using the thinned wafer of 50 mu m and 100 mu m thickness, respectively. For an accelerated Cu diffusion test, a thin Cu layer was deposited at the back surface as a contamination source. Cu atoms were artificially diffused into the substrate by annealing at 200 degrees C and 300 degrees C for various times in nitrogen ambient. The C-t curves of a MOS capacitor formed on a 100 mu m thickness substrate were degraded even after annealing at 200 degrees C. It means that Cu atoms diffuse into the active region and reach the Si-SiO2 interface during relatively low-temperature annealing. By increasing time and temperature, the transient time t(f) is more seriously decreased. The C-t curves of the MOS capacitor formed on the Si substrate of 50 mu m thickness were more seriously degraded even after the initial annealing at 200 degrees C for 5 min. These results indicate that the Cu contamination issue becomes more severe in a thinner Si substrate. This study shows that C-t analysis is a highly promising method to electrically evaluate the influence of Cu contamination on device reliability in the 3D LSI.

  250. Chip-level TSV integration for rapid prototyping of 3D system LSIs 査読有り

    Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262952  

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    For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called "chip-level TSV integration") was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection. Chip-level TSV integration will provide rapid prototyping of 3D system LSIs based on various chips with TSVs. © 2011 IEEE.

  251. Stacked SOI pixel detector using versatile fine pitch μ-bump technology 査読有り

    Makoto Motoyoshi, Junichi Takanohashi, Takafumi Fukushima, Yasuo Arai, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262959  

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    This Paper presents on 3D stacking technology with 2.5μm x 2.5μm In (Indium) bump connections with adhesive injection [1]. Instead of using the simple test device, this technology has been verified using the actual circuit level test chip. And it was found that the completion of stacking process is affected by the layout pattern of stacked each tier. In order to minimize those effects, we have optimized the layout, process parameter and device structure. © 2011 IEEE.

  252. 3D Integration Technology and Reliability Challenges 査読有り

    Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS) 2011年

    出版者・発行元:IEEE

    ISSN:2151-1225

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    Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of the super-chip are described. In addition, the reliability challenges such as the mechanical stress/strain and Cu contamination are discussed. Cu TSVs with the diameter of 20-ae m induced the maximum compressive stress of similar to 1 GPa at the Si substrate adjacent to them after annealed at 300 degrees C. Mechanical strain/stress and crystal defects were produced in extremely thin wafer of 10 mu m thickness not only during the thinning but also after the bonding using finepitch, high-density metal bump. The influences of Cu contamination from the back surface of the thinned wafer and Cu TSVs on device reliability were evaluated by C-t analysis. The C-t curves of MOS capacitors formed in the thinned wafer without IG layer were seriously degraded after annealed at 200 degrees C. The DP stress-relief EG layer at the backside of the thinned wafer exhibited good Cu retardation performance. The C-t curves of the MOS trench capacitor with 10-nm thick Ta barrier layer in Cu TSV were severely degraded after the initial annealing at 300 degrees C for 5min. The degraded C-t curve indicates that the generation lifetime of minority carrier is significantly reduced by Cu contamination.

  253. Cu Retardation Performance of Extrinsic Gettering Layers in Thinned Wafers Evaluated by Transient Capacitance Measurement 査読有り

    K-W. Lee, J-C. Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    JOURNAL OF THE ELECTROCHEMICAL SOCIETY 158 (8) H795-H799 2011年

    出版者・発行元:ELECTROCHEMICAL SOC INC

    DOI: 10.1149/1.3597317  

    ISSN:0013-4651

    eISSN:1945-7111

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    The behaviors of Cu diffusion at backside surface of thinned wafer with extrinsic gettering layer in three-dimensional (3-D) LSI were electrically and quantitatively evaluated by capacitance-time (C-t) analysis and Zerbst plot. In order to electrically evaluate Cu diffusion characteristics, MOS capacitors were fabricated using the thinned wafer of 100-mu m thickness. To compare the gettering ability to Cu diffusion, three types of extrinsic gettering layers were prepared on the back surface of thinned wafers by mechanical grinding and following CMP, DP, and UPG methods. For accelerated Cu diffusion test, thin Cu layer was deposited on the back surface as a contamination source and Cu atoms were artificially diffused into the substrate by annealing at 300 degrees C for various times. In the CMP treated wafer, the C-t curves of MOS capacitor are most severely degraded and transient time t(f) is more seriously decreased after annealing. The gettering efficiency of the DP treated wafer is enhanced about 50% as compared with the CMP treated wafer and 20% as compared with the UPG treated wafer, respectively, after annealing for 60 min. The DP treated wafer shows most good gettering ability to Cu diffusion. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3597317] All rights reserved.

  254. Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application 査読有り

    Yanli Pei, Tatsuro Hiraki, Toshiya Kojima, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    TECHNOLOGY EVOLUTION FOR SILICON NANO-ELECTRONICS 470 140-+ 2011年

    出版者・発行元:TRANS TECH PUBLICATIONS LTD

    DOI: 10.4028/www.scientific.net/KEM.470.140  

    ISSN:1013-9826

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    In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bottom layer. A large memory window and long retention time were obtained. However, the thermal electron excitation is dominant for the electron discharge process during retention. How to reduce the defects in MND layer is important for further improving of memory characteristics.

  255. 三次元集積化技術とヘテロインテグレーション 査読有り

    小柳光正, 福島誉史, LEE Kangwook, 田中徹

    電子情報通信学会論文誌 C J94-C (11) 355-364 2011年

    ISSN:1345-2827

  256. 三次元チップ積層のための電解めっきと蒸着法を用いた高密度Cu/Snマイクロバンプ形成技術 査読有り

    大原悠希, 乗木暁博, LEE Kang-Wook, 福島誉史, 田中徹, 田中徹, 小柳光正

    電子情報通信学会論文誌 C J94-C (11) 394-401 2011年

    ISSN:1345-2827

  257. シリコンバンプ上に積層した薄化チップの曲げ応力とデバイス特性評価 査読有り

    木野久志, MURUGESAN Mariappan, 小島俊哉, 福島誉史, 田中徹, 田中徹, 小柳光正

    電子情報通信学会論文誌 C J94-C (11) 411-418 2011年

    ISSN:1345-2827

  258. Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement 査読有り

    Jichel Bea, Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE ELECTRON DEVICE LETTERS 32 (1) 66-68 2011年1月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/LED.2010.2087004  

    ISSN:0741-3106

    eISSN:1558-0563

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    The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitance-time (C-t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-mu m thickness. The (C-t) curves of the MOS capacitor were severely degraded even after initial annealing at 300 degrees C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C-t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.

  259. High Density 3D LSI Technology using W/Cu Hybrid TSVs 査読有り

    M. Murugesan, H. Kino, A. Hashiguchi, C. Miyazaki, H. Shimamoto, H. Kobayashi, T. Fukushima, T. Tanaka, M. Koyanagi

    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 139-142 2011年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2011.6131503  

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    High density 3D LSI technology using W/Cu hybrid through silicon vias (TSVs) has been proposed. Major reliability issues attributed to W/Cu hybrid TSVs in high density 3D LSIs such as (i) thermo-mechanical stress exerted by W TSVs used for signal lines and Cu TSVs used for power/ground lines in active Si, (ii) external gettering (EG) role played by sub-surface defects in thinned Si substrate, and (iii) effect of local stress induced by mu-bumps on device characteristics are discussed. By annealing at the temperature of &gt;= 300 degrees C, both Cu (via size &lt;= 10 mu m) and W (via size &lt;= 1 mu m) square TSVs induce only compressive stress at small TSV spacing which will seriously affect the mobility in active Si area, and thus device characteristics. Large compressive stress not only leads to extrusion and peeling of TSV metal, but also die cracking, and it will adversely impact on the reliability of 3D-LSIs. Then it was proposed to increase the TSV pitch to larger than twice of TSV size to avoid these adverse effects in high density 3D-LSI. Sub-surface defects at dry polished (DP) surface well act as potential EG sites for Cu contamination. Influences of mechanical stress induced by mu-bumps on device characteristics were also evaluated and ultra-small size In-Au mu-bump technology has been developed to minimize the influences of mu-bumps on device characteristics.

  260. Development of 5 µm Diameter Backside Cu TSV Technology for 3D LSI 査読有り

    Yuki Ohara, Yoshitomo Watanabe, Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    Proceedings of the International Conference on Electronics Packaging (ICEP) 237-240 2011年

  261. Self-Assembly Technologies with High-Precision Chip Alignment and Fine-Pitch Microbump Bonding for Advanced Die-to-Wafer 3D Integration 査読有り

    T. Fukushima, Y. Ohara, M. Murugesan, J. -C. Bea, K. -W. Lee, T. Tanaka, M. Koyanagi

    2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 2050-2055 2011年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2011.5898799  

    ISSN:0569-5503

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    We have demonstrated surface-tension-driven chip self-assembly for 3D stacking of a large number of known good dies (KGDs) on silicon substrates in batch processing. In this work, we employed small droplets of ultra-pure water as a liquid to precisely align chips having fine-pitch indium/gold microbumps with a size/pitch of 5/10 or 10/20 mu m. By using the self-assembly technique, these chips were aligned in a face-down configuration and flip-chip bonded onto hydrophilic bonding areas formed on silicon substrates. The hydrophilic areas are surrounded by hydrophobic areas that have above 100 degrees in water contact angle. The wettability contrast between the hydrophilic and hydrophobic areas was found to be a key parameter to obtain high alignment accuracy. All chips having the indium/gold microbump arrays were self-assembled with high alignment accuracy of approximately 1 mu m or superior accuracy, and then, successfully bonded at 200 degrees C with thermal compression. The resulting resistance measured with the indium/gold daisy chain patterns was sufficiently low (&lt; 20 m Omega/bump) and comparable to one obtained by a conventional mechanical alignment technique.

  262. 3D LSI Technology and Reliability Issues 査読有り

    T. Tanaka, J. Bea, M. Murugesan, K. Lee, T. Fukushima, M. Koyanagi

    Proceedings of the 2011 Symposium on VLSI Technology 184-185 2011年

  263. Thinning Process Induced Surface Defects in Ultra-Thin Si Wafer 査読有り

    M. Murugesan, H. Nohira, C. Miyazaki, H. Shimamoto, H. Kobayashi, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 50-51 2011年

  264. Evaluation of Reconfigurable Processor Test Chip for Dependable 3D Stacked Multicore Processor 査読有り

    H. Hashimoto, T. Fukushima, K-W. Lee, T. Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 168-169 2011年

  265. Development of Implantable Si Neural Probe with Stimulus and Recording Electrodes for Deep Brain Stimulation 査読有り

    Yoshiho Yukita, Sanghoon Lee, Soichiro Kanno, Kangwook Lee, Takafumi Fukushima, Mitsumasa Koyanagi, Norihiro Katayama, Hajime Mushiake, Tetsu Tanaka

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 408-409 2011年

  266. Impacts of Microbump-Induced Local Bending Stress in 3D-LSI 査読有り

    H. Kino, M. Murugesan, K.-W. Lee, J.-C. Bea, C. Miyazaki, H. Kobayashi, H. Shimamoto, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 785-786 2011年

  267. Evaluation of Thermo-Mechanical Stress Induced by W-TSVs in 3D-LSI with W/Cu Hybrid TSVs 査読有り

    H. Hashiguchi, M. Murugesan, J.C. Bea, K.W. Lee, T. Fukushima, H. Kobayashi, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 795-796 2011年

  268. Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI 査読有り

    Akihiro Noriki, Kang-Wook Lee, Jicheol Bea, Takafumi Fukushima, Tetsu Fanaka, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 821-822 2011年

    DOI: 10.1109/3DIC.2012.6262957  

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    To realize very high performance computing system, we have proposed a novel opto-electronic 3-D LSI in which both electrical and optical devices are integrated. To realize such opto-electronic 3-D LSI, through Si photonic via (TSPV) is indispensable for vertical light transmission. In addition, vertically transmitted light has to be bended and coupled to a planar optical waveguide on the LSI chips. For this purpose, we have proposed unidirectional optical coupler and it shows very high coupling efficiency of the TSPV and the planar optical waveguide. In this work, we evaluated a fabrication tolerance of the high efficient unidirectional optical coupler by FDTD (Finite-Difference Time-Domain) method. From the simulation results, we found that a grating pitch of the coupler was most critical structural parameter to realize high efficient optical coupling. A standard variation of the grating pitch fluctuation should be less than 20nm to realize 80% coupling efficiency. We also showed that a misalignment tolerance of the unidirectional optical coupler. The misalignment of 1 μm induced 20% optical loss. If the misalignment could be less than 0.1 μm, the optical loss became almost negligible. © 2011 IEEE.

  269. A Block-Parallel SAR ADC for CMOS Image Sensor with 3-D Stacked Structure 査読有り

    K. Kiyoyama, K-W. Lee, T. Fukushima, H. Naganuma, H. Kobayashi, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1055-1056 2011年

  270. Development of Pillar-Shaped Stimulus Electrode Array for High Efficient Stimulation of Fully Implantable Retinal Prosthesis 査読有り

    Yoshitomo Watanabe, Chikashi Kigure, Kangwook Lee, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1097-1098 2011年

  271. Performance of Low-Loss and Low-Cost Optoelectronic Module with Polynorbornene Waveguide for 10-Gbps Data Transmission 査読有り

    Yuka Ito, Shinsuke Terada, Shinya Arai, Makoto Fujiwara, Tetsuya Mori, Koji Choki, Takafumi Fukushima, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1125-1126 2011年

  272. Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application 査読有り

    Yanli Pei, Tatsuro Hiraki, Toshiya Kojima, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    TECHNOLOGY EVOLUTION FOR SILICON NANO-ELECTRONICS 470 140-+ 2011年

    出版者・発行元:TRANS TECH PUBLICATIONS LTD

    DOI: 10.4028/www.scientific.net/KEM.470.140  

    ISSN:1013-9826

    詳細を見る 詳細を閉じる

    In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bottom layer. A large memory window and long retention time were obtained. However, the thermal electron excitation is dominant for the electron discharge process during retention. How to reduce the defects in MND layer is important for further improving of memory characteristics.

  273. Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration 査読有り

    Yuki Ohara, Lee Kangwook, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262950  

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    We developed a novel detachable bonding process by controlling wettability of a bonding surface. A high hydrophobic surface was formed in the bonding area for adhesion blocking. We applied an adhesive material with high thermal resistance at around 350 °C. In this paper, the bonding characteristics of the novel detachable bonding process was estimated by evaluating the shear strength and the dissolution time of adhesive material varying the ratio of hydrophobic area to the hydrophilic area using 5 mm 2 size chip. Based on the evaluation results of the shear strength and the de-bonding time, 10 % of the hydrophilic area is suitable condition for our novel chip-level 3D integration process. © 2011 IEEE.

  274. Temporary bonding strength control for self-assembly-based 3D integration 査読有り

    Takafumi Fukushima, Yuki Ohara, Jicheol Bea, Mariappan Murugesan, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262954  

    詳細を見る 詳細を閉じる

    We have demonstrated bonding strength control for self-assembly-based 3D integration in which many chips are instantly assembled on a wafer all at once by using liquid droplets, and then, temporarily bonded to the wafer. The wafer is named Reconfigured Wafer. The self-assembly-based multichip-to-wafer 3D stacking is called reconfigured-wafer-to-wafer 3D integration. The alignment accuracy is found to be within 1 μm and the temporal bonding strength is well controlled by the quality of oxides as a bonding interface material, liquid types (concentration of additives), total bonding area, and surface roughness of the oxides. The self-assembled and temporarily bonded chips are successfully transferred to another wafer in a face-to-face bonding manner in batch processing. © 2011 IEEE.

  275. Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI 査読有り

    Akihiro Noriki, Kang-Wook Lee, Jicheol Bea, Takafumi Fukushima, Tetsu Fanaka, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262957  

    詳細を見る 詳細を閉じる

    To realize very high performance computing system, we have proposed a novel opto-electronic 3-D LSI in which both electrical and optical devices are integrated. To realize such opto-electronic 3-D LSI, through Si photonic via (TSPV) is indispensable for vertical light transmission. In addition, vertically transmitted light has to be bended and coupled to a planar optical waveguide on the LSI chips. For this purpose, we have proposed unidirectional optical coupler and it shows very high coupling efficiency of the TSPV and the planar optical waveguide. In this work, we evaluated a fabrication tolerance of the high efficient unidirectional optical coupler by FDTD (Finite-Difference Time-Domain) method. From the simulation results, we found that a grating pitch of the coupler was most critical structural parameter to realize high efficient optical coupling. A standard variation of the grating pitch fluctuation should be less than 20nm to realize 80% coupling efficiency. We also showed that a misalignment tolerance of the unidirectional optical coupler. The misalignment of 1 μm induced 20% optical loss. If the misalignment could be less than 0.1 μm, the optical loss became almost negligible. © 2011 IEEE.

  276. A very low area ADC for 3-D stacked CMOS image processing system 査読有り

    K. Kiyoyama, K. W. Lee, T. Fukushima, H. Naganuma, H. Kobayashi, T. Tanaka, M. Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262958  

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    This paper presents a very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system. To realize high-speed image sensor, we have proposed a block-parallel signal processing with 3-D stacked structure. The proposed block-parallel analog signal processing elements contains CMOS image sensor, correlated double sampling (CDS) array, and ADC array. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. To achieve extremely low circuit area and low power dissipation, ADC designed in the prototype chip for fundamental evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. An implemented 9-bit prototype in a 90 nm CMOS technology occupies 100x100 μm 2, achieves an ENOB of 7.28 bit at a conversion rate of 4 MS/s. The power dissipation is 381μW with supply voltage of 1.0V and 4 MS/s conversion rate. © 2011 IEEE.

  277. High-bandwidth data transmission of new transceiver module through optical interconnection 査読有り

    Yuka Ito, Shinsuke Terada, Shinya Arai, Koji Choki, Takafumi Fukushima, Mitsumasa Koyangi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 1-36 2011年

    DOI: 10.1109/3DIC.2012.6263010  

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    This paper presents optical interconnection for module-to-module length for high-performance computing system. A new multi-chip transceiver module consisting of optical components, IC chips, flexible printed circuits (FPCs), and a sheet of optical polynorbornene (PNB) waveguides was fabricated by simple packaging processes. Waveguide sheet with micromirrors and the FPCs mounting of O/E devices were completed independently. After that, the waveguide sheet was aligned to optical devices on FPCs passively. Optical loss for waveguide including propagation and micromirror couplings was 3.30 dB. We successfully demonstrate high-bandwidth 100-Gbps (12.5 Gbps/ch x 8 channels) data transmission with the module, on which two 4-channel vertical-cavity surface emitting laser (VCSEL) arrays, one VCSEL driver (VD), two 4-channel PD arrays, and one transimpedance amplifier/limiting amplifier (TIA/LA) were mounted. © 2011 IEEE.

  278. High density Cu-TSVs and reliability issues 査読有り

    Murugesan Mariappan, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262969  

    詳細を見る 詳細を閉じる

    Reliability issues such as thermo-mechanical stress, extrusion of via metal, and die-cracking caused by high density Cu-TSVs in 3D-LSI Si die/wafer after wafer thinning and bonding have been systematically investigated respectively using micro-Raman spectroscopy, laser microscopy, and optical microscopy techniques. It is inferred that (i) for the TSV pitch value of less than twice the TSV-width, the remnant stress present in the Si at the TSV space region is turned to be only compressive, i.e. in the lateral direction, the compressive stress produced by the adjacent TSVs overlapped to each other for the TSV pitch values of greater than two times the TSV-width, the compressive stress in the Si at the vicinity of TSV is followed by the tensile stress and beyond that it becomes stress free at the TSV space region (ii) Irrespective of the TSV shape and size, the lateral extrusion of Cu occurs at the TSV space region. The lateral extrusion becomes prominent for the larger TSV size values and the higher bonding temperatures. The lateral extrusion is larger for the 20 μm-width TSV annealed at the higher temperature (∼4 μm @ 400 °C) than for the TSV annealed at lower temperature (a maximum of only 1.5 μm @ 200 °C) (iii) Cracking of LSI die/wafer occurs at the periphery of the TSV array for very fine pitch values, and for larger pitch values cracking occurs in between TSVs. © 2011 IEEE.

  279. W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress 査読有り

    Mariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 2011年

    DOI: 10.1109/3DIC.2012.6262970  

    詳細を見る 詳細を閉じる

    High density 3D-LSI with W-TSV for signal line and Cu-TSV for power/GND line, and Cu-TSV containing W stress absorbing layers were investigated for the induced thermo-mechanical stress in 3D-LSI Si die/wafer after wafer thinning and bonding using micro-Raman spectroscopic technique. Stress mapping analysis revealed that W-TSV has induced less thermo-mechanical stress in LSI Si, whereas the Cu-TSV has induced large amount of stress. Further, Cu-TSV with W stress absorbing layer showed much reduced residual thermo-mechanical stress as compared to the pure Cu-TSV, i.e for 6 μm diameter Cu-TSV with W layer showed &lt +100 MPa of tensile stress after heating at 400 °C, whereas the Cu-TSV without W layer revealed &gt -300 MPa of compressive stress after heating at 400 °C. This property can be readily employed to minimize the residual thermo-mechanical stress in the bonded high density 3D-LSI. © 2011 IEEE.

  280. High Reliable and Fine Size of 5-µm Diameter Backside Cu Through-Silicon Via(TSV)for High Reliability and High-End 3-D LSIs 査読有り

    K.-W. Lee, J.-C. Bea, T. Fukushima, Y. Ohara, T. Tanaka, M. Koyanagi

    Technical Digest of IEEE International 3D System Integration Conference (3DIC) 2011年

    DOI: 10.1109/3DIC.2012.6262975  

  281. A Cavity Chip Interconnection Technology for Thick MEMS Chip Integration in MEMS-LSI Multichip Module 査読有り

    Kang-Wook Lee, Soichiro Kanno, Kouji Kiyoyama, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JOURNAL OF MICROELECTROMECHANICAL SYSTEMS 19 (6) 1284-1291 2010年12月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/JMEMS.2010.2082497  

    ISSN:1057-7157

    eISSN:1941-0158

    詳細を見る 詳細を閉じる

    We develop a cavity chip interconnection technology for thick microelectromechanical systems (MEMS) chip integration. The cavity chip comprising Cu through-silicon via and Cu beam-lead wire was fabricated by micromachining processes. The cavity chip could easily connect a thick MEMS chip with a high step height of more than a few hundred micrometers without changing the circuit design of MEMS chip and complicated extra process. Fundamental characteristics are successfully obtained from a pressure-sensing MEMS chip of 360-mu m thickness, where the MEMS chip was connected to a Si substrate by the cavity chip without degrading brittle sensing elements. This interconnection technology would provide a good solution for thick MEMS chip integration with high flexibility.

  282. Effects of Postdeposition Annealing on Cobalt Nanodots Embedded in Silica for Nonvolatile Memory Application 査読有り

    Yanli Pei, Toshiya Kojima, Tatsuro Hiraki, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 49 (6) 066503-1-066503-4 2010年6月

    出版者・発行元:JAPAN SOC APPLIED PHYSICS

    DOI: 10.1143/JJAP.49.066503  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    We studied the effects of postdeposition annealing (PDA) on the films of cobalt nanodots (Co-NDs) dispersed in silica formed by self-assembled nanodot deposition (SAND). High-resolution transmission electron microscopy (HRTEM) analysis showed that the as-grown Co-NDs have a high density of 8 x 10(12)/cm(2) and a small size of similar to 1.5 nm. After PDA at 800 degrees C, a monolayer of Co-NDs is produced by agglomeration. Under this PDA condition, the dot size and density are easily controlled by adjusting the thickness of the as-grown Co-ND film. In contrast, a high-temperature PDA of 900 degrees C induces the diffusion of cobalt into the silicon substrate and leads to the failure of memory effect. When the PDA temperature is between 600 and 800 degrees C, a large counterclockwise hysteresis memory window is obtained. Furthermore, in this region, the charge retention is enhanced by increasing the PDA temperature, which presumably contributes to the release of oxygen from oxidized cobalt. (C) 2010 The Japan Society of Applied Physics

  283. Surface tension-driven chip self-assembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits 査読有り

    T. Fukushima, E. Iwata, T. Konno, J. -C. Bea, K. -W. Lee, T. Tanaka, M. Koyanagi

    APPLIED PHYSICS LETTERS 96 (15) 154105-1-154105-3 2010年4月

    出版者・発行元:AMER INST PHYSICS

    DOI: 10.1063/1.3328098  

    ISSN:0003-6951

    詳細を見る 詳細を閉じる

    We have demonstrated fluidic chip self-assembly on Si wafers for fabricating three-dimensional integrated circuits. In this self-assembly technique, small droplets of hydrofluoric acid were employed to simultaneously align many millimeter-scale chips and directly bond them to the hydrophilic bonding areas formed on the host wafers by oxide-oxide bonding. The liquid surface tension enables many Si chips to be self-assembled with the highest alignment accuracy of 50 nm. In addition, many chips were tightly bonded to the hydrophilic bonding areas without applying a mechanical force after the liquid was evaporated at room temperature.

  284. Three-Dimensional Integration Technology Using Through-Si Via Based on Reconfigured Wafer-to-Wafer Bonding 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

    IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010 2010年

    出版者・発行元:IEEE

    詳細を見る 詳細を閉じる

    Three-dimensional (3-D) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-D integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-D integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

  285. セルフアセンブリを基盤としたウェーハレベル三次元集積化技術 査読有り

    福島誉史, LEE Kang-Wook, 田中徹, 田中徹, 小柳光正

    電子情報通信学会技術研究報告 109 (408(SDM2009 171-181)) 323-326 2010年

    出版者・発行元:None

    ISSN:0913-5685

  286. Self-Assembly Technology for Advanced Die-to-Wafer 3D Integration 査読有り

    Takafumi Fukushima, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

    Technical Digest of the 2nd International IEEE Workshop on Low Temperature Bonding for 3D Integration (LTB-3D) 433-437 2010年

  287. Impact of Remnant Stress/Strain in 3D Stacked Retinal Chip by Wafer Thinning and Bonding 査読有り

    Hisashi Kino, Tatsuro Hiraki, Mariappan Murugesan, Jicheol Bea, Takafumi Fukushima, Mitsumasa Koyanagi, Testu Tanaka

    Proceedings of the 12th International Symposium of Tohoku University Global COE Programme Global Nano-Biomedical Engineering Education and Research Network Centre, Nano^Biomedical Engineering in the East Asian-Pacific Rim Region 123-124 2010年

  288. Electrical and Mechanical Characteristics of Si Double-sided Neural Probe for In-vivo Recording 査読有り

    Sanghoon Lee, Risato Kobayashi, Soichiro Kanno, Kangwook Lee, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka

    Proceedings of the 12th International Symposium of Tohoku University Global COE Programme Global Nano-Biomedical Engineering Education and Research Network Centre, Nano^Biomedical Engineering in the East Asian-Pacific Rim Region 127-128 2010年

  289. Highly Accurate Optical Stimulation of Neuron using Si Neural Probe with Optical Waveguide 査読有り

    Risato Kobayashi, Sanghoon Lee, Soichiro Kanno, Yoshiho Yukita, Kangwook Lee, Takafumi Fukushima, Toru Ishizuka, Hajime Mushiake, Hiromu Yao, Mitsumasa Koyanagi, Tetsu Tanaka

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 181-182 2010年

  290. Development of Versatile Backside Via Technology for 3D System on Chip 査読有り

    Y. Ohara, K.-W. Lee, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 237-238 2010年

  291. Evaluation of Copper Diffusion in Thinned Wafer with Extrinsic Gettering for 3D-LSI by Capacitance-Time (C-t) measurement 査読有り

    J.-C. Bea, K.-W. Lee, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1196-1197 2010年

  292. Through Silicon Photonic Via with Si core for Low loss and High Density Vertical Optical Interconnection in 3D-LSI 査読有り

    Akihiro Noriki, Kang-Wook Lee, Jicheol Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1198-1199 2010年

  293. Self-Assembly with Metal Microbump-to-Microbump Bonding for Advanced Chip-to-Wafer 3D Integration 査読有り

    Eiji Iwata, Yuki Ohara, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1202-1203 2010年

  294. Metal Micro-Bump Induced Stress in 3D-LSIs _a micro-Raman Study 査読有り

    M. Murugesan, Y. Ohara, J.C Bea, K.W. Lee, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 1204-1205 2010年

  295. Self-Assembly Technology for Reconfigured Wafer-to-Wafer 3D Integration 査読有り

    T. Fukushima, E. Iwata, K. -W. Lee, T. Tanaka, M. Koyanagi

    2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) 1050-1055 2010年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2010.5490830  

    ISSN:0569-5503

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    We have introduced a new 3D stacking technology called reconfigured wafer-to-wafer 3D integration using surface tension-powered multichip self-assembly and multichip transfer techniques. Many Si chips were simultaneously self-assembled to a carrier wafer named "reconfigured wafer". High-precision chip alignment with sub-micron-scale accuracy can be realized by optimizing self-assembly conditions. In addition, we developed a new self-assembled multichip bonder to three-dimensionally stack many known good dies (KDGs) on 8-inch wafers at the wafer level. By using the equipment, the many self-assembled Si chips were transferred to another target wafer in batch. [GRAPHICS] .

  296. Formation of Cobalt Nanodots Embedded in Silicon Oxide for Nonvolatile Memory Application 査読有り

    Yanli Pei, Tatsuro Hiraki, Toshiya Kojima, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    Proceedings of the China Semiconductor Technology International Conference (CSTIC) 55-55 2010年

  297. Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding 査読有り

    Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE 3D System Integration Conference 2010, 3DIC 2010 2010年

    DOI: 10.1109/3DIC.2010.5751432  

    詳細を見る 詳細を閉じる

    Micro-Raman spectroscopic technique has been employed to study the induced stress/strain by the metal microbumps in 3D-LSI Si die/wafer after wafer thinning and bonding, and the impact of bump spacing, bump size, bonding temperature and bonding force in the stress distribution in such a microbump bonded LSIs has been investigated. It is inferred that (i) the Si present at the interface (between CuSn and LSI die/wafer) is under compressive stress, and it decreases exponentially in the cross-sectional direction both in the die and the wafer (ii) in the lateral direction, the compressive stress produced by the adjacent microbumps overlapped to each other at the region of bump-spacing (iii) qualitatively, the residual mechanical stress/strain increases with the bonding temperature and the size of the microbump, i.e. it is large for the higher bonding temperature (as high as &gt 300 MPa @300°C) than for the non-bonded microbump (a maximum of only +125 MPa @ 280°C) (iv) the metal microbump exerted a large compressive stress up to the depth of &gt 10 μm in the bonded 3D-LSI die/wafer. © 2010 IEEE.

  298. Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI 査読有り

    Akihiro Noriki, Kang-Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    IEEE 3D System Integration Conference 2010, 3DIC 2010 2010年

    DOI: 10.1109/3DIC.2010.5751435  

    詳細を見る 詳細を閉じる

    To realize very high performance computing system, we have proposed a novel opto-electronic 3-D LSI in which both electrical and optical devices are integrated. For realizing such opto-electronic 3-D LSI, through Si photonic via (TSPV) is indispensable for vertical light transmission. In this work, we fabricated the TSPV comprising Si core and epoxy cladding. We measured near field patterns (NFP) of laser light passed through the TSPV to evaluate its light confinement effect. From the results of NFP measurement, we confirmed that the laser light was successfully confined and propagated in the Si core region of the TSPV. We successfully developed a fabrication process to form both the TSPV and TSV simultaneously. The size of the fabricated TSPV and TSV was 20μmx20μm and 16μmx16μm, respectively. © 2010 IEEE.

  299. エレクトロニクスの多様化を支える新デバイス技術-2020年を見据えて-4.極限集積化を目指すスーパチップ 査読有り

    小柳光正, 福島誉史, LEE Kangwook, 田中徹

    電子情報通信学会誌 93 (11) 918-922 2010年

    ISSN:0913-5693

  300. 3D Hybrid Integration Technology for Opto-Electronic Hetero-Integrated Systems 査読有り

    Kangwook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    PROCESSING, MATERIALS, AND INTEGRATION OF DAMASCENE AND 3D INTERCONNECTS 33 (12) 71-90 2010年

    出版者・発行元:ELECTROCHEMICAL SOC INC

    DOI: 10.1149/1.3501035  

    ISSN:1938-5862

    eISSN:1938-6737

    詳細を見る 詳細を閉じる

    We developed a 3D hybrid integration technology of complementary metal oxide semiconductor (CMOS), micro electro mechanical systems (MEMS) and photonic circuits for opto-electronic hetero-integrated systems. The 3D opto-electronic multi-chip module comprising CMOS, MEMS, and photonic devices was fabricated by using 3D hybrid integration technology. The electrical chips of amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS were mounted on the electrical Si interposer with Cu through silicon vias (TSVs). The photonic chips of vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) were embedded into the optical Si interposer with an optical waveguide. The electrical and the optical interposers were precisely bonded together to form 3D opto-electronic multi-chip module. The photonics and electrical devices are communicated via Cu TSVs. The photonic devices were connected via an optical waveguide. Basic functions of CMOS, MEMS and photonic devices in the 3D opto-electronic multi-chip module were successfully evaluated.

  301. Wafer Thinning, Bonding, and Interconnects Induced Local Strain/Stress in 3D-LSIs with Fine-Pitch High-Density Microbumps and Through-Si Vias 査読有り

    M. Murugesan, H. Kino, H. Nohira, J. C. Bea, A. Horibe, F. Yamada, C. Miyazaki, H. Kobayashi, T. Fukushima, T. Tanaka, M. Koyanagi

    2010 INTERNATIONAL ELECTRON DEVICES MEETING - TECHNICAL DIGEST 30-34 2010年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2010.5703279  

    詳細を見る 詳細を閉じる

    Mechanical strain/stress and crystal defects are produced in extremely thin wafers (thickness similar to 10 mu m) of 3D-LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and curing. Furthermore, the metal of through-Si via (TSV) and microbump not only becomes the cause of contamination, but also induces strain/stress (due to the difference in the co-efficient of thermal expansion (CTE) between Si and metal) in thinned Si substrate. X-ray photoelectron spectroscopy (XPS) results showed that the crystal quality of Si is highly deteriorated in the ultra-poly ground (UPG) surface after wafer thinning and stress relief. Micro-Raman spectroscopy (mu RS) data revealed that a local tensile strain amount to 1.8 GPa was induced by 4x4 mu m(2) square sized Si microbumps in 10 mu m-thick LSI wafers after bonding and curing. We have noticed that this locally induced strain/stress caused more than 10% change in the ON current of p-MOS transistor. CuSn microbumps have also induced strain/stress at Si wafer surface, and it penetrates deeper for larger bump size and wider for smaller bump pitch.

  302. 三次元積層型集積回路のための自己組織化チップ位置合せ技術 査読有り

    岩田永司, 福島誉史, 大原悠希, LEE Kang-Wook, 田中徹, 田中徹, 小柳光正

    電子情報通信学会論文誌 C J93-C (11) 493-502 2010年

    ISSN:1345-2827

  303. Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature 査読有り

    T. Fukushima, E. Iwata, J. Bea, M. Murugesan, K. W. Lee, T. Tanaka, M. Koyanagi

    IEEE 3D System Integration Conference 2010, 3DIC 2010 2010年

    DOI: 10.1109/3DIC.2010.5751436  

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    Chip-to-wafer bonding is a promising technology for 3D integration due to high production yield using known good dies (KGDs). However, conventional chip-to-wafer 3D integration lowers production throughput because pick-and-place chip assembly is employed. To overcome the problem, we proposed a new chip-to-wafer 3D integration using self-assembly by which many KGDs can be simultaneously, rapidly, and precisely aligned and tightly bonded on wafers. The driving force is liquid surface tension. Here, we used an aqueous solution including dilute HF. In this paper, we discuss the dependence of alignment accuracy on several parameters in self-assembly conditions. In addition, we describe mechanism on HF-assisted direct chip bonding to wafers without thermal compression. © 2010 IEEE.

  304. A block-parallel signal processing system for CMOS image sensor with three-dimensional structure 査読有り

    K. Kiyoyama, K. W. Lee, T. Fukushima, H. Naganuma, H. Kobayashi, T. Tanaka, M. Koyanagi

    IEEE 3D System Integration Conference 2010, 3DIC 2010 2010年

    DOI: 10.1109/3DIC.2010.5751479  

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    In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists of 3 stacked layers which are 100 pixels image sensor, CDS circuit, and one ADC. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area, ADC is required. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. ADC designed in the test chip for functional evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. The proposed 9-bit ADC was designed in 90-nm CMOS technology, and achieved power dissipation less than 0.5mW with supply voltage of 1.0V and 4 MS/s conversion rate. The circuit area is 100 x 100 μm2. © 2010 IEEE.

  305. Development of self-assembled 3-D integration technology and study of microbump and TSV induced stress in thinned chip/wafer 査読有り

    T. Tanaka, T. Fukushima, K. -W. Lee, M. Murugesan, M. Koyanagi

    2010 IEEE INTERNATIONAL SOI CONFERENCE 60-63 2010年

    出版者・発行元:IEEE

    DOI: 10.1109/SOI.2010.5641471  

    ISSN:1078-621X

  306. セルフアセンブリ法を用いた新しいヘテロインテグレーション技術 招待有り

    福島誉史, 田中徹, 小柳光正

    応用物理学会分科会 シリコンテクノロジー 「VLSIシンポジウム特集(先端CMOSデバイス・プロセス技術)」 115 17-22 2009年8月3日

  307. Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric 査読有り

    Yanli Pei, Chengkuan Yin, Toshiya Kojima, Masahiko Nishijima, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    APPLIED PHYSICS LETTERS 95 (3) 033118-033120 2009年7月

    出版者・発行元:AMER INST PHYSICS

    DOI: 10.1063/1.3189085  

    ISSN:0003-6951

    詳細を見る 詳細を閉じる

    In this letter, cobalt nanodots (Co-NDs) had been formed via a self-assembled nanodot deposition. High resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of similar to 2 nm and high density of (4-5)x10(12)/cm(2). The metal-oxide-semiconductor device with high density Co-NDs floating gate and high-k HfO2 blocking dielectric exhibits a wide range memory window (0-12 V) due to the charge trapping into and distrapping from Co-NDs. After 10 years retention, a large memory window of similar to 1.3 V with a low charge loss of similar to 47% was extrapolated. The relative longer data retention demonstrates the advantage of Co-NDs for nonvolatile memory application.

  308. Memory characteristics of metal-oxide-semiconductor capacitor with high density cobalt nanodots floating gate and HfO2 blocking dielectric 査読有り

    Yanli Pei, Chengkuan Yin, Toshiya Kojima, Masahiko Nishijima, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    APPLIED PHYSICS LETTERS 95 (3) 033118-1-033118-3 2009年7月

    出版者・発行元:AMER INST PHYSICS

    DOI: 10.1063/1.3189085  

    ISSN:0003-6951

    詳細を見る 詳細を閉じる

    In this letter, cobalt nanodots (Co-NDs) had been formed via a self-assembled nanodot deposition. High resolution transmission electron microscopy and x-ray photoelectron spectroscopy analyses clearly show that the high metallic Co-ND is crystallized with small size of similar to 2 nm and high density of (4-5)x10(12)/cm(2). The metal-oxide-semiconductor device with high density Co-NDs floating gate and high-k HfO2 blocking dielectric exhibits a wide range memory window (0-12 V) due to the charge trapping into and distrapping from Co-NDs. After 10 years retention, a large memory window of similar to 1.3 V with a low charge loss of similar to 47% was extrapolated. The relative longer data retention demonstrates the advantage of Co-NDs for nonvolatile memory application.

  309. MOSFET nonvolatile memory with a high-density tungsten nanodot floating gate formed by self-assembled nanodot deposition 査読有り

    Y. Pei, C. Yin, J. C. Bea, H. Kino, T. Fukushima, T. Tanaka, M. Koyanagi

    SEMICONDUCTOR SCIENCE AND TECHNOLOGY 24 (4) 2009年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.1088/0268-1242/24/4/045022  

    ISSN:0268-1242

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    Metal-oxide-semiconductor field-effect transistor (MOSFET) nonvolatile memories with high-density tungsten nanodots (W-NDs) dispersed in silicon nitride as a floating gate were fabricated and characterized. The W-NDs with a high density of similar to 5 x 10(12) cm(-2) and small sizes of 2-3 nm were formed by self-assembled nanodot deposition (SAND). A large memory window of similar to 1.7 V was observed with bi-directional gate voltage sweeping between -10 and +10 V. Considering that there is no hysteresis memory window for the reference sample without W-NDs, this result indicates the charge trapping in W-NDs or related defects. Finally, the program/erase speed and retention characteristics were investigated and discussed in this paper.

  310. Optical Interposer Technology using Buried Vertical-Cavity Surface-Emitting Laser Chip and Tapered Through-Silicon Via for High-Speed Chip-to-Chip Optical Interconnection 査読有り

    Akihiro Noriki, Makoto Fujiwara, Kang-Wook Lee, Woo-Cheol Jeong, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 48 (4) C113-1-C113-5 2009年4月

    出版者・発行元:JAPAN SOC APPLIED PHYSICS

    DOI: 10.1143/JJAP.48.04C113  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    A novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposer. Vertical-cavity surf ace-emit ring laser diode (VCSEL) chips and photo diode (PD) chips are buried in the optical interposer with polymeric optical waveguides. The VCSEL is 0.25 mm in width, 0.35 mm in length, and 0.15 mm in height. We realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and the subsequent surface-tension-powered self-assembly with a molten solder. In addition, we demonstrate the basic operation of the buried VCSEL chips in the optical interposer through tapered through-silicon vias (TSVs). The tapered TSVs are successfully formed by copper electroplating and are 64 mu m in top width, 34 mu m in bottom width, and 168 mu m in length. (C) 2009 The Japan Society of Applied Physics

  311. Fundamental Study of Complementary Metal Oxide Semiconductor Image Sensor for Three-Dimensional Image Processing System 査読有り

    Kenji Makita, Kouji Kiyoyarna, Takeaki Sugimura, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 48 (4) C077-1-C077-5 2009年4月

    出版者・発行元:JAPAN SOCIETY APPLIED PHYSICS

    DOI: 10.1143/JJAP.48.04C077  

    ISSN:0021-4922

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    In this paper, we describe a fundamental study of a complementary metal oxide semiconductor (CMOS) image sensor for a three-dimensional (3D) image-processing system. We proposed a pixel circuit with correlated double sampling (CDS) and high-speed image capturing for high-speed image processing. The CDS and high-speed image-capture circuit should be realized simultaneously to allow high-speed image processing. The pixel circuit can realize CDS and high-speed image-capture functions simultaneously. The CDS and high-speed image capturing are realized by using a pixel sample hold capacitor and shared coupling capacitor. Appending extra capacitors causes the pixel circuit size to become large in the two-dimensional (2D) CMOS image sensor. We proposed a 3D CMOS image sensor that can reduce the pixel circuit size and the electrical wiring length and increase the fill factor, even with CDS and high-speed image capturing. Therefore, small, high-speed parallel-processing systems can be realized by using our 3D CMOS image sensor. We fabricated the prototype 2D pixel circuit with CDS and high-speed image capturing. The prototype pixel circuit is successfully implemented in the simultaneous function. We believe the proposed pixel circuit is very effective for 3D CMOS image processing. (c) 2009 The Japan Society of Applied Physics

  312. Characteristics of Copper Spiral Inductors Utilizing FePt Nanodot Films 査読有り

    Woo-Cheol Jeong, Kouji Kiyoyama, Kang-Wook Lee, Akihiro Noriki, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 48 (4) C157-1-C157-5 2009年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.1143/JJAP.48.04C157  

    ISSN:0021-4922

    eISSN:1347-4065

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    We propose a novel Cu spiral inductor with an FePt magnetic nanodot (MND) layer of FePt magnetic nanodots dispersed in SiO2 film by self-assembled nanodot desposition (SAND). We expected an increase in inductance by adopting an MND layer. Nanodot sizes ranging from 2.5 to 3.5 nm in diameter can be well controlled. By optimizing thermal annealing conditions, we formed an FePt MND film with an electromagnetic permeability of 7.7 for passive devices used in a standard radio-frequency integrated circuit (RFIC) process. The quality factors of various spiral inductors were simulated and compared with the measured quality factors of the Cu spiral inductors we fabricated. In addition, the high-frequency characteristics of Cu spiral inductors were successfully observed. (C) 2009 The Japan Society of Applied Physics

  313. Development of Si Neural Probe with Microfluidic Channel Fabricated Using Wafer Direct Bonding 査読有り

    Soichiro Kanno, Risato Kobayashi, Lee Sanghoon, Bea Jicheol, Takafumi Fukushima, Kazuhiro Sakamoto, Norihiro Katayama, Hajime Mushiake, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 48 (4) C189-1-C189-4 2009年4月

    出版者・発行元:JAPAN SOCIETY APPLIED PHYSICS

    DOI: 10.1143/JJAP.48.04C189  

    ISSN:0021-4922

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    This paper reports the development of a novel Si neural probe with a microfluidic channel to deliver drugs into neural tissue. We fabricated this Si neural probe using wafer direct bonding. To confirm the fluidic capability of the fabricated Si probe, we demonstrated the ejection of liquid from the microfluidic channel using a syringe pump. We confirmed that the Si probe had sufficient bonding strength to eject liquid. In addition, we investigated the pressure drops in the microfluidic channel. From the results, we observed a linear relationship between the flow rate and the pressure drop. Since this result agreed well with the calculated values, we confirmed that the microfluiclic channel was successfully formed by wafer direct bonding. (C) 2009 The Japan Society of Applied Physics

  314. Development of Si Double-Sided Microelectrode for Platform of Brain Signal Processing System 査読有り

    Risato Kobayashi, Soichiro Kanno, Lee Sanghoon, Bea Jicheol, Takafumi Fukushima, Kazuhiro Sakamoto, Norihiro Katayama, Hajime Mushiake, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 48 (4) C194-1-C194-5 2009年4月

    出版者・発行元:JAPAN SOCIETY APPLIED PHYSICS

    DOI: 10.1143/JJAP.48.04C194  

    ISSN:0021-4922

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    We have proposed a new implantable neural recording system, which we call the brain signal processing system (BSPS). In this system, LSI chips such as amplifiers, analog-to-digital converters, and multiplexers are integrated on the Si microelectrocle array. To analyze the brain functions or to develop medical treatments for brain disorders, a high-density recording of action potentials is strongly required. To realize high-density recording of action potentials, we propose a novel Si double-sided microelectrode that has recording sites on both front and back sides. The back-side recording sites are connected to a recording apparatus by wire bonding through Si via holes. We fabricated the carefully designed Si double-sided microelectrocle and evaluated the electrical characteristics of the Si microelectrocle. The front- and back-side recording sites had impedance values of 2.5 and 2.7 M Omega at 1 kHz, respectively, which indicated that both recording sites have equivalent characteristics. An in vitro experiment of neuronal action potential recording using the fabricated Si double-sided microelectrocle was performed. The CA1 areas of 400-mu m-thick hippocampal slices obtained from the brains of guinea pigs were employed, and we successfully recorded neuronal action potentials from the recording sites of both sides. (C) 2009 The Japan Society of Applied Physics

  315. Formation of high density tungsten nanodots embedded in silicon nitride for nonvolatile memory application 査読有り

    Yanli Pei, Chengkuan Yin, Masahiko Nishijima, Toshiya Kojima, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    APPLIED PHYSICS LETTERS 94 (6) 063108-063110 2009年2月

    出版者・発行元:AMER INST PHYSICS

    DOI: 10.1063/1.3081042  

    ISSN:0003-6951

    詳細を見る 詳細を閉じる

    In this letter, the formation of high density tungsten nanodots (W-NDs) embedded in silicon nitride via a self-assembled nanodot deposition is demonstrated. In this method, tungsten and silicon nitride are cosputtered in high vacuum rf sputtering equipment. The W-NDs with small diameters (1-1.5 nm) and high density (similar to 1.3x10(13)/cm(2)) were achieved easily by controlling W composition; this is the ratio of total area of W chips to that of silicon nitride target. The metal-oxide-semiconductor memory device was fabricated with high density W-NDs floating gate and high-k HfO(2) blocking dielectric. A wide range memory window (0-29 V) was obtained after bidirectional gate voltages sweeping with range of +/- 1-+/- 23 V. It is feasible to design the memory window with propriety power consumption for nonvolatile memory application.

  316. 訂正:三次元積層型チップのためのSi貫通ビア(TSV)形成技術 [エレクトロニクス実装学会誌 12(2): 104-109 (2009)]

    福島 誉史, 田中 徹, 小柳 光正

    エレクトロニクス実装学会誌 12 (3) 262-262 2009年

    出版者・発行元:The Japan Institute of Electronics Packaging

    DOI: 10.5104/jiep.12.262  

    ISSN:1343-9677

    詳細を見る 詳細を閉じる

    Table 1. Trends in research and development of TSVs<br>-  2006 MRS [15] 2006 IEEE EDL [16] → 2006 MRS [15]<br>-  2006 IEEE EDL [16] 2006 SST [16] → 2006 IEEE EDL [16]<br>-  2007 SST [17] 2007 IEEE ED [17] → 2007 SST [17]<br>-  2008 IEEE ED [18] 2008 → 2008 IEEE ED [18]

  317. Three-Dimensional Integration Technology Based on Reconfigured Wafer-to-Wafer and Multichip-to-Wafer Stacking Using Self-Assembly Method 査読有り

    Takafumi Fukushima, Eiji Iwata, Yuki Ohara, Akihiro Noriki, Kiyoshi Inamura, Kang-Wook Lee, Jicheol Bea, Tetsu Tanaka, Mitsumasa Koyanagi

    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING 323-326 2009年

    出版者・発行元:IEEE

    ISSN:2380-9248

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    We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by self-assembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously transferred to an LSI wafer that is fully faced with the reconfigured wafer and has the same microbump array patterns to the self-assembled chips. On the other hand, in multichip-to-wafer 3D integration, Si chips having In/Au microbumps with sizes of 5 mu m and 10 mu m were directly self-assembled on another LSI wafer having the same In/Au microbumps in a face-to-face manner. After the self-assembly, these chips can be bonded at 200 C without applying mechanical pressure. In both of the self-assembly-based 3D integration, the chips were precisely aligned and bonded to the LSI wafers through the microbump-to-microbump interconnection. We obtained good electrical characteristics using the microbump daisy chains formed between the self-assembled chips and the wafers.

  318. Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding 査読有り

    M. Murugesan, J. C. Bea, H. Kino, Y. Ohara, T. Kojima, A. Noriki, K. W. Lee, K. Kiyoyama, T. Fukushima, H. Nohira, T. Hattori, E. Ikenaga, T. Tanaka, M. Koyanag

    Technical Digest - International Electron Devices Meeting, IEDM 14.5.4 2009年

    DOI: 10.1109/IEDM.2009.5424348  

    ISSN:0163-1918

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    Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (μRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor. © 2009 IEEE.

  319. 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding 査読有り

    Takafumi Fukushima, Eiji Iwata, Yuki Ohara, Akihiro Noriki, Kiyoshi Inamura, Kang-Wook Lee, Jicheol Bea, Tetsu Tanaka, Mitsumasa Koyanagi

    Technical Digest - International Electron Devices Meeting, IEDM 14.2.4 2009年

    DOI: 10.1109/IEDM.2009.5424351  

    ISSN:0163-1918

    詳細を見る 詳細を閉じる

    We demonstrate two types of three-dimensional (3D) integration using chip self-assembly techniques with liquid surface tension. In reconfigured wafer-to-wafer 3D integration, many different sizes of chips having In/Au microbumps with/without TSV (through-silicon via) were temporarily placed by selfassembly on a reconfigured wafer in a back-to-face manner. The many chips can be then simultaneously transferred to an LSI wafer that is fully faced with the reconfigured wafer and has the same microbump array patterns to the self-assembled chips. On the other hand, in multichip-to-wafer 3D integration, Si chips having In/Au microbumps with sizes of 5 μm and 10 μm were directly self-assembled on another LSI wafer having the same In/Au microbumps in a face-to-face manner. After the self-assembly, these chips can be bonded at 200 °C without applying mechanical pressure. In both of the self-assemblybased 3D integration, the chips were precisely aligned and bonded to the LSI wafers through the microbumpto-microbump interconnection. We obtained good electrical characteristics using the microbump daisy chains formed between the self-assembled chips and the wafers. © 2009 IEEE.

  320. Three-Dimensional Integration Technology and Integrated Systems 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

    PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 409-415 2009年

    出版者・発行元:IEEE

    ISSN:2153-6961

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    A three-dimensional (3-D) integration technology based on the wafer-to-wafer bonding using through silicon vias (TSV's) has been developed for the fabrication of new 3-D LSIs. A 3-D image sensor chip, 3-D shared memory chip, 3-D artificial retina chip and 3-D microprocessor test chip have been fabricated by using this technology. In addition, we have proposed a new reconfigurable parallel image processing system. To achieve this system, we have proposed a new 3-D integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration.

  321. Fabrication of Multichannel Neural Microelectrodes with Microfluidic Channels Based on Wafer Bonding Technology 査読有り

    R. Kobayashi, S. Kann, T. Fukushima, T. Tanaka, M. Koyanagi

    13TH INTERNATIONAL CONFERENCE ON BIOMEDICAL ENGINEERING, VOLS 1-3 23 (1-3) 2258-+ 2009年

    出版者・発行元:SPRINGER

    ISSN:1680-0737

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    We have proposed the intelligent Si neural probe which can realize high density and multifunctional recording of neuronal behaviors. In this device, LSI chips such as amplifiers, A/D converters, and multiplexers are integrated on the Si neural probe. In this paper, we report the development of a novel multichannel Si neural microelectrode with microfluidic channels which is the key part of the intelligent Si neural probe. The microelectrode has microfluidic channels fabricated using a wafer bonding technology to deliver drugs into the brain when neuronal action potentials are recorded. And also, our microelectrode has recording sites on both front- and backside of Si to realize high density recording. We fabricated the carefully-designed multichannel Si neural microelectrode, and we evaluated characteristics of both recording sites and microfluidic channels. From the liquid ejection test, we confirmed that there was no void at bonding faces. We observed the liner relationship between the flow rate and the pressure drop, and the relationship was identical to that from the calculation, which indicated that the microfluidic channel was successfully formed. Moreover, both front- and back-side recording sites had impedance values of 2.5 M Omega and 2.7 M Omega at 1 kHz, respectively, which indicated that both recording sites had equivalent characteristics. The neuronal action potentials from CA1 area in a hippocampal slice were successfully recorded by using the fabricated microelectrode.

  322. Development of A Silicon Neural Probe for An Intelligent Silicon Neural Probe System

    Risato Kobayashi, Lee Sanghoon, Soichiro Kanno, Bea Jicheol, Takafumi Fukushima, Kazuhiro Sakamoto, Norihiro Katayama, Hajime Mushiake, Tetsu Tanaka, Mitsumasa Koyanagi

    Nano-Biomedical Engineering 2009 297-308 2009年

  323. Electrical characterization of MOS memory devices with self-assembled tungsten nano-dots dispersed in silicon nitride 査読有り

    Y. Pei, C. Yin, M. Nishijima, T. Kojima, H. Nohira, T. Fukushima, T. Tanaka, M. Koyanagi

    ECS Transactions 18 (1) 33-37 2009年

    DOI: 10.1149/1.3096423  

    ISSN:1938-5862 1938-6737

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    Crystallized W-NDs dispersed in silicon nitride were prepared by self-assembled nanodot deposition (SAND) with extremely high density (1.3×1013/cm2) and small size (1-1.5nm), successfully. XPS results show that the high metallic states of tungsten are remained after 800°C anneal due to the surround silicon nitride. MOS memory capacitor with W-NDs floating gate and HfO2 blocking dielectric was fabricated. A hysteresis memory window of ∼ 1.0V is observed under low sweeping gate voltage of ±5V. A maximum memory window as large as 29V was obtained with sweeping gate voltage of ±23V, suggesting that it is a good candidate for multi-bit nonvolatile memory application. ©The Electrochemical Society.

  324. Electrical Characterization of MOS Memory Devices with Self-assembled Tungsten Nano-dots Dispersed in Silicon Nitride 査読有り

    Y. Pei, C. Yin, M. Nishijima, T. Kojima, H. Nohira, T. Fukushima, T. Tanaka, M. Koyanagi

    Proceedings of the International Semiconductor Technology Conference/China Semiconductor Technology International Conference (ISTC/CSTIC) 85-89 2009年

  325. Super Hetero-Integration Technology for LSI /MEMS Integration 査読有り

    M. Koyanagi, K.-W. Lee, T. Fukushima, T. Tanaka

    Proceedings of the International Conference on Electronics Packaging (ICEP) 589-595 2009年

  326. Development of Double-sided Si Neural Probe with Microfluidic Channels Using Wafer Direct Bonding Technique 査読有り

    R. Kobayashi, S. Kanno, S. Lee, T. Fukushima, K. Sakamoto, Y. Matsuzaka, N. Katayama, H. Mushiake, M. Koyanagi, T. Tanaka

    2009 4TH INTERNATIONAL IEEE/EMBS CONFERENCE ON NEURAL ENGINEERING 96-+ 2009年

    出版者・発行元:IEEE

    DOI: 10.1109/NER.2009.5109243  

    ISSN:1948-3546

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    We have proposed the intelligent Si neural probe system which can realize high density and multifunctional recording of neuronal behaviors. In this device, LSI chips such as amplifiers, A/D converters, and multiplexers are integrated on the intelligent Si neural probe. In this paper, we report the development of a novel Si neural probe with microfluidic channels which is the key part of the intelligent Si neural probe system. The Si neural probe has microfluidic channels fabricated using a wafer bonding technique to deliver drugs into the brain when neuronal action potentials are recorded. Furthermore, our Si neural probe has recording sites on both front- and back-side of Si to realize high density recording. We fabricated the carefully-designed Si neural probe, and evaluated characteristics of microfluidic channels. From the liquid ejection test, we confirmed that there was no void at bonding interfaces. We observed the liner relationship between the flow rate and the pressure drop, and the relationship was identical to that from the calculation, which indicated that the microfluidic channel was successfully formed. In addition, we fabricated the Si neural probe for in vivo neural recording. Both front- and back-side recording sites of the fabricated Si neural probe had impedance values of 1.5 M Omega and 1.2 M Omega at 1 kHz, respectively, which indicated that both recording sites had equivalent characteristics. The neuronal action potentials in motor area of Japanese macaque's brain were successfully recorded by using the fabricated Si neural probe.

  327. A Simple Device Allowing Silicon Microelectrode Insertion for Chronic Neural Recording in Primates 査読有り

    Kazuhiro Sakamoto, Yoshia Matsuzaka, Tamotsu Suenaga, Hiroshi Watanabe, Risato Kobayashi, Takafumi Fukushima, Norihiro Katayama, Tetsu Tanaka, Mitsumasa Koyanagi, Hajime Mushiake

    2009 4TH INTERNATIONAL IEEE/EMBS CONFERENCE ON NEURAL ENGINEERING 104-+ 2009年

    出版者・発行元:IEEE

    DOI: 10.1109/NER.2009.5109245  

    ISSN:1948-3546

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    Micro-machined silicon microelectrodes are useful for obtaining high-density, high-spatial resolution sampling of neuronal activity within the brain, and hold promise for revealing the spatiotemporal dynamics of local circuits. However, the fragile nature of silicon electrodes precludes their application in chronic recordings for a long period of time in which electrodes are repeatedly passed through the hardened dura matter. Here, we describe a newly developed holder designed to make a micro-perforation through the dura matter in which a silicon electrode can easily be inserted.

  328. Cu Lateral Interconnects Formed Between 100-mu m-Thick Self-Assembled Chips on Flexible Substrates 査読有り

    M. Murugesan, J. -C. Bea, T. Fukushima, T. Konno, K. Kiyoyama, W. -C. Jeong, H. Kino, A. Noriki, K. -W. Lee, T. Tanaka, M. Koyanagi

    2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4 1496-1501 2009年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2009.5074210  

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    A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were fabricated via conventional electroplating technique. As formed single as well as daisy chain lateral interconnects (both are crossing over the thick test chips that are face-up bonded onto the flexible substrates by self-assembly) were characterized for their electrical characteristics. We have obtained a low resistance values for the Cu lateral interconnects which are close to the calculated values. Further, a module contains RF test chips that are interconnected by this unique Cu lateral interconnections has been tested for the operation.

  329. Development of EEB (Electroplated Evaporation Bumping) Technology for Fine Pitch and Low Resistance Cu/Sn Micro-Bumps 査読有り

    Y. Ohara, A. Noriki, E. Iwata, T. Hiraki, K.-W. Lee, M. Murugesan, J.-C. Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 86-87 2009年

  330. High-Aspect-Ratio Fine Cu Sidewall Interconnection over Chip Edge with Tapered Polymer for MEMS-LSI Multi-Chip Module 査読有り

    A. Noriki, Y. Kaiho, E. Iwata, Y. Ohara, M. Murugesan, K.-W. Lee, J.-C. Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 88-89 2009年

  331. Evaluation of Thin LSI Wafers by Capacitance-Time (C-t) Measurement for the Process Characterization of Three-Dimensional (3D) Integration 査読有り

    J.-C. Bea, M. Murugesan, Y. Ohara, A. Noriki, H. Kino, K.-W. Lee, T. Fukushima, T. Tanaka, M. Koyanagi

    Extended Abstracts of International Conference on Solid State Devices and Materials (SSDM) 370-371 2009年

  332. In vivo Neural Signal Recording using Double-sided Si Neural Probe 査読有り

    S. Lee, R. Kobayashi, S. Kanno, K. Lee, T. Fukushima, K. Sakamoto, Y. Matsuzaka, N. Katayama, H. Mushiake, M. Koyanagi, T. Tanaka

    Extended Abstract of International Conference on Solid State Devices and Materials (SSDM) 691-692 2009年

  333. Heterogeneous Integration Technology for MEMS-LSI Multi-Chip Module 査読有り

    K-W Lee, S. Kanno, Y. Ohara, K. Kiyoyama, J-C Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION 6-+ 2009年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    We developed novel interconnection technology for heterogeneous integration of MEMS and LSI mufti-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead wires was developed for interconnecting MEMS chips with high step height of more than 100um. Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360 mu m thickness, which was connected to the substrate by the cavity chip. MEMS and LSI chips were vertically integrated by using the cavity chip without changes of chip design and extra processes. This interconnection technology can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module.

  334. A Parallel ADC for High-Speed CMOS Image Processing System with 3D Structure 査読有り

    K. Kiyoyama, Y. Ohara, K-W Lee, Y. Yang, T. Fukushima, T. Tanaka, M. Koyanagi

    2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION 101-+ 2009年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    In this paper, we describe the fundamental study of a parallel signal processing circuit, which Includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS). To realize high speed image capturing sensor, we have proposed a block-parallel signal processing with three-dimensional (3D) structure. Using 3D structure, the different function layers are stacked vertically and interconnected electrically by through-Si vias (TSVs), which can improve sensor performance and signal band width. On the other hand, the fixed pattern noise (FPN), caused by the circuit device variation, becomes a critical challenge. Experiments on the fabricated pixel circuit have been implemented in a single-layer (two-dimensional) 0.18-mu m CMOS image sensor technology. With the analog CDS, the FPN of pixel circuit is reduced by 8.6%. To eliminate the FPN of parallel ADC, a digital CDS technique is implemented. The proposed ADC with digital CDS is designed In a two-dimensional 0.18-mu m CMOS technology. The ADC design, Including an 8-bit memory, a 6-bit memory, a subtraction circuit and a comparator, occupies 100 x 100 mu m(2) area and 0.9mW with supply voltage 1.8 V and 1 MS/s conversion rate. The functional simulation and measurement results confirm that our techniques can effectively reduce fixed pattern noise.

  335. Micro-Raman Spectroscopy Analysis and Capacitance-Time (C-t) Measurement of Thinned Silicon Substrates for 3D Integration 査読有り

    J. -C. Bea, M. Murugesan, Y. Ohara, A. Noriki, H. Kino, K. -W Lee, T. Fukushima, T. Tanaka, M. Koyanagi

    2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION 189-193 2009年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    Mechanical stress, crystal defects, and metal contamination in thinned silicon substrates with and without intrinsic gettering (IG) zone have been investigated for three-dimensional (3D) integration. The remnant stress existing after wafer thinning was evaluated using angle-(5 degrees) polished silicon wafers by micro-Raman spectroscopy (mu RS). The metal contamination in the thinned silicon substrates has been evaluated by a capacitance - time (C-t) measurement method using MOS capacitors in which the thinned silicon substrates were diffused with metallic impurities such as Cu and Au used for through-silicon via (TSV) and metal micro bump in 3D LSI.

  336. 10 µm Fine Pitch Cu/Sn Micro-Bumps for 3-D Super-Chip Stack 査読有り

    Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang-Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    Technical Digest of the IEEE International 3D System Integration Conference 2009 (3DIC) 389-+ 2009年

    出版者・発行元:None

    ISSN:2164-0157

  337. Development of a New Self-Assembled Die Bonder to Three-Dimensionally Stack Known Good Dies in Batch 査読有り

    Takafumi Fukushima, Eiji Iwata, Tetsu Tanaka, Mitsumasa Koyanagi

    2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION 434-437 2009年

    出版者・発行元:IEEE

    ISSN:2164-0157

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    We developed a new self-assembled die bander to produce three-dimensionally integrated circuit (3D IC) using a multichip-to-wafer bonding method in batch. In the self-assembled multichip bander, large number of known good dies (KGDs) can be simultaneously transferred to an LSI wafer on which hydrophilic banding areas with liquid droplets are prepared. The marry KGD can be aligned to the banding areas by the liquid surface tension. The average alignment accuracy was found to be approximately 400 ran and the total alignment time was less dum 0.1 sec. After liquid evaporation, the many KGDs can be handed to the banding areas in die new self-assembled die bonder.

  338. Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking 査読有り

    Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    MATERIALS AND TECHNOLOGIES FOR 3-D INTEGRATION 1112 121-130 2009年

    出版者・発行元:MATERIALS RESEARCH SOCIETY

    ISSN:0272-9172

    詳細を見る 詳細を閉じる

    We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 mu m on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 see by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.

  339. Ultra Low Power Vertical MOS Devices for Fully Implantable Rtinal Prosthesis 査読有り

    H. Kino, T. Hiraki, J-C. Bea, T. Fukushima, M. Koyanagi, T. Tanaka

    3rd East Asian Pacific Student Workshop on Nano-Biomedical Engineering 112-113 2009年

  340. Cu filling characteristics in through-Si via holes by electroless plating with addition of inhibitors 査読有り

    F. Inoue, M. Koyanagi, T. Fukushima, K. Yamamoto, S. Tanaka, Z. Wang, S. Shingubara

    ECS Transactions 16 (22) 27-32 2009年

    DOI: 10.1149/1.3115647  

    ISSN:1938-5862 1938-6737

    詳細を見る 詳細を閉じる

    In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the most promising methods. However, with an increase of the aspect ratio of TSV, a formation of conductive seed layer prior to Cu electroplating is becoming more and more difficult. We propose an alternative approach using the electroless plating of Cu, which utilize displacement plating without catalyst. This method is effective for fabricating a low resistance TSV when combined with a barrier layer which is composed of tungsten (W). We found that an addition of Cl ions drastically suppressed the pinch-off at the entrance of the TSV, and it enabled conformai Cu deposition for high aspect ratio TSVs. ©The Electrochemical Society.

  341. Impact of Remnant Stress/Strain and Metal Contamination in 3D-LSIs with Through-Si Vias Fabricated by Wafer Thinning and Bonding 査読有り

    M. Murugesan, J. C. Bea, H. Kino, Y. Ohara, T. Kojima, A. Noriki, K. W. Lee, K. Kiyoyama, T. Fukushima, H. Nohira, T. Hattori, E. Ikenaga, T. Tanaka, M. Koyanagi

    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING 335-+ 2009年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2009.5424348  

    ISSN:2380-9248

    詳細を見る 詳細を閉じる

    Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication, However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated, The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (mu RS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 degrees C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

  342. 3D Heterogeneous Opto-Electronic Integration Technology for System-on-Silicon (SOS) 査読有り

    K-W Lee, A. Noriki, K. Kiyoyama, S. Kanno, R. Kobayashi, W-C Jeong, J-C Bea, T. Fukushima, T. Tanaka, M. Koyanagi

    2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING 495-498 2009年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2009.5424305  

    詳細を見る 詳細を閉じる

    We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

  343. 3D System Integration Technology and 3D Systems 査読有り

    Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    Conference Proceedings Advanced Metallization Conference 2008 (AMC 2008) 479-485 2009年1月

  344. High-Density Through Silicon Vias for 3-D LSIs 招待有り 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

    PROCEEDINGS OF THE IEEE 97 (1) 49-59 2009年1月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/JPROC.2008.2007463  

    ISSN:0018-9219

    eISSN:1558-2256

    詳細を見る 詳細を閉じる

    High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. in the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.

  345. Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking 招待有り 査読有り

    Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    MATERIALS AND TECHNOLOGIES FOR 3-D INTEGRATION 1112 121-130 2009年

    出版者・発行元:MATERIALS RESEARCH SOCIETY

    ISSN:0272-9172

    詳細を見る 詳細を閉じる

    We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 mu m on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 see by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.

  346. 三次元実装材料 三次元積層型チップのためのSi貫通ビア(TSV)形成技術 招待有り 査読有り

    福島誉史, 田中徹, 田中徹, 小柳光正

    エレクトロニクス実装学会誌 12 (2) 104-109 2009年

    出版者・発行元:None

    DOI: 10.5104/jiep.12.104  

    ISSN:1343-9677

  347. Cu filling characteristics in through-Si via holes by electroless plating with addition of inhibitors 査読有り

    F. Inoue, M. Koyanagi, T. Fukushima, K. Yamamoto, S. Tanaka, Z. Wang, S. Shingubara

    ECS Transactions 16 (22) 27-32 2009年

    DOI: 10.1149/1.3115647  

    ISSN:1938-5862 1938-6737

    詳細を見る 詳細を閉じる

    In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the most promising methods. However, with an increase of the aspect ratio of TSV, a formation of conductive seed layer prior to Cu electroplating is becoming more and more difficult. We propose an alternative approach using the electroless plating of Cu, which utilize displacement plating without catalyst. This method is effective for fabricating a low resistance TSV when combined with a barrier layer which is composed of tungsten (W). We found that an addition of Cl ions drastically suppressed the pinch-off at the entrance of the TSV, and it enabled conformai Cu deposition for high aspect ratio TSVs. ©The Electrochemical Society.

  348. Perfect Conformal Deposition of Electroless Cu for High Aspect Ratio Through-Si Vias 査読有り

    F. Inoue, Y. Harada, M. Koyanagi, T. Fukushima, K. Yamamoto, S. Tanaka, Z. Wang, S. Shingubara

    ELECTROCHEMICAL AND SOLID STATE LETTERS 12 (10) H381-H384 2009年

    出版者・発行元:ELECTROCHEMICAL SOC INC

    DOI: 10.1149/1.3193535  

    ISSN:1099-0062

    詳細を見る 詳細を閉じる

    In three-dimensional integration technology, through-silicon vias (TSVs) with a high aspect ratio in excess of 10 are required, due to a strong demand for a higher packing density. We achieved perfect conformal electroless plating of Cu by the addition of Cl(-) and bis(3-sulfopropyl) disulfide to a standard plating bath. With this technology, the Cu thickness of the TSV sidewalls remained constant with depth, even for the TSV with an aspect ratio of 20. Perfect conformal plating is a promising technology that could lower the resistance of high aspect ratio TSVs. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3193535] All rights reserved.

  349. Investigation of the effect of in situ annealing of FePt nanodots under high vacuum on the chemical states of Fe and Pt by x-ray photoelectron spectroscopy 査読有り

    M. Murugesan, J. C. Bea, C. -K. Yin, H. Nohira, E. Ikenaga, T. Hattori, M. Nishijima, T. Fukushima, T. Tanaka, M. Miyao, M. Koyanagi

    JOURNAL OF APPLIED PHYSICS 104 (7) 074316-1-074316-5 2008年10月

    出版者・発行元:AMER INST PHYSICS

    DOI: 10.1063/1.2973665  

    ISSN:0021-8979

    詳細を見る 詳細を閉じる

    The chemical states of Fe and Pt in in situ annealed L1(0) structured FePt nanodots formed by self-assembled nanodot deposition method have been systematically investigated by angle resolved x-ray photoelectron spectroscopy. From the Fe(3p) and the Pt(4f) core level x-ray photoelectron (XP) spectra, it is evident that both the Fe and Pt of the nanodots were oxidized in the as-grown state. After the in situ annealing under high vacuum, a peak corresponding to metallic Fe begins to appear, and subsequently the metallic peak fraction increased with the increase in the annealing temperature. In line with this, the peak fraction of the respective oxides is drastically decreased. Irrespective of the annealing temperatures, it is inferred from the intensity of the XP spectrum that the Fe atom of the FePt nanodots is highly prone to oxidation than the Pt atom. Nevertheless, the valence band spectra of the as-grown FePt nanodot film clearly depict the presence of metallic Fe-Pt alloy. We would like to explain the results of the core level and valence band XP spectra as follows: only the peripheral Fe and Pt atoms of the as-formed FePt nanodots are bonded to the oxygen of the cosputtered SiO(2) matrix, whereas the metallic core of the as-formed FePt nanodots is always preserved. The very good vacuum ambient during postannealing highly promotes the dissociation of oxygen from the metal oxides via reduction reaction. This results into an increase in the fraction of metallic Fe and Pt at the periphery of FePt nanodots and the formation of high quality SiO(2) matrix after annealing. Similar results were also observed for the monatomic W as well as Pt nanodots embedded in SiO(2) matrix. Hence, this simple, rather effective method of in situ annealing of metal dots dispersed in an insulating matrix can be readily employed in the fabrication of high-density nanodot memory devices. (C) 2008 American Institute of Physics. [DOI: 10.1063/1.2973665]

  350. Memory characteristics of self-assembled tungsten nanodots dispersed in silicon nitride 査読有り

    Yanli Pei, Masahiko Nishijima, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    APPLIED PHYSICS LETTERS 93 (11) 113115-113117 2008年9月

    出版者・発行元:AMER INST PHYSICS

    DOI: 10.1063/1.2986409  

    ISSN:0003-6951

    eISSN:1077-3118

    詳細を見る 詳細を閉じる

    In this letter, tungsten nanodots (W-NDs) in silicon nitride formed by a self-assembled nanodot deposition method have been investigated as a floating gate of nonvolatile memory (NVM). Observations from transmission electron microscopy and x-ray diffraction pattern clearly confirm the formation of crystallized W-NDs with a diameter of similar to 5 nm. The metal-oxide-semiconductor device with W-NDs in silicon nitride exhibits a larger memory window (similar to 4.1 V at +/- 12 V sweep), indicating charge trapping and distrapping between the W-ND and a silicon substrate. The program/erase behaviors and data retention characteristics were evaluated. After 10 years retention, a large memory window of similar to 3.4 V with a low charge loss of similar to 15% was extrapolated. These results demonstrate advantages of W-NDs in silicon nitride for the NVM application. (c) 2008 American Institute of Physics.

  351. Chip Self-Assembly Technique for 3D LSI Fabrication

    T. Fukushima, T. Konno, T. Tanaka, M. Koyanagi

    Technical Digest of the International 3D System Integration Conference (3D-SIC) 2008 207-216 2008年5月12日

  352. Low-loss optical interposer with recessed vertical-cavity surface-emitting laser diode and photodiode chips into Si substrate 査読有り

    Makoto Fujiwara, Shinsuke Terada, Yoji Shirato, Hiroshi Owari, Kei Watanabe, Mutsuhiro Matsuyama, Keizo Takahama, Tetsuya Mori, Kenji Miyao, Koji Choki, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 47 (4) 2936-2940 2008年4月

    出版者・発行元:IOP PUBLISHING LTD

    DOI: 10.1143/JJAP.47.29361  

    ISSN:0021-4922

    eISSN:1347-4065

    詳細を見る 詳細を閉じる

    A new interposer with an optical interconnection called optical interposer has been proposed for a high-performance parallel processor system. The optical interposer is composed of polynorbornene (PNB) optical waveguides with 45 degrees micromirrors and a Si substrate having chip-sized through-Si holes of 150 pm depth. The polymeric waveguides are formed on the Si substrate before forming the through-Si holes by deep reactive ion etching (DRIE). Vertical-cavity surface-emitting laser diode (VCSEL) and photodiode (PD) chips are placed onto the photolithographically defined hole patterns that are 15 mu m larger than the size of the chips. In addition, the chips can be precisely aligned and recessed into the holes by passive alignment of selfassembly driven by the surface tension of a lead-free solder. We can fabricate the low-loss optical interposer with an insertion loss of below 0.2dB measured at the waveguide length of 5cm and a coupling loss of 0.5dB measured with a 45 degrees micromirror.

  353. Tungsten through-silicon via technology for three-dimensional LSIs 査読有り

    Hirokazu Kikuchi, Yusuke Yamada, Atif Mossad Ali, Jun Liang, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 47 (4) 2801-2806 2008年4月

    出版者・発行元:JAPAN SOCIETY APPLIED PHYSICS

    DOI: 10.1143/JJAP.47.2801  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    Tungsten through-silicon via (W-TSV) technology is investigated for the fabrication of three-dimensional (3D) LSI chips having low-resistive TSVs with a width less than 3 mu m. In our 3D integration technology, completed two-dimensional (2D) LSI chips including metal-oxide-semiconductor field-effect transistors (MOSFETs) and metal wirings are vertically stacked through a number of short vertical interconnections called TSV with lengths ranging from several microns to several tens of microns. The W-TSV technology is mainly divided into three low-temperature processes: deep-trench etching, dielectric layer formation, and filling with a conductive material. We successfully formed deep Si trenches through a 6-mu m-thick SiO(2) dielectric layer by the modified Bosch process. The depth of the resulting Si trenches with a dielectric layer is approximately 40 mu m. A SiO(2) layer was formed at the bottom and on the sidewall of the Si trenches by sub-atmospheric chemical vapor deposition (SACVD) method using tetraethylorthosilicate (TEOS) and O(3). In addition, we succeeded in uniformly depositing a conformal W metal layer by time-modulated W-CVD method at 300 degrees C.

  354. New reconfigurable memory architecture for parallel image-processing LSI with three-dimensional structure 査読有り

    Shigeo Kodama, Daijirou Amano, Takeaki Sugimura, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 47 (4) 2774-2778 2008年4月

    出版者・発行元:JAPAN SOCIETY APPLIED PHYSICS

    DOI: 10.1143/JJAP.47.2774  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    A reconfigurable memory network for a parallel image-processing LSI with a three-dimensional structure is proposed. The proposed memory network can be dynamically configured by changing the connections between processing elements (PEs) and memories in accordance with the required part of the stored image data. In addition, a specification of the data bandwidth between PEs and the proposed memory network can be changed in the synchronization with single instruction stream-multiple data stream (SIMD) and multiple instruction stream-multiple data stream (MIMD) operations. Therefore, data transfer has greater flexibility. Also, from the result of the performance evaluation by implementation into the field programmable gate array (FPGA), it was successfully shown that the proposed memory network reduced the execution time by up to 28.2% for a 9 x 9 filtering operation.

  355. Power supply system using electromagnetic induction for three-dimensionally stacked retinal prosthesis chip 査読有り

    Ken Komiya, Risato Kobayashi, Takafumi Kobayashi, Keigo Sato, Takafumi Fukushima, Hiroshi Tomita, Hiroyuki Kurino, Tetsu Tanaka, Makoto Tamai, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS 47 (4) 3244-3247 2008年4月

    出版者・発行元:JAPAN SOCIETY APPLIED PHYSICS

    DOI: 10.1143/JJAP.47.3244  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    We have proposed a new retinal prosthesis system consisting of a three-dimension ally (3-D) stacked retinal prosthesis chip, a flexible cable with an electrode array stimulus, and a power supply system for the retinal prosthesis chip. Electromagnetic induction with a primary coil and a secondary coil was employed as the power supply system. The power was transmitted to the retinal prosthesis chip through an RF/DC voltage conversion chip that converted AC voltage into DC voltage. The 3-D stacked retinal prosthesis chip operates with a DC supply voltage of 3.3 V, and the secondary coil requires a transmitted voltage that is I V higher than the DC supply voltage. In order to receive a sufficient supply voltage, several parameters such as external supply voltage and transmission frequency were optimized. A peak RF voltage of 4.5 V was obtained when we employed a primary coil with 50 turns, a secondary coil with 20 turns, an external supply voltage of 4.1 V, and a frequency of 3 MHz. We also successfully fabricated Schottky barrier diodes to rectify the RF voltage received by the secondary coil. The fabricated Schottky barrier diodes have a high breakdown voltage of 4.6 V, which is sufficient for our 3-D stacked retinal prosthesis chip.

  356. Electrical Characterization of Metal–Oxide–Semiconductor Memory Devices with High-Density Self-Assembled Tungsten Nanodots 査読有り

    Yan-Li PEI, Takafumi FUKUSHIMA, Tetsu TANAKA, Mitsumasa KOYANAGI

    Japanese Journal of Applied Physics 47 (4) 2680-2683 2008年4月

    出版者・発行元:None

    DOI: 10.1143/JJAP.47.2680  

    ISSN:0021-4922

  357. A New Nano-System with Three-Dimensional Structure for Real Time Parallel Image Processing

    Mitsumasa Koyanagi, Takafumi Fukushima

    Proceeding of the 5th International Conference on Mechanical Science based on Nanotechnology 117-118 2008年3月6日

  358. 3D system integration technology and 3D systems 招待有り

    Takafumi FUKUSHIMA Tetsu TANAKA, Mitsumasa KOYANAGI

    Abstract Book: European Workshop Materials for Advanced Metallization (MAM) 2008 37-38 2008年3月2日

  359. 自己組織化ウェーハ張り合せによる三次元集積化技術 招待有り

    福島誉史, 田中徹, 小柳光正

    応用物理学会分科会 シリコンテクノロジー 「多層配線」特集号 (99) 34-37 2008年2月8日

  360. Three-Dimensional Super-Chip Integration Technology Using Self-Assembly Technique 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

    2008 IEEE SILICON NANOELECTRONICS WORKSHOP 23-24 2008年

    出版者・発行元:IEEE

  361. Three-dimensional integration technology using self-assembly technique and super-chip integration 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

    PROCEEDINGS OF THE IEEE 2008 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE 10-12 2008年

    出版者・発行元:IEEE

    ISSN:2380-632X

    eISSN:2380-6338

    詳細を見る 詳細を閉じる

    We have proposed a new three-dimensional (3-D) integration technology based on multichip-to-wafer bonding called a super-chip integration. Many chips are simultaneously aligned and bonded onto lower chips using a self-assembly technique in a super-chip integration. It was confirmed that Si chips with sizes of 1 mm square to 5 mm square were precisely assembled on Si wafers with high alignment accuracy of less than 0.5 mu m. We have fabricated 3-D LSI test chips by a super-chip integration technology.

  362. New Three-Dimensional Integration Technology Using Reconfigured Wafers 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 1180-1183 2008年

    出版者・発行元:IEEE

    詳細を見る 詳細を閉じる

    We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100 %. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology).

  363. A Closed-loop Power Control Function for Bio-implantable devices 査読有り

    Kouji Kiyoyama, Yoshito Tanaka, Mashahiro Onoda, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE 321-+ 2008年

    出版者・発行元:IEEE

    詳細を見る 詳細を閉じる

    A wireless communication system with a closed-loop power control function for bio-implantable applications is described which keeps the power dissipation of implantable unit at the allowable level for human body. The function is controlled by monitoring an excessive current at the implantable unit and limiting the power transmission at the external interrogator unit. The implantable unit with the closed-loop power control function has been fabricated in a standard 0.18 mu m CMOS technology, achieved less than 530 mu W with a 1.8V and the chip core size of 0.14 mm(2). The system uses inductive coupling at 13.56MHz with internal and external coils. Experimental results confirm its stable power supply to the implantable unit over a coil distance of 0.5 to 10mm.

  364. 受光素子と刺激電流生成回路を有する完全埋込型人工網膜チップ 査読有り

    田中徹, 福島誉史, 小柳光正

    映像情報メディア学会技術報告 32 (19(IST2008 8-18/CE2008 21-31)) 1015-+ 2008年

    出版者・発行元:None

    DOI: 10.1109/IEDM.2007.4419127  

    ISSN:1342-6893

  365. Multichip self-assembly technique on flexible polymeric substrate 査読有り

    T. Fukushima, T. Konno, T. Tanaka, M. Koyanagi

    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS 1532-1537 2008年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2008.4550179  

    ISSN:0569-5503

    詳細を見る 詳細を閉じる

    We newly introduce a batch assembly technique of a number of LSI and MEM chips onto Si or flexible polymeric substrates using self-assembly driven by surface tension of a small volume of liquid. Self-assembly can provide batch processes including high-precision chip alignment within 0.1 sec and bonding with high adhesion strength more than 5 MPa at room temperature without applying pressure on the chips. The alignment accuracy was found to be approximately 300 nm under optimized conditions when Si wafers were employedas substrates. We also demonstrated multichip self-assembly with a droplet of aqueous or resin solutions onto polymeric substrates with an alignment accuracy of several microns.

  366. A Novel SPRAM (SPin-transfer torque RAM)-based Reconfigurable Logic Block for 3D-Stacked reconfigurable Spin Processor 査読有り

    M. Sekikawa, K. Kiyoyama, H. Hasegawa, K. Miura, T. Fukushima, S. Ikeda, T. Tanaka, H. Ohno, M. Koyanagi

    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST 935-+ 2008年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2008.4796645  

    詳細を見る 詳細を閉じる

    A novel reconfigurable logic block with SPRAM (SPin-transfer torque RAM) is demonstrated. Magnetic elements of 50 x 200 nm(2) in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 k Omega (parallel) and the MR ratio is 91.7%.

  367. New Heterogeneous Multi-Chip Module Integration Technology Using Self-Assembly Method 査読有り

    T. Fukushima, T. Konno, K. Kiyoyama, M. Murugesan, K. Sato, W. -C. Jeong, Y. Ohara, A. Norki, S. Kanno, Y. Kaiho, H. Kino, K. Makita, R. Kobayashi, C. -K. Yin, K. Inamura, K. -W. Lee, J. -C. Bea, T. Tanaka, M. Koyanagi

    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST 499-502 2008年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2008.4796735  

    詳細を見る 詳細を閉じる

    We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mu m were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

  368. Evaluation of platinum-black stimulus electrode array for electrical stimulation of retinal cells in retinal prosthesis system 査読有り

    Taiichiro Watanabe, Risato Kobayashi, Ken Komiya, Takafumi Fukushima, Hiroshi Tomita, Eriko Sugano, Hiroyuki Kurino, Tetsu Tanaka, Makoto Tamai, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 46 (4B) 2785-2791 2007年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.46.2785  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    A retinal prosthesis system with a three-dimensionally (3D) stacked LSI chip has been proposed. We fabricated a new implantable stimulus electrode array deposited with Platinum-black (Pt-b) on a polyimide-based flexible printed circuit (FPC) for the electrical stimulation of the retinal cells. Impedance measurement of the Pt-b electrode-electrolyte interface in a saline solution was performed and the Pt-b electrode realized a very low impedance. The power consumption at the electrode array when retinal cells were stimulated by a stimulus current was evaluated. The power consumption of the Pt-b stimulus electrode array was 91 % lower than that of a previously fabricated Al stimulus electrode array due to a convexo-concave surface. In the cytotoxicity test (CT), we confirmed that Pt implantation induced no cellular degeneration of the rat retina. In the animal experiments, electrically evoked potential (EEP) was successfully recorded using Japanese white rabbits. These results indicate that electrical stimulation using the Pt-b stimulus electrode array can restore visual sensation.

  369. Novel optical/electrical printed circuit board with polynorbornene optical waveguide 査読有り

    Makoto Fujiwara, Yoji Shirato, Hiroshi Owari, Kei Watanabe, Mutsuhiro Matsuyama, Keizo Takahama, Tetsuya Mori, Kenji Miyao, Koji Choki, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 46 (4B) 2395-2400 2007年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.46.23951  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    An optical interconnection with a new optically transparent polymer called polynorbornene (PNB) was investigated for short-distance and high-speed data transmission on printed circuit boards (PCBs). PNB waveguides were formed by simple photoirradiation followed by heating without development and reactive ion etching (RIE) processes. The PNB waveguides exhibit a high-heat resistance of more than 270 degrees C and an extremely low optical loss of 0.029 dB/cm at 830 nm. We successfully integrated PNB waveguides into a multilayer PCB, which we call a optical/electrical printed circuit board (O/E-PCB), and confirmed a basic data transmission rate of 10 Gbps.

  370. Low power spin-transfer magnetoresistive random access memory writing scheme with selective word line bootstrap 査読有り

    Takeaki Sugimura, Takeshi Sakaguchi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 46 (4B) 2226-2230 2007年4月

    出版者・発行元:JAPAN SOC APPLIED PHYSICS

    DOI: 10.1143/JJAP.46.2226  

    ISSN:0021-4922

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    We describe a new writing scheme with a selective word line bootstrap for spin-transfer magnetoresistive random access memory (MRAM). Applying spin-transfer switching to MRAM, its writing power consumption decreases and its memory cell area is also reduced. However, during write operation, the required bit line cramp voltage for stored data switching depends on the value of stored data, magnetic tunnel junction (MTJ) characteristics, and switching current direction. Therefore, the bit line voltage must be optimized to minimize the power consumption. With the proposed scheme, word line voltage is varied according to the value of writing data in order to decrease the threshold bit line voltage. Furthermore, the spin-transfer MRAM resistance model with reading and writing operations was successfully implemented for the circuit simulation. From the simulation results, it was found that writing threshold bit line bias during writing operation can decrease from 17 to 28% with the proposed selective bootstrap. Also, more than 25% of the cell transistor gate width can be decreased. This result shows that the proposed writing scheme is effective in reducing power consumption, and can also reduce the MRAM cell area.

  371. New magnetic nanodot memory with FePt nanodots 査読有り

    Cheng-Kuan Yin, Mariappan Murugesan, Ji-Chel Bea, Mikihiko Oogane, Takafumi Fukushima, Tetsu Tanaka, Shozo Kono, Seiji Samukawa, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 46 (4B) 2167-2171 2007年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.46.2167  

    ISSN:0021-4922

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    A new magnetic nanodot (MND) memory with FePt nanodots was proposed. The FePt nanodots dispersed in SiO2 insulating film was successfully fabricated by self-assembled nanodot deposition (SAND). The size of the FePt nanodot can be controlled by SAND with a different target area ratio of the FePt pellets area in the SiO2 target. Thermal annealing converts the magnetic properties of the FePt nanodots from anti ferrom agnetic into high coercivity ferromagnetic without thermal agglomeration. An L1(0) face-centered tetragonal (fct) FePt MND film was successfully formed which acted as a charge retention layer. Furthermore, the fundamental characteristics of the MND memory were investigated-Using magnetic metal oxide semiconductor (MOS) capacitor devices.

  372. Fully implantable retinal prosthesis chip with photodetector and stimulus current generator

    T. Tanaka, K. Sato, K. Komiya, T. Kobayashi, T. Watanabe, T. Fukushima, H. Tomita, H. Kurino, M. Tamai, M. Koyanagi

    Technical Digest - International Electron Devices Meeting, IEDM 1015-1018 2007年

    DOI: 10.1109/IEDM.2007.4419127  

    ISSN:0163-1918

    詳細を見る 詳細を閉じる

    To recover visual sensation of blind patients, we have fabricated a fully implantable retinal prosthesis chip that includes photodetector and stimulus current generator. For the first time, we successfully implanted the retinal prosthesis chip bonded on the flexible cable with stimulus electrode array into a rabbit eyeball. Moreover, we recorded and analyzed electrically evoked potential (EEP) elicited from a rabbit brain by current stimulation to retina. © 2007 IEEE.

  373. New three-dimensional integration technology to achieve a super chip 査読有り

    Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka

    ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings 318-321 2007年

    DOI: 10.1109/ICSICT.2006.306217  

    詳細を見る 詳細を閉じる

    We have proposed a new mree-dimensional (3D) integration technology based on a chip-to-wafer bonding method which is called a super chip integration technology. Various kinds of chips such as processor chip, memory chips, analog IC chip and sensor chips which are fabricated by different technologies can be vertically stacked into a 3D LSI chip by using a super chip integration technology. Such 3D LSI chip is called a super chip. Various kinds of chips with different chip size, chip thickness and material can be vertically stacked in the super chip integration technology. To establish the super chip integration technology, several key technologies of vertical interconnection formation, chip alignment and bonding, adhesive injection, and chip thinning and planarization were developed. By using the super chip integration technology, three-layer stacked LSI chips with vertical interconnections were successfully fabricated. © 2006 IEEE.

  374. High performance polynorbornene optical waveguide for Opto-Electric interconnections 査読有り

    M. Fujiwara, Y. Shirato, H. Owari, K. Watanabe, M. Matsuyama, K. Takahama, T. Mori, K. Miyao, K. Choki, T. Fukushima, T. Tanaka, M. Koyanagi

    6TH INTERNATIONAL IEEE CONFERENCE ON POLYMERS AND ADHESIVES IN MICROELECTRONICS AND PHOTONICS, PROCEEDINGS 2007 193-+ 2007年

    出版者・発行元:IEEE

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    We have newly developed a multi-mode polymer optical waveguide with polynorbornene (PNB). The PNB waveguide has extremely low optical loss of 0.03 dB/cm at wavelength of 830-nm and high glass transition temperature (Tg) of 270 degrees C. The PNB waveguide can be formed by only UV irradiation step without both etching and developing processes. By using this method, the waveguide can be easily patterned with various shapes such as Y-branch, bend, taper, and so on. In addition, we can fabricate the minimum waveguide pitch less than 75 pm with the 50-mu m-width core. We can also easily fabricate a stacked waveguide because the core layer with flat surface can be formed without an etching and a developing process. In the PNB waveguide, 45 degrees mirror was formed by an excimer laser. This method provides a small mirror (100 mu m x 200 pm) with smooth surface in respective waveguides. From the result of insertion loss measurements, total optical loss was less than 2 dB in an 8-cm-length waveguide with two 45 degrees mirrors. Furthermore, new Opto-Electric (O-E) interconnection with PNB optical waveguide was proposed. This PNB waveguide has high flexibility and high adaptability to reflow soldering process because of its high Tg. Therefore, the PNB waveguide can be formed in flexible printed circuit boards (PCBs) without particular process, as compared to the conventional PCB fabrication process, which leads to low cost O-E interconnection.

  375. Magnetic characteristics of FePt nanodots formed by a self-assembled nanodot deposition method 査読有り

    C. K. Yin, H. Choi, J. C. Bea, M. Murugesan, J. H. Yoo, T. Fukushima, Y. Murakami, T. Tanaka, D. Shindo, M. Miyao, M. Koyanagi

    2007 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2007, Technical Proceedings 4 401-404 2007年

    詳細を見る 詳細を閉じる

    FePt nanodot with L10 face-centered-tetragonal (fct) structure has attracted considerable attention owing to its potentials for new applications including a high-density magnetic data storage and a novel nonvolatile memory which are produced by its high magnetocrystalline anisotropy1. FePt nanodots dispersed in a SiO2 film (FePt nanodot film) were formed by a self-assembled nanodots deposition (SAND) method in which FePt and SiO2 are co-sputtered in a high-vacuum RF magnetron sputtering equipment. Furthermore, FePt nanodot film with a monolayer of FePt nanodots was formed by annealing at 800°C for 1 h, due to the agglomeration of FePt atoms diffused in SiO2 films. The electron holography was a powerful tool to study the single-domain FePt nanodots. In this study, not only the phenomenon of FePt diffusion was evaluated, but also the ferromagnetic phase of monolayer FePt nanodots was analysed by electron holography10-11.

  376. Self-assembly process for chip-to-wafer three-dimensional integration 査読有り

    T. Fulcushima, Y. Yamada, H. Kikuchi, T. Tanaka, M. Koyanagi

    57TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2007 PROCEEDINGS 836-+ 2007年

    出版者・発行元:IEEE

    DOI: 10.1109/ECTC.2007.373895  

    ISSN:0569-5503

    詳細を見る 詳細を閉じる

    We have proposed chip-to-wafer stacking for three-dimensional (3D) integration. To realize the chip to-wafer 3D integration, five key technologies of through-Si interconnection and microbump formation, chip-to-wafer alignment, underfilling, and chip thinning were investigated. Three-layer stacked chips with a layer thickness of several tens microns were fabricated by using the key technologies. Each chip was serially and mechanically aligned and bonded onto a support LSI wafer. In addition, we newly introduce a stacking technique using self-assembly as a key process for advanced chip-to-wafer 3D integration. High-precision alignment with an accuracy of within 1 mu m was obtained and stacking throughput can be dramatically improved by the self-assembly.

  377. New three-dimensional integration technology based on reconfigured wafer-on-wafer bonding technique 査読有り

    Takafumi Fukushima, Hirokazu Kikuchi, Yusuke Yamada, Takayuki Konno, Jun Liang, Keiichi Sasaki, Kiyoshi Inamura, Tetsu Tanaka, Mitsumasa Koyanagi

    2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 985-988 2007年

    出版者・発行元:IEEE

    DOI: 10.1109/IEDM.2007.4419119  

    ISSN:2380-9248

    詳細を見る 詳細を閉じる

    We have proposed a new three-dimensional (3D) integration technology based on reconfigured wafer-on-wafer bonding technique to solve several problems in 3D integration technology using the conventional wafer-on-wafer bonding technique. 3D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100 %. As a result, we can obtain a high production yield even after bonding many wafers. In addition, it is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3D integration technology based on the configured-wafer-on-wafer bonding technique (Reconfig. W-on-W 3D technology). We have developed key technologies to form W Through-Si-Via (TSV) in the reconfigured wafer to fabricated ID LSI test chips. We obtained excellent electrical characteristics of W-TSV using the daisy chain in 3D LSI test chip.

  378. Analysis of GOI-MOSFET with high-k gate dielectric and metal gate fabricated by Ge condensation technique 査読有り

    Mungi Park, Jicheol Bea, Takafumi Fukushima, Mitsumasa Koyanagi

    SURFACE AND INTERFACE ANALYSIS 38 (12-13) 1720-1724 2006年12月

    出版者・発行元:JOHN WILEY & SONS LTD

    DOI: 10.1002/sia.2434  

    ISSN:0142-2421

    詳細を見る 詳細を閉じる

    In order to improve the complementary metal-oxide-semiconductor (CMOS) circuit performance under sub-100 nm technology nodes with low supply voltages, a metal-oxide-semiconductor field-effect transistor (MOSFET) including a high mobility channel and a silicon-on-insulator (SOI) structure is a promising device design. According to The International Technology Roadmap for Semiconductors (ITRS), a 25-nm MOSFET with a gate oxide equivalent oxide thickness (EOT) of 5-8 nm will be produced by 2010. Several groups have reported thermally stable gate dielectrics such as HfO2, ZrO2, HfxSi1-xO, HfOxNy, ZrOxNy, and Ln(2)O(3). However, considering the relatively thick interfacial layer (similar to 0.5 nm SiOx) and the relatively low dielectric constant (10-20) of these materials, it is very difficult to scale down the EOT below 1 nm. In this paper, we report on the electrical characteristics of sputtered HfO2 with an EOT of 0.78 nm. We report Ge metal-insulator-semiconductor field-effect transistors (MISFETs) with HfO2 and W/W2N metal gate electrode on germanium-on-insulator (GOI) wafer obtained by the new graded Ge condensation method. Excellent device characteristics are achieved with a subthreshold swing of 80 mV/dec and low gate leakage. Copyright (C) 2006 John Wiley & Sons, Ltd.

  379. Three-dimensional integration technology based on wafer bonding with vertical buried interconnections 招待有り 査読有り

    Mitsumasa Koyanagi, Tomonori Nakamura, Yuusuke Yamada, Hirokazu Kikuchi, Takafumi Fukushima, Tetsu Tanaka, Hiroyuki Kurino

    IEEE TRANSACTIONS ON ELECTRON DEVICES 53 (11) 2799-2808 2006年11月

    出版者・発行元:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

    DOI: 10.1109/TED.2006.884079  

    ISSN:0018-9383

    eISSN:1557-9646

    詳細を見る 詳細を閉じる

    A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip. This 3-D technology is based on the wafer bonding and thinning method. Five key technologies for 3-D integration were developed, namely, the formation of vertical buried interconnections, metal microbump formations, stacked wafer thinning, wafer alignment, and wafer bonding. Deep trenches having a diameter of 2 mu m and a depth of approximately 50 mu m were formed in the silicon substrate using inductively coupled plasma etching to form vertical buried interconnections. These trenches were oxidized and filled with n+ polycrystalline silicon or tungsten. The 3-D devices and 3-D shared-memory test chips with three-stacked layers were fabricated by bonding the wafers with vertical buried interconnections after thinning. No characteristic degradation was observed in the fabricated 3-D devices. It was confirmed that fundamental memory operation and broadcast operation between the three memory layers could be successfully performed in the fabricated 3-D shared-memory test chip.

  380. Development of Si Long Microprobe (SiLM) for Platform of Intelligent Neural Implant Microsystem 査読有り

    Risato Kobayashi, Taiichiro Watanabe, Ken Komiya, Takafumi Fukushima, Kazuhiro Sakamoto, Hiroyuki Kurino, Tetsu Tanaka, Norihiro Katayama, Hajime Mushiake, Mitsumasa Koyanagi

    International Conference on Solid State Devices and Materials 898-899 2006年9月12日

  381. Magnetic properties of FePt nanodots formed by a self-assembled nanodot deposition method 査読有り

    C. K. Yin, T. Fukushima, T. Tanaka, M. Koyanagi, J. C. Bea, H. Choi, M. Nishijima, M. Miyao

    APPLIED PHYSICS LETTERS 89 (6) 063109-1-063109-3 2006年8月

    出版者・発行元:AMER INST PHYSICS

    DOI: 10.1063/1.2335588  

    ISSN:0003-6951

    詳細を見る 詳細を閉じる

    Fe50Pt50 nanodots dispersed in a SiO2 film (Fe50Pt50 nanodot film) were formed by a self-assembled nanodot deposition (SAND) method in which Fe50Pt50 and SiO2 are cosputtered in a high vacuum rf magnetron sputtering equipment. Fe50Pt50 pellets are laid on a SiO2 target in a sputtering chamber to form the Fe50Pt50 nanodot film in the SAND method. The size and density of Fe50Pt50 nanodot were controlled by changing the ratio of the total area of Fe50Pt50 pellets to that of SiO2 target. The Fe50Pt50 nanodot size decreases and its density increases when the ratio decreases. As-deposited Fe50Pt50 nanodots self-assembled to a face-centered-cubic phase of single-crystal structure. The Fe50Pt50 nanodot films were annealed to evaluate the nanodot size controllability, the magnetic anisotropy, and the thermal stability. Fully ordered L1(0) face-centered-tetragonal Fe50Pt50 nanodots with high magnetocrystalline anisotropy (K-u congruent to 8.7x10(7) ergs/cm(3)) were obtained by in situ annealing at 600 degrees C for 1 h in a high vacuum ambience. Furthermore, the Fe50Pt50 nanodot film with a monolayer of Fe50Pt50 nanodots was formed by annealing at 800 degrees C due to the agglomeration of Fe50Pt50 nanodots in the SiO2 film. (c) 2006 American Institute of Physics.

  382. Multichip shared memory module with optical interconnection for parallel-processor system 査読有り

    Hirofumi Kuribara, Hiroyuki Hashimoto, Takafumi Fukushima, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3504-3509 2006年4月

    出版者・発行元:JAPAN SOC APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.3504  

    ISSN:0021-4922

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    A new multichip shared memory module with optical interconnection for a parallel-processor system was introduced. The new shared memory module mainly consists of shared memory units optically connected to one another through polyimide waveguides and electrically connected to processor elements. We designed and fabricated a static random access memory (SRAM) test chip which has an optical/electrical (O/E) receiver circuit and electrical/optical (E/O) transmitter circuit for optical data transfer. A vertical-cavity surface-emitting laser diode (VCSEL) was integrated onto an LSI chip by the beam-lead bonding technique. Optical data transfer was achieved using polyimide optical waveguides with Al micromirrors formed on a Si substrate. called an optical plate, and the optical writing and electrical reading operation in the SRAM test chip was successfully demonstrated.

  383. Low-power and high-sensitivity magnetoresistive random access memory sensing scheme with body-biased preamplifier 査読有り

    Takeaki Sugimura, Jun Deguchi, Hoon Choi, Takeshi Sakaguchi, Hyuckjae Oh, Takafumi Fukushima, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3321-3325 2006年4月

    出版者・発行元:JAPAN SOC APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.3321  

    ISSN:0021-4922

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    In this paper, we describe a new magnetoresistive random access memory (MRAM) sensing scheme with a body-biased preamplifier for low-power and high-sensitivity operation. The proposed new MRAM sense amplifier consists of a current sense preamplifier with a body biasing differential pair of a common-gate amplifier and a voltage sense amplifier. The preamplifier controls bitline voltage appropriately and amplifies the difference in bitline current as current-mode sense amplifier. The new sense amplifier enhances sensitivity, and the body-biased preamplifier enables low-voltage operation. To evaluate the proposed circuit, the modeling of magnetic tunnel junction (MTJ) resistance characteristics was performed with a VHDL-AMS description, and the proposed circuit was simulated with a mixed signal circuit simulator. From the simulation result, it is confirmed that the proposed sensing scheme results in a 1.57 times faster access time than a conventional scheme, and that the power of the sense amplifier is lower than that of the conventional amplifier at the same speed.

  384. Quantitative derivation and evaluation of wire length distribution in three-dimensional integrated circuits using simulated quenching 査読有り

    Jun Deguchi, Takeaki Sugimura, Yoshihiro Nakatani, Takafumi Fukushima, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3260-3265 2006年4月

    出版者・発行元:JAPAN SOC APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.3260  

    ISSN:0021-4922

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    Three-dimensional (3D) integration is the most promising technology to improve IC performance by stacking some active device layers and connecting them using vertical interconnections. In this paper, in order to quantitatively evaluate the benefits of 3D IC, wire length distributions in 3D ICs are derived by adapting the simulated quenching algorithm for 3D placement and routing of specific benchmark circuits. By evaluating the wire length distribution, we can confirm that the total wire length is reduced by 26.0 and 41.3% with three and five active layers, respectively. Similarly, 38.1 and 52.0% reduction in the longest wire length with three and five active layers can be achieved.

  385. Fabrication and evaluation of magnetic tunnel junction with MgO tunneling barrier 査読有り

    Takeshi Sakaguchi Hoon Choi, Ahn Sung-Jin, Takeaki Sugimura, Mungi Park, Milcihiko Oogane, Hyuckjae Oh, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Takafumi Fukushima, Terunobu Miyazaki, Hideo Ohno, Mitsumasa Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3228-3232 2006年4月

    出版者・発行元:JAPAN SOC APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.3228  

    ISSN:0021-4922

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    Magnetoresistive random access' memory (MRAM) has recently attracted considerable attention due to its non-volatility and high programming speed. A high Tunnel magnetoresistance (TMR) ratio is a key factor of MRAM. However, a conventional MRAM using aluminum oxide as insulator film shows a low TMR ratio of several tens of percents. MgO tunneling insulator is one of the candidates for achieving a high TMR ratio. In this study, we fabricated and evaluated Magnetic tunnel junctions (MTJs) with MgO tunneling barrier on a clad Cu word line.

  386. New magnetic flash memory with FePt magnetic floating gate 査読有り

    CK Yin, JC Bea, YG Hong, T Fukushima, M Miyao, K Natori, M Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3217-3221 2006年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.3217  

    ISSN:0021-4922

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    A novel flash memory which has FePt magnetic floating gate was proposed. An FePt magnetic floating gate with a high coercivity was successfully fabricated by DC magnetron sputtering with rapid thermal annealing. As for magnetic properties, the switching magnetic fields of 21 Oe for the NiFe film and 1600 Oe for the FePt film were employed for the control gate and the floating gate materials, respectively. The fundamental characteristics of the magnetic flash memory were confirmed using magnetic metal oxide semiconductor (MOS) capacitor devices and magnetic tunneling diode (MTD) devices.

  387. Characteristics of silicon-on-low k insulator metal oxide semiconductor field effect transistor with metal back gate 査読有り

    Y Yamada, H Oh, T Sakaguchi, T Fukushima, M Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3040-3044 2006年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.30401  

    ISSN:0021-4922

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    We proposed a silicon-on-low k insulator (SOLK) metal oxide semiconductor field effect transistor (MOSFET) with a metal back gate for high-speed and ultralow power devices. In this work, Benzocyclobutene (BCB) and tetramethyl ammonium hydroxide (TMAH) were employed to fabricate SOLK Devices without damaging the transistor channels. We successfully fabricated the proposed submicron fully depleted (FD) SOLK MOSFETs with a metal back gate. The process technologies and electrical properties of SOLK MOSFETs were introduced in detail. Furthermore, threshold voltage shift was obtained at 55 mV/V using a NMOSFET and at 35 mV/V using a PMOSFET and drain current characteristics are enhanced by the back gate bias.

  388. Deep-trench etching for chip-to-chip three-dimensional integration technology 査読有り

    H Kikuchi, Y Yamada, H Kuima, T Fukushima, M Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3024-3029 2006年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.3024  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    Deep-Si-trench etching was investigated to establish chip-to-chip three-dimensional (3D) integration technology where completed two-dimensional (2D) LSI chips fabricated using standard complementary metal oxide semiconductor (CMOS) technology can be vertically stacked through a number of vertical interconnections formed in the 2D LSI chips. The formation of deep Si trenches through dielectric layers is a key process in chip-to-chip 3D integration technology. In this process, trench profile is an important factor to achieve the complete filling of the resulting deep Si trenches with conductive materials. We have successfully obtained deep Si trenches with a depth of 28 mu m through a 7-mu m-thick SiO2 layer by inductively coupled plasma (ICP) etching using a time-modulated bias. The desirable high-aspect-ratio Si trenches with a forward tapered shape, a 3.0 mu m top width and a 2.4 mu m bottom width were also formed in a Si test chip glued on a Si wafer supporting material by the Bosch process.

  389. Nickel germanide formation on condensed Ge layer for Ge-on-insulator device application 査読有り

    H Choi, M Park, T Fukushima, M Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 2984-2986 2006年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.2984  

    ISSN:0021-4922

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    As an effort for realizing a germanium-on-insulator (GOI) device, a method of fabricating a GOI substrate and a technique for forming nickel germanide by a multistep annealing method are presented in this paper. A GOI substrate was fabricated by a germanium condensation technique, that involves a new approach of SiGe epitaxial growth on a silicon-on-insulator (SOI) substrate at a certain modulating gas ratio (Si2H6/GeH4). From the results of atomic force microscopy (AFM), X-ray diffractometer (XRD) and Raman spectroscopy measurements, it was found that this technique can be practically used for GOI substrate fabrication. The novel nickel germanide formation technique with the multistep annealing method was also studied on a condensed GOI layer. A NiGe layer with a low sheet resistance (6.5 Omega/sq.) was obtained at 500 degrees C. This result confirmed that this method is suitable for nickel germanide formation for fabricating GOI MOSFETs with low source/drain resistances. These technologies are applicable to GOI device fabrication.

  390. Effects of ion implantation damage on elevated source/drain formation for ultrathin body silicon on insulator metal oxide semiconductor field-effect transistor 査読有り

    H Oh, T Sakaguchi, T Fukushima, M Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 2965-2969 2006年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.2965  

    ISSN:0021-4922

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    For high-speed and low-power performance, ultrathin body (UTB) silicon on insulator (SOI) metal oxide semiconductor field-effect semiconductors (MOSFETs) with an elevated source/drain (ESD) have been investigated using selectively epitaxial growth (SEG) technology. In this work, We found that the morphology of a SEG layer on an ultrathin Si film and the crystallinity of the top Si film are strongly dependent on ion implantation damage. The morphology and surface roughness of SEG layers were investigated by field emission scanning electron microscopy (FE-SEM) and the crystallinities of the top silicon films with and without ion implantation were characterized by atomic force microscopy (AFM) and Rutherford backscattering spectroscopy (RBS), respectively. Furthermore, to suppress ion implantation damage, a SEG layer was formed before ion implantation for source drain extension (SDE) formation by the sacrificial sidewall spacer method. As results, UTB SOI-MOSFETs with a flat ESD were successfully fabricated by the proposed method.

  391. New three-dimensional integration technology using chip-to-wafer bonding to achieve ultimate super-chip integration 査読有り

    T Fukushima, Y Yamada, H Kikuchi, M Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (4B) 3030-3035 2006年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.45.3030  

    ISSN:0021-4922

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    A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In-Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm 2 and ranging in thickness from 30 to 90 pm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.

  392. Research and development of transistor structure in nano-scale region 査読有り

    M. Koyanagi, Y. Yamada, M. Park, T. Fukushima, T. Tanaka

    2006 INTERNATIONAL WORKSHOP ON NANO CMOS, PROCEEDINGS 34-37 2006年

    出版者・発行元:IEEE

  393. Development of new three-dimensional integration technology for retinal prosthesis 査読有り

    Yusuke Yamada, Jun Deguchi, Taiichiro Watanabe, Takafumi Fukushima, Hiroyuki Kurino, Tetsu Tanaka, Mitsumasa Koyanagi

    FUTURE MEDICAL ENGINEERING BASED ON BIONANOTECHNOLOGY, PROCEEDINGS 613-+ 2006年

    出版者・発行元:WORLD SCIENTIFIC PUBL CO PTE LTD

    DOI: 10.1142/9781860948800_0067  

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    We propose a new three-dimensional (3D) integration technology using SOI transistors and low-k dielectric material for low power retinal prosthesis chip, In this technology, the crystalline silicon is used only in the transistor channel region. Metal wirings and MOS transistors are completely surrounded by low-k dielectric materials to reduce the parasitic capacitances. Therefore, this technology is indispensable for realizing low-power and high-speed retinal prosthesis chip. To establish such 3D integration technology, we have developed the key technologies such as the wafer bonding and the removal of silicon substrate. In this work, we successfully fabricated the proposed submicron fully depleted (FD) SOI MOSFETs.

  394. Neuromorphic analog circuits for three-dimensionally stacked vision chip 査読有り

    Jun Liang, Yoshihiro Nakagawa, Jun Deguchi, Jeoung-Chill Shim, Takafumi Fukushima, Hiroyuki Kurino, Tetsu Tanaka, Mitsumasa Koyanagi

    FUTURE MEDICAL ENGINEERING BASED ON BIONANOTECHNOLOGY, PROCEEDINGS 455-+ 2006年

    出版者・発行元:WORLD SCIENTIFIC PUBL CO PTE LTD

    DOI: 10.1142/9781860948800_0049  

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    Three-dimensional (3D) LSI technology is useful for realizing artificial neuromorphic system since it provides a massively interconnected wiring structure similar to the layered structure of living retina or cortex, which is suitable for highly parallel processing. We propose a new 3D stacked vision chip with high fill-factor and high resolution. We have evaluated the basic characteristics of circuits used in vision chip and demonstrated the basic functions of 3D stacked vision test chip fabricated using our 3D integration technology.

  395. Chip-to-wafer three-dimensional integration technology for retinal prosthesis chips 査読有り

    Hircrazu Kikuchi, Yusuke Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

    FUTURE MEDICAL ENGINEERING BASED ON BIONANOTECHNOLOGY, PROCEEDINGS 385-+ 2006年

    出版者・発行元:WORLD SCIENTIFIC PUBL CO PTE LTD

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    We newly introduce three-dimensional (3D) integration technology based on chip-to-wafer bonding into the fabrication of advanced retinal prosthesis chips. By using the 3D integration technology, a photodiode chip, an image processor chip, and an electrical current generator chip can be vertically stacked and electrically connected by a number of short vertical interconnections. The formation of deep Si trenches through dielectric layers is a key process in the chip-to-wafer 3D integration technology. In this etching process, trench profile is an important factor to achieve the complete filling of the resulting deep Si trenches with conductive materials. We have successfully obtained deep Si trenches with a depth of 28 mu m through a 7-mu m-thick SiO2 layer by inductively coupled plasma (ICP) etching using a time-modulated bias. High-aspect-ratio deep Si trenches with a top width of 3.0 mu m and a bottom width of 2.4 mu m were also formed in a Si test chip by the Bosch process.

  396. Novel retinal prosthesis system with three dimensionally stacked LSI chip 査読有り

    T. Watanabe, H. Kikuchi, T. Fukushima, H. Tomita, E. Sugano, H. Kurino, T. Tanaka, M. Tamai, M. Koyanagi

    ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE 327-+ 2006年

    出版者・発行元:IEEE

    DOI: 10.1109/ESSDER.2006.307704  

    ISSN:1930-8876

    詳細を見る 詳細を閉じる

    We have proposed a novel retinal prosthesis system with three-dimensionally stacked retinal prosthesis chip. The retinal prosthesis chip consists of several LSI chips that are vertically stacked and electrically connected using three-dimensional integration technology. We fabricated retinal prosthesis chip including photodetectors and stimulus current generators. We confirmed that current waveform parameters can be varied by bias voltages. Implantable stimulus electrode array was also fabricated for the electrical stimulation of the retina. To evaluate optimal retinal stimulus current, electrically evoked potential (EEP) was recorded in animal experiments. The recorded waveform shows a similar behavior to the visually evoked potential (VEP) waveform, indicating possibilities that the electrical stimulation of the retina can restore visual sensation for the blind patients.

  397. Evaluation of electrical stimulus current applied to retinal cells for retinal prosthesis 査読有り

    Taiichiro Watanabe, Keita Motonami, Takafumi Fukushima, Hiroyuki Kurino, Tetsu Tanaka, Mitsumasa Koyanagi

    FUTURE MEDICAL ENGINEERING BASED ON BIONANOTECHNOLOGY, PROCEEDINGS 45 (4B) 585-+ 2006年

    出版者・発行元:WORLD SCIENTIFIC PUBL CO PTE LTD

    DOI: 10.1142/9781860948800_0065  

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    We have proposed a novel retinal prosthesis system with three-dimensionally stacked retinal prosthesis chip. We employ the three-dimensional integration technology to realize the high performance retinal prosthesis system. To restore the visual sensation by stimulating the retinal cells, it is essential to determine the optimal stimulus current for designing retinal prosthesis chips. Therefore, we fabricated a stimulus electrode array on a flexible cable for recording of electrically evoked potential (EEP) to optimize the parameters of stimulus current. As a result of animal experiment, the recorded waveform shows a similar behavior to the visually evoked potential (VEP) waveform, indicating possibilities that the electrical stimulation of the retina can restore visual sensation for the blind patients. Furthermore, we developed the Si microprobe for recording of neuronal signals from the animals' brain. By using fabricated Si microprobe, we successfully recorded the neuronal signals from the brain of monkey. This result indicates that Si microprobe array enable us to performed the advanced recording as compared with conventional EEP recording in future.

  398. ロボットビジョンシステムのための積層型並列リコンフィギャラブル画像処理プロセッサの設計 査読有り

    杉村武昭, 小西雄太, 出口淳, 石原聡之, 福島誉史, 近野敦, 内山勝, 小柳光正

    電子情報通信学会論文誌 D J89-D (6) 1141-1152 2006年

    ISSN:1880-4535

  399. New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super Chip Integration 査読有り

    T. Fukushima, Y. Yamada, H. Kikuchi, M.Koyanagi

    Proceeding of SOLID STATE DEVICES AND MATERIALS (SSDM) 2005 64-65 2005年9月

  400. Nickel Germanide Formation on Condensed Ge Layer For Ge-on-Insulator Device Application 査読有り

    Hoon CHOI, Mungi PARK, Takafumi FUKUSHIMA, Mitsumasa KOYANAGI

    International Conference on Solid State Device and Materials (SSDM) 572-573 2005年9月

  401. Characteristics of Silicon-on-Low-K Insulator (SOLK) MOSFET with Metal Back-Gate 査読有り

    Y. Yamada, Hyuckjae Oh, T. Sakaguchi, T. Fukushima, M. Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 66-67 2005年9月

  402. Multi-Chip Shared-Memory Module with Optical Interconnection for Parallel Processor System 査読有り

    Hirofumi Kuribara, Hiroyuki Hashimoto, Takafumi Fukushima, Mitsumasa Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 2005 334-335 2005年9月

  403. Magnetic and Microstructural Properties of FePt L10 Nanoparticle Films Fabricated by Self-Assembled Nano-Dot Deposition(SAND) Method 査読有り

    J. C. Bea, C.-K. Yin, M. Nishijima,T. Fukushima, T. Sadoh, M. Miyao, M. Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 436-437 2005年9月

  404. Intelligent Neural Implant Microsystem Fabricated Using Multi-Chip Bonding Technique 査読有り

    Taiichiro Watanabe, Keita Motonami, Kazuhiro Sakamoto, Jun Deguchi, Risato Kobayashi, Ken Komiya, Keiji Okumura, Takafumi Fukushima, Hiroyuki Kurino, Hajime Mushiake, Mitsumasa Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 2005 462-463 2005年9月

  405. Influences of Ion Implantation Damages on Elevated Source/Drain Formation for Ultra-Thin Body SOI MOSFET 査読有り

    Hyuckjae Oh, Takeshi Sakaguchi, Jicheol Bea, Takafumi Fukusima, Mitsumasa Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 520-521 2005年9月

  406. Deep Trench Etching for Chip-to-Chip Three-Dimensional Integration 査読有り

    Hirokazu Kikuchi, Yusuke Yamada, Hitoshi Kijima, Takafumi Fukushima

    International Conference on Solid State Device and Materials (SSDM) 562-563 2005年9月

  407. Characteristics of Metal Gate GOI-MOSFET with High-k Gate Dielectric Fabricated by Ge Condensation Method 査読有り

    Mungi Park, Hoon Choi, Jicheol Bea, Takafumi Fukushima, Mitsumasa Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 588-589 2005年9月

  408. Fabrication and Evaluation of Magnetic Tunnel Junction with MgO Tunneling Barrier 査読有り

    Takeshi Sakaguchi, Hoon Choi, Takeaki Sugimura, Mikihiko Oogane, Hyuckjae Oh, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Takafumi Fukushima, Terunobu Miyazaki, Hideo Ohno, Mitsumasa Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 642-643 2005年9月

  409. Estimation of Wire Length Distribution for Evaluating Performance Improvement of Three-Dimensional LSI 査読有り

    Jun Deguchi, Yoshihiro Nakatani, Takeaki Sugimura, Takafumi Fukushima, Mitsumasa Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 2005 660-661 2005年9月

  410. Low Power and High Sensitivity MRAM Sensing Scheme with Body Biased Preamplifier 査読有り

    Takeaki Sugimura, Jun Deguchi, Hoon Choi, Takeshi Sakaguchi, Hyuchjae Oh, Takafumi Fukushima, Mitsumasa Koyanagi

    International Conference on Solid State Device and Materials (SSDM) 2005 928-929 2005年9月

  411. 三次元積層型リコンフィギャラブル画像処理プロセッサを用いたロボットビジョンシステム

    杉村武昭, 出口淳, 小西雄太, 中谷好博, 福島誉史, 近野敦, 栗野浩之, 内山勝, 小柳光正

    電子情報通信学会技術研究報告 105 (43(RECONF2005 15-29)) 79-84 2005年

    ISSN:0913-5685

  412. New three-dimensional integration technology using self-assembly technique 査読有り

    T Fukushima, Y Yamada, H Kikuchi, M Koyanagi

    IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST 359-362 2005年

    出版者・発行元:IEEE

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    To achieve ultimate super chip integration, we have developed a new three-dimensional integration technology called Super-Smart-Stack technology using a novel self-assembly technique. The chip alignment accuracy of within 1 mu m is obtained by the self-assembly technique. We demonstrated for the first time that 3D SRAM test chip with ten memory layers was successfully fabricated using the Super-Smart-Stack (SSS) technology.

  413. Deep Si Hole Etching Technique for Super Chip Integration 査読有り

    T. Fukushima, H. Kurino, H. Kikuchi, H. Kijima, Y. Yamada, J. Shim, M. Koyanagi

    Proceeding of The Electrochemical Society International Semiconductor Technology Conference (ISTC) 364-366 2004年9月

  414. Bump Formation Technique for Multi-Chip Module with Optical Interconnections 査読有り

    T. Fukushima, H. Kurino, R. Nitobe, H. Kuribara, Y. Yamada, J. Shim, M. Koyanagi

    Proceeding of The Electrochemical Society International Semiconductor Technology Conference (ISTC) 442-444 2004年9月

  415. Ultimate Functional Multi-Electrode System (UFMES) Formed by Multi-Chip Bonding Technology 査読有り

    T. Watanabe, K. Motonami, K. Sakamoto, J. Deguchi, T. Fukushima, J. Shim, H. Mushiake, H. Kurino, M. Koyanagi

    Proceeding of 2004 International Conference on Solid State Device and Materials (SSDM) 2004年9月

  416. Ultrathin-SOI PMOSFET with Elevated S/D and buried back gate

    H. Oh, T. Fukushima, T. Sakaguchi, J. Shim, C. Yin, M. Park, H. Kurino, M. Koyanagi

    Proceeding of The Electrochemical Society International Semiconductor Technology Conference (ISTC) 51-56 2004年9月

  417. Three-dimensionally stacked analog retinal prosthesis chip 査読有り

    J Deguchi, T Watanabe, T Nakamura, Y Nakagawa, T Fukushima, S Jeoung-Chill, H Kurino, T Abe, M Tamai, M Koyanagi

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 43 (4B) 1685-1689 2004年4月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.43.1685  

    ISSN:0021-4922

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    As blind patients with an intact optic nerve and damaged photoreceptor cells increase in number in recent years, there has been a growing interest in visual prostheses by electrically stimulating their retinas. Previous clinical studies indicated that blind patients perceive a controlled electrical current applied to a small area of the retina via electrodes as a spot of light. We propose a novel implantable device, so-called three-dimensionally (3D) stacked retinal prosthesis, which is composed of a photodetector. an image processor, electrical current generator circuits, and an electrode array on one chip. The spice simulation showed that our designed analog circuits for 3D stacked retinal prosthesis chip could output desirable electrical current with variable pulse width by controlling bias voltages.

  418. 並列リコンフィギュラブル画像処理プロセッサを用いたロボットビジョンシステム

    杉村武昭, 出口淳, 小西雄太, 中谷好博, 福島誉史, 近野敦, 栗野浩之, 内山勝, 小柳光正

    電子情報通信学会技術研究報告 104 (521(ICD2004 183-192)) 49-54 2004年

    ISSN:0913-5685

  419. Heat-resistant photoresists based on new imaging technique: reaction development patterning 査読有り

    T Fukushima, Y Kawakami, A Kitamura, T Oyama, M Tomoi

    JOURNAL OF MICROLITHOGRAPHY MICROFABRICATION AND MICROSYSTEMS 3 (1) 159-167 2004年1月

    出版者・発行元:SPIE-INT SOCIETY OPTICAL ENGINEERING

    DOI: 10.1117/1.1633273  

    ISSN:1537-1646

    詳細を見る 詳細を閉じる

    Spin-coated films of nonphotosensitive engineering thermoplastics mixed with photosensitive agent diazonaphthoquinone (DNQ) can be clearly imaged with near-UV light. The selected engineering thermoplastics are commercially available poly(bisphenol A carbonate), polyarylate (U polymer(R)) and polyetherimide (Ultem(R)), and synthesized fluorinated polyimide, which have no specific functional groups. Development with a solution including ethanolamine dissolves the irradiated areas to give positive fine patterns. The two-component photosensitive systems shows good photosensitivity and resolution (line/space 10/10 mum) with about 10 to 15 mum in thickness. Gel-permiation chromatography (GPC) and H-1-NMR measurements that can give information on the structure of components dissolved from the irradiated regions are carried out to make clear the imaging mechanism, which we call reaction development patterning (RDP). RDP-based photosensitive polymers showed high heat resistance up to their glass transition temperature (T-g) or above. (C) 2004 Society of Photo-Optical Instrumentation Engineers.

  420. Photosensitive fluorinated polyimides with constant based on reaction development a low dielectric patterning 査読有り

    T Miyagawa, T Fukushima, T Oyama, T Iijima, M Tomoi

    JOURNAL OF POLYMER SCIENCE PART A-POLYMER CHEMISTRY 41 (6) 861-871 2003年3月

    出版者・発行元:JOHN WILEY & SONS INC

    DOI: 10.1002/pola.10638  

    ISSN:0887-624X

    詳細を見る 詳細を閉じる

    The fluorinated polyimide PI(6FDA/HFBA.PP) was prepared by the reaction of 4,4'-(hexafluoroisopropylidene)diphthalic anhydride (6FDA) with 2,2-bis[4-(4-aminophenoxy)phenyl]hexafluoropropane (HFBAPP) in 1-methyl-2-pyrrolidone/toluene. A multiblock copolyimide with both fluorinated and rigid-rod segments, PI(6FDA/ HFBAPP)(BPDA/2-DMB), was prepared by the addition of a second dianhydride, 3,3',4,4'-biphenyltetracarboxylic dianhydride (BPDA), and a second diamine, 2,2'-dimethylbenzidine (2-DMB), to the polyimide main chain. The potential lithographic performance of photosensitive polyimides composed of nonphotosensitive fluorine-containing polyimides and photosensitive diazonaphthoquinone (DNQ) was studied on the basis of a new imaging principle recently proposed by our laboratory, that is, reaction development patterning. Neat PI(6FDA/HFBAPP) showed a low dielectric constant (E) of 2.41 and a low dissipation factor (tan delta) of 0.0027 at 20 GHz, and a 10-mum resolution of the fluorinated polyimide/DNQ system was demonstrated with reactive development with a solution including ethanolamine after ultraviolet exposure. Although slight changes in the dielectric properties were observed in the presence of DNQ residues, these values (epsilon = 2.63 and tan delta = 0.0033 at 20 GHz) were low enough for use in microelectronic applications. However, PI(6FDA/HFBA.PP)(BPDA/2-DMB), having a lower coefficient of thermal expansion (CTE; 33 ppm/degreesC) than PI(6FDA/HFBAPP) (49 ppm/degreesC), exhibited good positive photosensitivity, whereas the relatively low-CTE multiblock copolyimide displayed a much higher epsilon value (3.48 at 1 MHz) than the highly fluorinated polyimide (2.88 at 1 MHz). A film consisting of PI(6FDA/HFBAPP)(BPDA/ 2-DMB) and the remaining DNQ derivatives showed a CTE value comparable to that of the neat polyimide film. (C) 2003 Wiley Periodicals, Inc. J Polym Sci Part A: Polym Chem 41: 861-871,2003.

  421. Ultrafast active transmission lines with low-k polyimide integrated with ultrafast photoconductive switches 査読有り

    S Yagi, T Itatani, H Kawanami, S Gorwadkar, T Uemura, T Fukushima, H Itatani, M Tomoi, M Tacano

    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS 42 (2B) L154-L156 2003年2月

    出版者・発行元:INST PURE APPLIED PHYSICS

    DOI: 10.1143/JJAP.42.L154  

    ISSN:0021-4922

    詳細を見る 詳細を閉じる

    We fabricated the first ultrafast active transmission lines with low dielectric constant (low-k) polyimide integrated with ultrafast photoconductive switches formed by the nano-anodization process. Electrical pulses as short as 290 fs were measured on this transmission line by an electrooptic sampling system based on a femtosecond laser. P-n junctions were inserted in the transmission line to control dispersion in lines, and low-k polyimide was introduced to reduce dielectric and radiation losses.

  422. Heat-resistant photoresists based on new imaging technique: reaction development patterning (RDP) 査読有り

    T Fukushima, T Oyama, M Tomoi

    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2 5039 960-967 2003年

    出版者・発行元:SPIE-INT SOC OPTICAL ENGINEERING

    DOI: 10.1117/12.483709  

    ISSN:0277-786X

    詳細を見る 詳細を閉じる

    Spin-coated films of non-photosensitive engineering thermoplastics mixed with photosensitive. agent diazonaphthoquinone (DNQ) can be imaged with near-UV light. The engineering thermoplastics selected for study are commercially available poly(bisphenol A carbonate), polyarylate (U polymer((R))) and polyetherimide (Ultem((R))), and synthesized fluorinated polyimide, which have no specific functional groups. Development with a solution including ethanolamine dissolves the irradiated areas to give positive fine patterns. The two-component photosensitive systems showed good photosensitivity and resolution (line/space 10/10 mum) with about 10-15 mum in thickness.

  423. Ionic-bonded negative photosensitive polyimides having pendant aminoalkyl (meth)acrylamide groups 査読有り

    T Fukushima, T Oyama, M Tomoi

    REACTIVE & FUNCTIONAL POLYMERS 56 (1) 59-73 2003年

    出版者・発行元:ELSEVIER SCIENCE BV

    DOI: 10.1016/S1381-5148(03)00033-6  

    ISSN:1381-5148

    詳細を見る 詳細を閉じる

    Soluble polyimides having pendant carboxyl groups were prepared by a direct one-pot polycondensation of various acid dianhydrides with 3.5-diaminobenzoic acid and bis[4-(3-aminophenoxy)phenyl]sulfone in the presence of gamma-valerolactone/pyridine catalyst in 1-methyl-2-pyrrolidone (NMP)/toluene mixture at 180 degreesC. The pendant carboxyl groups were blocked with photopolymerizable (meth)acrylamides, N-[3-(dimethylamino)propyl]acrylamide (DMAPAA), N-[3-(dimethylamino)propyl]methacrylamide (DMAPMA), or N-[3-(diethylamino)propyl]methacrylamide (DEAPMA), through ionic bonding at room temperature. The ionic-bonded photosensitive polyimide films containing photosensitizer Michler's ketone (MK) and ethylene glycol dimethacrylate (EGDMA) as an external multifunctional cross-linker gave negative-tone behavior by near-UV irradiation followed by development with 10% aqueous NaOH at 25 degreesC. The SEM photograph of the resultant images showed fine patterns (line/space 20/20 mum) with similar to15 mum in film thickness. The sensitivity of photosensitive polyimides with DMAPAA or DMAPMA was higher than that of photosensitive polyimides with (meth)acrylate esters such as 2-(dimethylamino)ethyl acrylate (DMAEA), 3-(dimethylamino)propyl acrylate (DMAPA), 2-(dimethylamino)ethyl methacrvlate (DMANA), and 2-(diethylamino)ethyl methacrylate (DEAMA). (C) 2003 Elsevier B.V. All rights reserved.

  424. 反応現像画像形成法を基盤とした感光性エンジニアリングプラスチックの開発 招待有り 査読有り

    福島誉史, 大山俊幸, 友井正男

    日本化学会講演予稿集 83rd (2) 585-588 2003年

    ISSN:0285-7626

  425. New Concept of Heat-Resistant Photoresists: Reaction Development Patterning (RDP) 査読有り

    T. Fukushima, T. Oyama, M. Tomoi

    IUPAC World Polymer Congress 2002, 39th International Symposium on Macromolecules 2002年7月

  426. Positive Photosensitive Polyimides Based on Novel Imaging Principle: Reaction Development Patterning (RDP)

    T. Fukushima, T. Oyama, M. Tomoi

    Proceedings of STEPI6: 6th European Technical Symposium on Polyimides and High Performance Functional Polymer 2002年5月

  427. Photosensitive polyarylates based on reaction development patterning 査読有り

    T Oyama, A Kitamura, T Fukushima, T Iijima, M Tomoi

    MACROMOLECULAR RAPID COMMUNICATIONS 23 (2) 104-108 2002年1月

    出版者・発行元:WILEY-V C H VERLAG GMBH

    ISSN:1022-1336

    詳細を見る 詳細を閉じる

    Communication: Films of a commercially available polyarylate (U polymer(R)) containing a photosensitive agent were prepared by means of spin-coating onto copper foil, which showed positive-tone behavior after UV irradiation and development with an ethanolamine/N-methylpyrrolidone/H2O mixture. Scanning electron microscope photographs of the images exhibited fine patterns (approximate to10 mum fine/space resolution) with 9-14 mum film thickness. The pattern-forming mechanism is based on the reaction development patterning (RDP) process, where the main pattern-forming reaction occurs during development.

  428. Photosensitive polyetherimide (Ultem) based on reaction development patterning (RDP) 査読有り

    T Fukushima, Y Kawakami, T Oyama, M Tomoi

    JOURNAL OF PHOTOPOLYMER SCIENCE AND TECHNOLOGY 15 (2) 191-196 2002年

    出版者・発行元:TECHNICAL ASSOC PHOTOPOLYMERS,JAPAN

    DOI: 10.2494/photopolymer.15.191  

    ISSN:0914-9244

    詳細を見る 詳細を閉じる

    Photosensitive polyetherimide (PEI) consisting of non-photosensitive PEI (Ultem((R))) and photosensitive diazonaphthoquinone (DNQ) compounds gave positive-tone behavior by UV irradiation, followed by development in solution including ethanolamine. The SEM of the resultant images showed fine patterns with 10-15 mum film thickness. GPC and H-1-NMR measurements that can give information on the structure of dissolved components in the irradiated region were carried out in order to clarify the mechanism of pattern formation. The imaging of photosensitive PEI is based on reaction development patterning (RDP), where the amine causes main-chain scission directly related to the pattern formation in development step to form low molecular weight amidized products.

  429. Ultrafast photoconductive swiches integrated with electrical waveguides of low-k polyimide 招待有り 査読有り

    S Yagi, T Itatani, H Kawanami, S Gorwadkar, T Uemura, T Fukushima, H Itatani, M Tomoi, M Tacano

    APPLICATIONS OF PHOTONIC TECHNOLOGY 5 4833 623-632 2002年

    出版者・発行元:SPIE-INT SOC OPTICAL ENGINEERING

    DOI: 10.1117/12.474331  

    ISSN:0277-786X

    詳細を見る 詳細を閉じる

    We have fabricated ultrafast electrical waveguides with low-k polyimide integrated with ultrafast photoconductive switches formed by nano-anodization process for the first time. Electrical signals are affected by nonlinear capacitance of p-n junctions in this waveguides, and pass through the low-k polyimide, so the dielectric loss and the radiation loss are dramatically reduced. The electrical pulses as short as 290 fs were measured on this waveguide by an electro-optic sampling system based on a femtosecond laser.

  430. Durable and refreshable polymeric N-halamine biocides containing 3-(4′-vinylbenzyl)-5,5-dimethylhydantoin 査読有り

    Takafumi Fukushima, Toshiyuki Oyama, Takao Iijima, Masao Tomoi, Hiroshi Itatani

    Journal of Polymer Science, Part A: Polymer Chemistry 39 (19) 3348-3355 2001年10月1日

    DOI: 10.1002/pola.1317  

    ISSN:0887-624X

    詳細を見る 詳細を閉じる

    A novel vinyl-hydantoin monomer, 3-(4′-vinylbenzyl)-5,5-dimethylhydantoin, was synthesized in a good yield and was fully characterized with Fourier transform infrared (FTIR) and 1H NMR spectra. Its homopolymer and copolymers with several common acrylic and vinyl monomers, such as vinyl acetate, acrylonitrile, and methyl methacrylate, were readily prepared under mild conditions. The polymers were characterized with FTIR and 1H NMR, and their thermal properties were analyzed with differential scanning calorimetry studies. The halogenated products of the corresponding copolymers exhibited potent antibacterial properties against Escherichia coli, and the antibacterial properties were durable and regenerable. The structure-property relationships of the polymers were further discussed.

  431. Photosensitive polycarbonates based on reaction development patterning (RDP) 査読有り

    T Oyama, Y Kawakami, T Fukushima, T Iijima, M Tomoi

    POLYMER BULLETIN 47 (2) 175-181 2001年10月

    出版者・発行元:SPRINGER-VERLAG

    DOI: 10.1007/s002890170009  

    ISSN:0170-0839

    詳細を見る 詳細を閉じる

    Films of commercially available poly(bisphenol A carbonate) (BPA-PC) and poly[bisphenol A carbonate-co-4,4'-(3,3,5-trimethylcyclohexylidene)diphenol carbonate] (BPA-TMC-PQ containing photosensitive agent (diazonaphthoquinone (DNQ) compound) were prepared by spin-coating onto copper foil. The obtained films showed positive-tone behavior by UV irradiation and following development with ethanolamine/N-methylpyrrolidone (NMP)/H2O mixture (1/1/1 by weight). The scanning electron microscope (SEM) photographs of the resulting images exhibited fine patterns (similar to 10 mum line/space resolution) with 15-16 mum film thickness. The pattern forming mechanism is based on the Reaction Development Patterning (RDP), in which the carboxylic acid resulting from photo-rearrangement of DNQ in the film attracts ethanolamine in the developer and the amine reacts with carbonate in the main chain to induce degradation of the polymer. RDP, where the main pattern forming reaction occurs during the development, is proved to be efficient for polycarbonates as well as polyimide.

  432. New concept of positive photosensitive polyimide: Reaction development patterning (RDP) 査読有り

    T Fukushima, T Oyama, T Iijima, M Tomoi, H Itatani

    JOURNAL OF POLYMER SCIENCE PART A-POLYMER CHEMISTRY 39 (19) 3451-3463 2001年10月

    出版者・発行元:JOHN WILEY & SONS INC

    DOI: 10.1002/pola.1327  

    ISSN:0887-624X

    詳細を見る 詳細を閉じる

    A soluble multiblock copolyimide without specific functional groups such as OH and COOH was prepared by a direct one-pot polycondensation of two types of dianhydrides and diamines in the presence of gamma -valerolactone/pyridine catalyst using N-methylpyrrolidone (NMP)/toluene mixture as a solvent. The polyimide film containing the photosensitive agent diazonaphthoquinone (DNQ) compound gave positive-tone behavior by UV irradiation, followed by development in a mixture of ethanolamine/NMP/H2O (1/1/1 by weight). The scanning electron microscopic photograph of the resultant image showed fine patterns with about 20 mum film thickness. Its pattern forming was based on the photorearrangement of diazonaphthoquinone, a process in which the ring-opening reaction of imide units of the polyimide with the amine used as a developer and the following degradation of the polymer are induced. Such a new imaging technique combines principles of photolithography and etching of a polyimide to give, what we call, reaction development patterning in which the main chemical reactions directly related to the pattern formation occur during development. (C) 2001 John Wiley & Sons, Inc.

  433. Synthesis and positive-imaging photosensitivity of soluble polyimides having pendant carboxyl groups 査読有り

    T Fukushima, K Hosokawa, T Oyama, T Iijima, M Tomoi, H Itatani

    JOURNAL OF POLYMER SCIENCE PART A-POLYMER CHEMISTRY 39 (6) 934-946 2001年3月

    出版者・発行元:JOHN WILEY & SONS INC

    DOI: 10.1002/1099-0518(20010315)39:6<934::AID-POLA1068>3.0.CO;2-T  

    ISSN:0887-624X

    詳細を見る 詳細を閉じる

    Polyimides having pendant; carboxyl groups were prepared by a direct one-pot polycondensation of 4,4'-(hexafluoroisopropylidene)diphthalic anhydride (6FDA) with 3,5-diaminobenzoic acid (DABz) and bis[4-(3-aminophenoxy)phenyl]sulfone (m-BAPS) in the presence of a gamma -valerolactone/pyridine catalyst system using N-methyl-2-pyrrolidone (NMP)/toluene mixture asa solvent at 180 degreesC. The obtained polyimides were soluble in dipolar aprotic solvents such as dimethylformamide, dimethyl sulfoxide, and NMP as well as in tetrahydrofuran and aqueous basic solution. The solubility of the polyimides was dependent on the diamine composition. Photosensitve polyimide (PSPI) systems composed of the polyimides and diazonaphthoquinone compound as a photosensitive material gave positive-tone behavior by UV irradiation, followed by development with aqueous tetramethylammonium hydroxide (TMAH) solution. The scanning electron microscopic photograph of the resulting image showed 10-mum line/space resolution with about 15 mum of film thickness. The PSPIs baked at 350 degreesC for a short time had excellent thermal resistance comparable to the original polyimides. (C) 2001 John Wiley & Sons, Inc.

  434. Positive photosensitive polyimide synthesized by block-copolymerization for KrF lithography 査読有り

    T Itatani, S Gorwadkar, T Fukushima, M Komuro, H Itatani, M Tomoi, T Sakamoto, S Matsumoto

    ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XVII, PTS 1 AND 2 3999 552-558 2000年

    出版者・発行元:SPIE-INT SOC OPTICAL ENGINEERING

    ISSN:0277-786X

    詳細を見る 詳細を閉じる

    We have developed photosensitive polyimides synthesized by block-copolymerization for KrF lithography. The polyimides were synthesized from aliphatic tetracarboxylic dianhydrides and aliphatic diamines. Aliphatic rings have been introduced to reduce absorption at 248 nm(KrF). We have obtained line patterns of 0.17 mu m at a dose of 170 mJ/cm(2), and line and space patterns of 0.25 mu m at a dose of 190 mJ/cm(2).

  435. Applications of newly developed positive photosensitive block co-polyimides to CSPs 査読有り

    S Matsumoto, XZ Jin, T Fukushima, M Miyamura, H Itatani

    PROCEEDINGS OF 3RD ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE 367-372 2000年

    出版者・発行元:IEEE

    詳細を見る 詳細を閉じる

    Meeting the challenging market-defined needs of CSPs (chip sized packages) industry requires a new substrate technology that provides higher I/O densities, higher performance, thinner and lighter packaging structures than previously available solutions. In this paper, the first applications to CSP interposer (CSP-IP) processes by newly developed positive photosensitive block co-polyimides (PPI), which P I R&D Co., Ltd. of Japan has commercialized recently, are discussed. Block co-polyimides are prepared in organic polar solvents by the sequential addition co-polymerization process in the presence of the binary catalyst, which has been described in US patents by the author. PPI polymer solutions are derived from block co-polyimides including photo-sensitizers. Advantages of newly developed PPIs from block co-polyimides are as follows; 1) no imidization process needs at high temperature, 2) PPIs have strong adhesive ability to Cu, Al and Si wafers, 3) thinner thickness polyimide films are available with high durability, 4) positive photo-pattern are available with high resolution, 5) PPIs are high temperature Tg materials. In CSP-IP packaging processes by PPI, it is shown that PPI&apos;s UV-lights resolution workability brings highly uniformed 20 microns diameter via hole, and also, highly uniformed solder bumps attached on the polyimides layers. PPI requires no imidization process after drying and curing in the processes, accordingly, the whole heat requirements in the CSP-IP processes are below 200 degreesC, which enables to CSP-IP the additional layers of lead I/O patterning between solder bumps interstice without any solder bump deformations, that provides higher I/O densities, size reductions to the new CSP-IP. PPI&apos;s pin-holeless performance using black masks processes brings CSP-IP production cost keeps very low-level, and it is possible to coat PPI polymer solution directly on silicon wafer easily and to produce the wafer CSP with high production yield, which keep this wafer CSP processes quite a competitive low cost. Thinner layered CSP-IP packages by PPI described above could be applied to the 3D-stacked CSP package features.

  436. Sub-micron Patterning of Positive Photo-sensitive Polyimide Synthesized by Block Copolymerization 査読有り

    T. Itatani, S. Gorwadkar, T. Fukushima, Y. Yamamoto, M. Maezawa, M. Komuro, T. Sakamoto, M. Tomoi, H. Itatani

    Proceedings of International Conference on Solid State Device and Materials (SSDM), 1999年9月

︎全件表示 ︎最初の5件までを表示

MISC 196

  1. PMMA被覆Auナノ粒子含有ブロック高分子の誘導自己組織化と三次元配線形成

    福島 誉史

    第70回高分子学会年次大会 1H09 2021年5月

  2. 多段階励起による発光現象を用いた光遺伝学用神経メッシュプローブの提案と作製

    長崎春樹, 浦山翔太, YANG Fen, 木野久志, 福島誉史, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 68th 2021年

  3. UV-LED内蔵ハイドロゲルフレキシブル基板を用いた殺菌絆創膏の作製と評価

    高橋則之, 煤孫祐樹, WANG Z., 小田島輩, 木野久志, 田中徹, 田中徹, 福島誉史, 福島誉史

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 68th 2021年

  4. Directed Self-Assembly based Interconnect Technology for Next-Generation 2D/3D LSI

    Takafumi Fukushima

    Impact 2020 (1) 6-8 2020年2月27日

    出版者・発行元:Science Impact, Ltd.

    DOI: 10.21820/23987073.2020.1.6  

    ISSN:2398-7073

    詳細を見る 詳細を閉じる

    Three-dimensional integrated circuits (3D ICs) contain multiple layers of active device chiplets and have the potential to improve signal transfer and the overall performance of a microelectronic systems, while saving energy. Dr Takafumi Fukushima is an Associate Professor based in the Department of Mechanical Systems Engineering, Tohoku University, Japan, whose research revolves around 3D/heterogeneous/flexibel integration technologies. Within the Department Fukushima focuses on self-assembly technologies. 'Self-assembly is the process by which an organised structure spontaneously forms from individual components, as a result of specific, local interactions among the components,' he explains. One of these is advanced DSA. This process enables ultrafine-pitch interconnect formation through the simple coating and heating of nanocomposites with block co-polymers and metal compounds/nanoparticles. 'DSA is a type of directed assembly which utilises the nano-phase separation of block co-polymers to create ultrafine lines, space and hole patterns, facilitating more accurate control of the feature shapes,' Fukushima outlines. 'Conventional DSA with the block co-polymers is an alternative way to photo-patterning with photoresists that are spin-on photosensitive materials to photolithographically form fine patterns and traditionally used in semiconductor industry.' Through his advanced DSA Fukushima is able to make both ultrafine patterns as well as form lateral and vertical interconnections with nanocomposites based on non-photolithographic methodology.

  5. RDL-First FOWLP技術を利用したハイドロゲルフレキシブル基板上への配線形成

    高橋則之, 煤孫祐樹, 木野久志, 田中徹, 田中徹, 福島誉史, 福島誉史

    電子情報通信学会論文誌 C(Web) J103-C (3) 2020年

    ISSN:1881-0217

  6. Fan-Out Wafer-Level Packagingによるフレキシブル経爪脈波センサの集積化

    小田島輩, 煤孫祐樹, QIAN Zhengyang, 高橋則之, 永田柊太, 木野久志, 田中徹, 田中徹, 福島誉史, 福島誉史

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 81st 2020年

  7. インモールドエレクトロニクス用フレキシブル三次元波状配線の作製

    永田柊太, 木野久志, 田中徹, 田中徹, 福島誉史, 福島誉史

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 81st 2020年

  8. SPECIAL REPORT (SEMICON Taiwan Special): Through Silicon Via Propels 3D Chip Integration 招待有り

    24-25 2019年9月

  9. 誘導自己組織化による極微細三次元配線形成技術

    福島誉史, 福島誉史, MURUGESAN Mariappan, 小柳光正

    電子情報通信学会技術研究報告 118 (438(SDM2018 91-97)) 2019年

    ISSN:0913-5685

  10. Multichip-to-Wafer三次元集積化基盤技術の開発(3)-異種機能集積化に向けたマイクロバンプ接合技術-

    三輪侑紀, LEE Sungho, LIANG Rui, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 66th 2019年

  11. Multichip-to-Wafer三次元集積化基盤技術の開発(1)-テンポラリ接着剤を用いた一括チップ薄化技術-

    LEE Sungho, LIANG Rui, 三輪侑紀, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 66th 2019年

  12. μLED埋め込み型フレキシブルオプト神経プローブの開発

    島智大, 煤孫裕樹, ZHANG Bowen, 浦山翔太, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 66th 2019年

  13. 高集積ストレッチャブルデバイス作製に資する基盤技術研究

    福島誉史

    村田学術振興財団年報 (33) 2019年

    ISSN:0919-3383

  14. チップ内蔵フレキシブル・ハイブリッド・エレクトロニクスの電気特性評価

    煤孫祐樹, ZHENGYANG Qian, 高橋則之, 木野久志, 田中徹, 田中徹, 福島誉史

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 66th 2019年

  15. ハイドロゲルを用いたフレキシブル・ハイブリッド・エレクトロニクス作製

    高橋則之, 煤孫祐樹, 木野久志, 田中徹, 田中徹, 福島誉史

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 66th 2019年

  16. TSVを用いた三次元集積技術によるAIチップの開発

    福島誉史, 福島誉史, 福島誉史

    半導体・集積回路技術シンポジウム(CD-ROM) 83rd 2019年

  17. RDL-first FOWLPによるハイドロゲル用いたFHEのためのチップ内蔵技術

    高橋則之, 煤孫祐樹, 木野久志, 田中徹, 田中徹, 福島誉史, 福島誉史

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 80th 2019年

  18. 光遺伝学用UCNPオプト神経プローブの発光強度特性評価

    浦山翔太, 木野久志, 福島誉史, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 80th 2019年

  19. 経爪型集積化光電容積脈波計測システムの開発-二階微分回路の設計と評価-

    SATAKE Filipe Alves, LEE Kar Mun, QIAN Zhengyang, 矢吹僚介, DU Bang, 福島奨, 木野久志, 福島誉史, 清山浩司, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 80th 2019年

  20. 高密度電極接続を用いた三次元集積のための低背マイクロバンプ接合評価

    三輪侑紀, LEE Sungho, LIANG Rui, 熊原宏征, 木野久志, 福島誉史, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 80th 2019年

  21. Multichip-to-Wafer三次元集積に向けたマイクロバンプ接合技術

    熊原宏征, 三輪侑紀, LEE Sungho, LIANG Rui, 木野久志, 福島誉史, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 80th 2019年

  22. 硬い単結晶半導体で創る曲面集積フレキシブルデバイス創製

    福島誉史

    天野工業技術研究所年次報告 2018 2019年

  23. ニューラルネットワーク向け相関二重サンプリング回路の開発

    清水郁也, 清山浩司, 木野久志, 福島誉史, 田中徹, 小柳光正

    電気・情報関係学会九州支部連合大会講演論文集(CD-ROM) 72nd 2019年

  24. 多段階励起による発光現象を用いた光遺伝学用神経プローブの作製

    浦山翔太, 島智大, ZHANG Bowen, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 66th 2019年

  25. 高集積フレキシブルデバイスシステム作製の技術基盤構築

    煤孫祐樹, 木野久志, 田中徹, 田中徹, 福島誉史

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 65th 2018年

  26. 経爪型集積化光電容積脈波計測システムの開発(2)-動脈血酸素飽和度(SpO<sub>2</sub>)の計測-

    矢吹僚介, QIAN Zhengyang, 竹澤好樹, 下川賢士, LEE Kar Mun, 木野久志, 福島誉史, 清山浩司, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 65th 2018年

  27. 三次元積層シリコン神経プローブアレイの開発(2)-低侵襲刺入を目的としたシャンク配置の検討-

    島智大, 原島卓也, ZHANG Bowen, 森川拓実, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 65th 2018年

  28. 経爪型集積化光電容積脈波計測システムの開発(1)-集積化PPG計測LSIの設計と評価-

    QIAN Zhengyang, 竹澤好樹, 下川賢士, 矢吹僚介, LEE Karmun, 木野久志, 福島誉史, 清山浩司, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 65th 2018年

  29. 真空支援スピン塗布型BCBライナー絶縁膜を用いたTSV形成技術

    李晟豪, 菅原陽平, 伊藤誠人, 木野久志, 福島誉史, 田中徹, 田中徹

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 32nd 2018年

    ISSN:1880-4616

  30. DRAMセルアレイを用いた3D-IC内部のCu汚染の高精度評価

    谷川星野, 福島誉史, 木野久志, 田中徹, 田中徹

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 32nd 2018年

    ISSN:1880-4616

  31. マルチウェル構造TSVを用いたTSV側壁界面評価方法の開発

    菅原陽平, 木野久志, 福島誉史, 田中徹, 田中徹

    電子情報通信学会論文誌 C(Web) J101-C (2) 2018年

    ISSN:1881-0217

  32. 高集積フレキシブルデバイスシステム作製のための応力緩衝層の評価

    煤孫祐樹, JACQUMOND Achille, JACQUMOND Achille, 高橋則之, 木野久志, 田中徹, 田中徹, 福島誉史

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 79th 2018年

  33. 経爪型集積化光電式SpO<sub>2</sub>計測システムの開発-回路の設計と評価-

    矢吹僚介, QIAN Zhengyang, LEE Kar Mun, BANG Du, 木野久志, 福島誉史, 清山浩司, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 79th 2018年

  34. 三次元集積化技術の現状と脳型情報処理システムへの応用

    小柳光正, 福島誉史

    光技術コンタクト 56 (10) 30-40 2018年

    ISSN:0913-7289

  35. 経爪型集積化光電容積脈波計測システムの開発-受光・計測回路の設計と評価-

    QIAN Zhengyang, 竹澤好樹, 下川賢士, 木野久志, 福島誉史, 清山浩司, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 78th 2017年

  36. 三次元積層人工網膜チップのためのラプラシアンエッジ強調機能を有する刺激電流生成回路の評価

    下川賢士, QIAN Zhengyang, 竹澤好樹, 木野久志, 福島誉史, 清山浩司, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 78th 2017年

  37. 矩形波インピーダンス計測のためのGIDL電流を用いた低周波リングオシレータの設計と評価

    竹澤好樹, 下川賢士, QIAN Zhengyang, 福島奨, 木野久志, 福島誉史, 清山浩司, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 78th 2017年

  38. 皮質層別刺激可能なシリコンオプト神経プローブの開発

    森川拓実, 原島卓也, ZHANG Bowen, 土居史弥, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 78th 2017年

  39. 生体信号計測・電気刺激のためのGIDL電流を用いたインピーダンス計測回路の評価

    清山浩司, 竹澤好樹, 下川賢士, 銭正ヨウ, 木野久志, 福島誉史, 田中徹

    電気・情報関係学会九州支部連合大会講演論文集(CD-ROM) 70th 2017年

  40. 三次元神経活動記録のための積層シリコン神経プローブアレイの開発

    原島卓也, 森川拓実, ZHANG Bowen, 土居史弥, 木野久志, 福島誉史, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 78th 2017年

  41. 特定深さの細胞のみ光刺激可能な光ファイバ埋め込みシリコンオプト神経プローブの開発

    森川拓実, 原島卓也, 木野久志, 福島誉史, 片山統裕, 虫明元, 田中徹

    日本生体医工学会大会プログラム・抄録集(Web) 56th (3) 191-191 2017年

    出版者・発行元:公益社団法人 日本生体医工学会

    詳細を見る 詳細を閉じる

    近年、脳科学研究の分野において光遺伝学が注目されている。光遺伝学は光感受性タンパク質を発現した細胞のみを刺激可能であり、発現させる光感受性タンパク質を変えることで細胞の興奮と抑制を制御することができる。一方、脳神経の電気活動記録に用いられるツールの一つであるシリコン神経プローブは、微細な記録電極を高密度に形成することができ、脳神経活動を多点かつ精密に記録することが可能である。このシリコン神経プローブ上に光刺激機能を実装することで、光感受性タンパク質を発現させた細胞を光刺激し、同時に神経プローブ上の記録電極で神経活動を記録することが可能である。これまで、光ファイバをプローブのシャンク部上面に接着した光刺激機能を有する神経プローブが報告されている。しかし、接着された光ファイバによって、刺入時の脳細胞の損傷が増大する恐れがある。我々は細胞損傷を抑制しながら脳に刺入して光刺激できる神経プローブの実現を目指し、光ファイバ埋め込みシリコンオプト神経プローブの開発を行った。神経プローブのシャンク部に溝を形成し、光ファイバを埋め込むことで脳内に刺入する際の損傷を低減できる。また、溝端部に斜め加工を施すことでプローブ刺入方向と垂直に光を照射でき、特定の深さの細胞のみに光刺激を行うことが可能である。この新しい神経プローブは光遺伝学を用いた脳機能解明において有用なツールの一つとして使用可能である。

  42. 三次元神経活動記録のための積層尖鋭化シリコン神経プローブアレイの開発

    原島卓也, 森川拓実, 木野久志, 福島誉史, 片山統裕, 虫明元, 田中徹

    日本生体医工学会大会プログラム・抄録集(Web) 56th (3) 189-189 2017年

    出版者・発行元:公益社団法人 日本生体医工学会

    詳細を見る 詳細を閉じる

    &lt;p&gt;神経回路網の研究では三次元的に高密度で配置された記録電極を有する神経プローブを用いた神経活動の解析が有効である。これまでに三次元的に記録点を配置した神経プローブはいくつか報告されているが、電極密度や加工精度に限界がある。今回、我々は三次元神経活動記録のための積層尖鋭化シリコン神経プローブアレイについて報告する。このシリコン神経プローブアレイは4本のシャンクを有する3つの単層プローブを2つのスペーサを用いて熱圧着で積層したもので、12本のシャンクと三次元的に配置された156の記録電極を有している。脳刺入による細胞損傷を低減させるために、積層後のSiの異方性エッチングによってシャンクの断面形状を四角形から三角形にして断面積を減らし、刺入後の脳への圧迫を低減している。また、シャンク先端を尖らせることで刺入に必要な力や脳の変形も同様に低減している。本神経プローブアレイは半導体微細加工技術を用いて作製しているため、高い電極密度と位置合わせ精度を実現している。試作した積層尖鋭化シリコン神経プローブアレイの刺入特性を評価したところ、尖鋭化していないものに比べて優れた刺入特性を示すことを確認した。積層尖鋭化シリコン神経プローブアレイは三次元的に高密度で配置された記録電極と優れた刺入特性を有しており、神経回路網の解明や神経生理学の発展に大きく寄与するものである。&lt;/p&gt;

  43. Heterogeneous Integration with High-Performance and Scalable Substrates: Si-IF (Interconnect Fabric) and FlexTrateTM

    T. Fukushima, A. Bajwa, S.S.Iyer

    Advancing Microelectronics Magazine Mar./Apr. 2017年

  44. 『健康的に見える外見に着目した取り組み』~統合失調症患者に対する立位姿勢・歩行へのアプローチ~

    坂井孝行, 東将洋, 山井亨, 上村真紀, 福島翔, 尾林誉史, 佐田美佐子, 岡崎祐士

    九州精神神経学会・九州精神医療学会プログラム・抄録集 69th-62nd 2016年

  45. シリコンウエハの表面処理 半導体ウエハへの三次元配線加工:TSVと狭ピッチ電極を中心に

    福島誉史, 福島誉史, 福島誉史, LEE Kang-Wook, 田中徹, 田中徹, 小柳光正

    表面技術 67 (8) 414-420 2016年

    DOI: 10.4139/sfj.67.414  

    ISSN:0915-1869

  46. 高集積フレキシブルSiデバイス作製技術の開発

    福島誉史

    立石科学技術振興財団助成研究成果集 (24) 2015年

    ISSN:0918-9939

  47. 気相堆積重合ポリイミドを用いたTSVライナー形成

    福島誉史, MARIAPPAN Murugesan, BEA Ji-Ceol, LEE Kang-Wook, 小柳光正

    電子情報通信学会技術研究報告 113 (451(SDM2013 165-173)) 2014年

    ISSN:0913-5685

  48. 3D IC用ビアラスト・バックサイドビアプロセスにおけるプラズマダメージのMOSFET特性への影響評価

    菅原陽平, 橋口日出登, 谷川星野, 木野久志, 福島誉史, LEE K.-W., 小柳光正, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 75th 2014年

  49. 三次元集積化におけるTSV作製プロセスがトランジスタ特性に及ぼす影響評価

    菅原陽平, 谷川星野, 橋口日出登, 木野久志, 福島誉史, LEE Kangwook, 小柳光正, 田中徹

    電気学会全国大会講演論文集(CD-ROM) 2014 2014年

  50. 高解像網膜下刺激人工網膜モジュールの開発

    木暮爾, 笹木悠一郎, 長沼秀樹, 渡辺洋太, 木野久志, 福島誉史, LEE Kangwook, 小柳光正, 田中徹, 田中徹

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 60th 2013年

  51. 光電子集積三次元LSIのための高効率光カップラの作製

    乗木暁博, LEE K.-W, BEA J.-C., 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 60th 2013年

  52. 自己組織化静電仮接合を用いたC2W三次元集積化技術

    橋口日出登, 福島誉史, BEA J., MURUGESAN Mariappan, 木野久志, LEE K.-W., 田中徹, 田中徹, 小柳光正

    応用物理学会春季学術講演会講演予稿集(CD-ROM) 60th 2013年

  53. 室温硬化型樹脂による3D IC内の機械応力低減に関する検討

    木野久志, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 74th 2013年

  54. C2W三次元集積のための自己組織化静電仮接合の評価

    橋口日出登, 福島誉史, BEA J.-C., 木野久志, LEE K.-W., 田中徹, 田中徹, 小柳光正

    応用物理学会秋季学術講演会講演予稿集(CD-ROM) 74th 2013年

  55. 三次元LSIとヘテロインテグレーション

    LEE K-W., 福島誉史, 田中徹, 小柳光正

    半導体・集積回路技術シンポジウム講演論文集 77th 2013年

  56. 機能性液体を用いた自己組織化チップ実装技術

    伊藤有香, 伊藤有香, 福島誉史, 李康旭, 長木浩司, 田中徹, 田中徹, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 27th 2013年

    ISSN:1880-4616

  57. 自己組織化静電吸着技術を利用した三次元チップ積層

    橋口日出登, 福島誉史, はい志哲, 木野久志, 李康旭, 田中徹, 田中徹, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 27th 2013年

    ISSN:1880-4616

  58. 三次元集積化技術の動向と実用化に向けた課題

    李 康旭, 福島 誉史, 田中 徹, 小柳 光正

    電子情報通信学会技術研究報告. ICD, 集積回路 112 (324) 15-22 2012年11月20日

    出版者・発行元:一般社団法人電子情報通信学会

    ISSN:0913-5685

    詳細を見る 詳細を閉じる

    これまで,LSIは,半導体素子の微細化により,著しい速度で高性能化,大容量化が達成されてきた.しかし,消費電力の増大や特性ばらつきの増加などにより微細化が次第に難しくなってきている.これらの問題を解決するためには,素子の微細化だけでなく,LSIに実装技術やMEMS技術,フォトニクス技術などの異種技術を融合して,システム全体で高性能化,高機能化をはかる新しい集積化技術が必要となる.したがって,今後のLSI開発は,素子の微細化を更に進めるMore Moore技術と,異種技術を融合するMore than Moore技術を車の両輪のようにうまく協調,共存させながら進めていくことが重要になる.本報告では,More than Moore技術を代表する技術の一つである3次元集積化技術について,現状の課題と将来の可能性について言及する.

  59. 風力発電機出力平滑化用エネルギー貯蔵装置の定格決定に関する検討

    黒瀬誉史, 高橋理音, 田村淳二, 福島知之, 坂原淳史, 新谷宏治

    電気学会論文誌 B 132 (2) 2012年

    ISSN:0385-4213

  60. 24×24ピクセルを有する網膜下刺激人工網膜モジュールの開発

    渡辺慶朋, 長沼秀樹, 木暮爾, 笹木悠一郎, 清山浩司, 清山浩司, 福島誉史, LEE Kangwook, 小柳光正, 田中徹, 田中徹

    応用物理学関係連合講演会講演予稿集(CD-ROM) 59th 2012年

  61. 高信頼性Cu-TSVのための応力低減層の開発

    橋口日出登, MURGESAN Mariappan, 福島誉史, LEE K., 田中徹, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集(CD-ROM) 59th 2012年

  62. チッププロセスによる積層チップ形成

    朴澤一幸, 花岡裕子, 青木真由, 武田健一, LEE K.W., 福島誉史, 小柳光正

    応用物理学会学術講演会講演予稿集(CD-ROM) 73rd 2012年

  63. 光電子集積三次元LSIのための高効率光カップラの検討

    乗木暁博, LEE K.-W, BEA J.-C., 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集(CD-ROM) 73rd 2012年

  64. 三次元リコンフィギャラブルスピンプロセッサ用金属マイクロバンプ接合技術の開発

    木野久志, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 73rd 2012年

  65. 接着界面の濡れ性を制御した3D IC用チップ/ウェーハ転写技術

    大原悠希, LEE K., 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集(CD-ROM) 59th 2012年

  66. 和文論文誌C 特集号 「高密度実装を牽引する材料技術とヘテロインテグレーション」編集幹事(特集号編集委員会)

    福島誉史

    電子情報通信学会, エレクトロニクスソサエティNEWS LETTER 150 19-19 2012年

  67. Cu-TSV/Cu-Snマイクロバンプを有する薄ウェハのストレス評価

    マリヤッパン ムルゲサン, 福島 誉史, 田中 徹, 小柳 光正

    電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 110 (408) 43-47 2011年1月31日

    出版者・発行元:一般社団法人電子情報通信学会

    ISSN:0913-5685

    詳細を見る 詳細を閉じる

    マイクロバンプとTSVインターコネクションにより薄いLSIウェハで発生したストレスをマイクロラマン分光による詳細な分析を行った。(i)大型バンプでは、より深部までストレスが伝播する。(ii)バンプ間隔がより小さい場合、ストレスはより広範囲に伝播する。(iii) Cu-TSVに囲まれたSi内で大きな圧縮ストレスに続いて引張ストレスが継続される。

  68. 脳深部刺激のための刺激電極付きシリコン神経プローブの開発

    菅野壮一郎, 小林吏悟, LEE S., 雪田嘉穂, LEE K., 福島誉史, 片山統裕, 虫明元, 小柳光正, 田中徹

    応用物理学関係連合講演会講演予稿集(CD-ROM) 58th 2011年

  69. 3次元積層による薄化LSIチップの変形と応力分布の解析

    木野久志, MURUGESAN Mariappan, BEA Jichel, LEE Kangwook, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学関係連合講演会講演予稿集(CD-ROM) 58th 2011年

  70. 高集積微細デバイスにおける今後の信号伝達/配線技術:シリコン貫通光インターコネクション(TSPV)を用いた光電子三次元集積化技術

    福島誉史, 乗木暁博, 田中徹, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集(CD-ROM) 58th 2011年

  71. 眼球内完全埋込型人工網膜用ピラー型刺激電極アレイの開発

    竹下博隆, 渡辺慶朋, 乗木暁博, LEE Kangwook, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学関係連合講演会講演予稿集(CD-ROM) 58th 2011年

  72. 光・電気刺激に対する網膜応答記録用フレキシブルケーブル電極の作製

    木暮爾, 渡辺慶朋, 笹木悠一郎, LEE Kangwook, 福島誉史, 小柳光正, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 72nd 2011年

  73. 脳深部刺激用シリコン神経プローブの刺激電極材料評価

    雪田嘉穂, LEE S., 菅野壮一郎, LEE K., 福島誉史, 小柳光正, 片山統裕, 虫明元, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 72nd 2011年

  74. 電極間クロストークを抑制した人工網膜用ピラー型刺激電極アレイの開発

    渡辺慶朋, 木暮爾, LEE Kangwook, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 72nd 2011年

  75. 光電子集積三次元LSIに用いるシリコン貫通光配線のFDTD解析

    乗木暁博, LEE K.-W, BEA J.-C., 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集(CD-ROM) 72nd 2011年

  76. 三次元積層時の局所応力がMOSFETの特性に与える影響

    木野久志, MURUGESAN Mariappan, BEA Jichel, LEE Kangwook, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 72nd 2011年

  77. 三次元集積のための高精度チップ位置合わせと常温直接接合技術

    岩田永司, 福島誉史, LEE K.-W., 田中徹, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集(CD-ROM) 58th 2011年

  78. 狭ピッチ金属マイクロバンプを有するチップの自己組織化実装技術

    福島誉史, 岩田永司, 李康旭, 田中徹, 田中徹, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集(CD-ROM) 25th 2011年

    ISSN:1880-4616

  79. 三次元光・電子融合集積化技術

    李 康旭, 乗木 暁博, 清山 浩司, 福島 誉史, 田中 徹, 小柳 光正

    電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 109 (408) 21-24 2010年1月22日

    出版者・発行元:一般社団法人電子情報通信学会

    ISSN:0913-5685

    詳細を見る 詳細を閉じる

    三次元光・電子融合集積化技術を提案した。三次元光・電子融合システムを実現する為、セルフアセンブリによるチップ積層、乗越え配線およびチップ間の光接続を用いたLSI、MEMSや光デバイスを統合する技術を開発した。三次元光・電子融合集積化技術を用いて、複数のLSI、MEMSや光デバイスにより構成される三次元光・電子融合マルチチップモジュールを作製した。デジタル振幅変調LSI、LCフィルタ、MEMS圧カセンサチップが搭載された電気通信用インターポーザとVCSELやフォトダイオードが埋め込まれた光通信用インターポーザの接合によって、三次元光・電子融合マルチチップモジュールが製作された。光および電子デバイスは各々のTSVを介して通信が行われる。光デバイス間は光通信用インターポーザに作製された導波路を用いて接続される。三次元光・電子融合マルチチップモジュールに搭載されたLSL、MEMSおよび光デバイスの機能動作に初めて成功した。

  80. 三次元集積化技術の課題と展望

    小柳光正, 福島誉史, LEE Kang-Wook, 田中徹

    電子情報通信学会技術研究報告 109 (412(SDM2009 182-192)) 2010年

    ISSN:0913-5685

  81. 三次元積層型人工網膜チップのための三次元積層技術の開発

    海法克享, 大原悠希, 清山浩司, LEE K., 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学関係連合講演会講演予稿集(CD-ROM) 57th 2010年

  82. 三次元集積回路のための高密度Cu/Snマイクロバンプ形成技術

    大原悠希, 乗木暁博, MURUGESAN Mariappan, 岩田永司, 開達郎, LEE K.-W., BEA J.-C., 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集(CD-ROM) 57th 2010年

  83. メタルナノドットメモリの電荷保持特性に関する研究

    開達郎, PEI Yanli, 小島俊哉, BEA Ji Cheol, 木野久志, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学関係連合講演会講演予稿集(CD-ROM) 57th 2010年

  84. スピン回路を用いたリコンフィギュラブルプロセッサに関する基礎検討

    清山浩司, 清山浩司, 福島誉史, 小柳光正, 田中徹

    電気関係学会九州支部連合大会講演論文集(CD-ROM) 63rd 2010年

  85. 縦型メタルナノドット不揮発性メモリに関する研究

    開達郎, 栗山祐介, 小島俊哉, MURUGESAN Mariappan, PEI Yanli, 木野久志, BEA Ji Cheol, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 71st 2010年

  86. LSI積層による曲げ応力がデバイス特性に与える影響に関する研究

    木野久志, 開達郎, 栗山祐介, MURUGESAN Mariappan, BEA Jichel, LEE Kangwook, 福島誉史, 小柳光正, 田中徹, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 71st 2010年

  87. ファインピッチ金属マイクロバンプを有するチップの自己組織化積層

    岩田永司, 福島誉史, LEE Kang-Wook, 小柳光正, 田中徹, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 71st 2010年

  88. 金属マイクロバンプ接合を介した自己組織化チップ積層

    岩田永司, 福島誉史, LEE K.-W., 田中徹, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集(CD-ROM) 57th 2010年

  89. 風力発電機出力平滑化用エネルギー貯蔵装置の定格決定に関する検討

    黒瀬誉史, 高橋理音, 田村淳二, 福島知之, 笹野栄一, 坂原淳史, 新谷宏治

    電気学会回転機研究会資料 RM-10 (134-152) 2010年

  90. 光導波路付きシリコン神経プローブの開発

    小林吏悟, LEE S., 菅野壮一郎, 酒井誠一郎, LEE K., 福島誉史, 片山統裕, 虫明元, 八尾寛, 小柳光正, 田中徹, 田中徹

    応用物理学関係連合講演会講演予稿集(CD-ROM) 57th ROMBUNNO.17P-ZD-15 2010年

  91. 神経細胞の高精度光刺激のための光導波路付きシリコン神経プローブの開発

    小林吏悟, LEE S., 菅野壮一郎, 酒井誠一郎, LEE K., 福島誉史, 石塚徹, 虫明元, 八尾寛, 小柳光正, 田中徹

    応用物理学会学術講演会講演予稿集(CD-ROM) 71st ROMBUNNO.16A-ZW-24 2010年

  92. 電子回路・実装の注目製品・技術 3次元積層型集積回路に向けた自己組織化チップ実装技術

    福島誉史, LEE Kang Wook, 田中徹, 小柳光正

    電子材料 49 (6) 17-24 2010年

    ISSN:0387-0774

  93. in-vivo神経細胞活動記録用両面電極付きSiプローブの開発

    LEE S., 小林吏悟, 管野壮一郎, 福島誉史, 坂本一寛, 松坂義哉, 片山統裕, 虫明元, 田中徹, 田中徹, 小柳光正, 小柳光正

    応用物理学関係連合講演会講演予稿集 56th (3) 2009年

  94. 神経細胞活動のin vivo記録用Si両面プローブの開発

    LEE S., 小林吏悟, 菅野壮一郎, 福島誉史, 坂本一寛, 松坂義哉, 片山統裕, 虫明元, 小柳光正, 田中徹, 田中徹

    日本生体医工学会大会プログラム・論文集(CD-ROM) 48th 2009年

  95. メタルナノドットメモリの電荷保持特性に関する研究

    開達郎, PEI Yanli, 小島俊哉, BEA Ji Cheol, 木野久志, 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 70th (2) 2009年

  96. 周波数変動を考慮した風力発電機出力平滑化用エネルギー貯蔵装置の設計に関する基礎検討

    黒瀬誉史, 高橋理音, 田村淳二, 福島知之, 笹野栄一, 新谷宏治

    電気・情報関係学会北海道支部連合大会講演論文集(CD-ROM) 2009 2009年

  97. 窒化膜スペーサによる縦型MOSFETの寄生容量低減に関する研究

    木野久志, 開達郎, BEA J.C., 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 70th (2) 2009年

  98. 眼球内完全埋め込み型人工網膜のためのピラー型刺激電極の開発

    竹下博隆, 海法克享, LEE K.-W., 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 70th (3) 2009年

  99. 自己組織化による三次元LSIチップの高精度位置合わせ技術

    岩田永司, 福島誉史, 田中徹, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 70th (2) 2009年

  100. マイクロ流路付き両面シリコン神経プローブの開発

    菅野壮一郎, 小林吏悟, LEE S., LEE K., 福島誉史, 坂本一寛, 松坂義哉, 片山統裕, 虫明元, 小柳光正, 田中徹, 田中徹

    応用物理学会学術講演会講演予稿集 70th (3) 2009年

  101. 実装技術とそれを支える周辺機器 自己組織化によるウェハレベル三次元集積化技術

    福島誉史, 小柳光正, 田中徹

    M & E 36 (1) 123-125 2009年

    ISSN:0286-1550

  102. Characterization of metal nanodots nonvolatile memory (シリコン材料・デバイス)

    裴 艶麗, 西嶋 雅彦, 福島 誉史, 田中 徹, 小柳 光正

    電子情報通信学会技術研究報告 108 (80) 83-88 2008年6月9日

    出版者・発行元:一般社団法人電子情報通信学会

    ISSN:0913-5685

    詳細を見る 詳細を閉じる

    SAND(Self-Assembled Nanodot Deposition)法を用いて、絶縁膜中に高密度の金属ナノドットが埋め込まれた金属ナノドット膜を形成した。金属としてタングステン、絶縁膜としてシリコン酸化膜とシリコン窒化膜を用いた。TEMやXPSの物性分析によって、金属ナノドットの熱安定性と化学組成を評価し、シリコン窒化膜中ではタングステンナノドット(W-ND)の酸化が抑制されていることを明らかにした。さらに、W-ND膜を用いたMOSキャパシタを試作し、ナノドットへの電子注入・放出、電荷保持特性を評価した。W-NDをシリコン酸化膜中に埋め込んだMOSキャパシタの短い電荷保持時間に対して、W-NDをシリコン窒化膜に埋め込んだMOSキャパシタでは約10年の電荷保持が可能である。前者ではW-NDが酸化されることにより、捕獲される電子のエネルギー状態が変わり、電荷保持時間が短くなっていると考えられる。金属ナノドット不揮発性メモリの実現には、金属ナノドットが酸化されない絶縁膜を採用することが重要である。

  103. MEMS-半導体横方向配線技術 II:配線基板へのMEMSチップのセルフアセンブリ

    今野隆行, 福島誉史, 菊池宏和, 佐藤圭悟, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (2) 2008年

  104. 三次元LSI技術を用いた人工視覚と脳埋め込み電極

    小柳光正, 福島誉史, 田中徹

    応用物理学関係連合講演会講演予稿集 55th 2008年

  105. 自己組織化ウェーハ張り合わせによる三次元集積化技術

    福島誉史, 田中徹, 小柳光正

    電子情報通信学会技術研究報告 107 (481(SDM2007 263-272)) 2008年

    ISSN:0913-5685

  106. MEMS-半導体横方向配線技術 IV:インプリント技術を用いたマイクロバンプ形成

    菊池宏和, 山田裕介, 福島誉史, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (2) 2008年

  107. 高密度記録のためのSi両面電極の開発

    小林吏悟, 佐藤圭悟, 小宮謙, 管野壮一郎, 福島誉史, 坂本一寛, 田中徹, 片山統裕, 虫明元, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (3) 2008年

  108. FM/I/Nano-Dot FM構造でのスピン電子の磁気トンネル効果

    BEA JiChel, BEA JiChel, MURUGESAN M., MURUGESAN M., YIN ChengKuan, 福島誉史, 田中徹, 寒川誠二, 河野省三, 佐道泰造, 宮尾正信, 名取研二, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (2) 2008年

  109. MEMS-半導体横方向配線技術 V:高透磁率膜上に形成したインダクタの基本特性

    木野久志, YIN C.K., JEON W.C, 小宮謙, 清山浩司, 福島誉史, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (2) 2008年

  110. シリコン窒化膜中に埋め込んだタングステンナノドットフローティングゲートMOSキャパシタのメモリ特性

    PEI Y, 福島誉史, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (2) 2008年

  111. キャビティ構造を有するMEMSチップのセルフアセンブリ

    今野隆行, 小林吏悟, 福島誉史, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 69th (2) 2008年

  112. 三次元LSIを搭載した光インターポーザのためのテーパTSVの形成

    乗木暁博, 藤原誠, 藤原誠, 福島誉史, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 69th (3) 2008年

  113. 直接接合法を用いたマイクロ流路付Siプローブの開発

    菅野壮一郎, 小林吏悟, 福島誉史, 坂本一寛, 片山統裕, 虫明元, 田中徹, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 69th (3) 2008年

  114. High-k絶縁膜を有するタングステンナノドットフローティングゲートMOSキャパシタのメモリ特性

    PEI Y., 西嶋雅彦, 福島誉史, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 69th (2) 2008年

  115. MEMS-半導体横方向配線技術I:フレキシブル基板へのLSIチップのセルフアセンブリ

    福島誉史, 今野隆行, 田中徹, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (2) 2008年

  116. 眼球内撮像型人工網膜システムで用いるTiN刺激電極のインピーダンス特性

    佐藤圭悟, 小宮謙, 小林貴史, 小林吏悟, 福島誉史, 富田浩史, 菅野江里子, 栗野浩之, 田中徹, 玉井信, 小柳光正

    日本生体医工学会大会プログラム・論文集(CD-ROM) 47th ROMBUNNO.PS2-6-11 2008年

  117. 眼球内人工網膜チップへの電力供給用2次コイルの開発

    小宮謙, 佐藤圭吾, 小林貴史, 小林吏悟, 海法克享, 福島誉史, 富田浩史, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (3) 1360 2008年

  118. 無線通信による出力電流調整可能な人工網膜チップの設計

    小林貴史, 小宮謙, 佐藤圭悟, 清山浩司, 福島誉史, 富田浩史, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (3) 1359 2008年

  119. 3次元積層型人工網膜チップ実装のためのフレキシブル基板上におけるマイクロバンプ形成

    佐藤圭悟, 小宮謙, 小林貴史, 小林吏悟, 福島誉史, 富田浩史, 栗野浩之, 田中徹, 小柳光正, 小柳光正

    応用物理学関係連合講演会講演予稿集 55th (3) 1360 2008年

  120. Tungsten Through-Si Via (TSV) Technology for Three-Dimensional LSIs

    KIKUCHI Hirokazu, YAMADA Yusuke, ALI Atif Mossad, LIANG Jun, FUKUSHIMA Takafumi, TANAKA Tetsu, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2007 482-483 2007年9月19日

  121. Memory Window Enhancement of MOS Memory Devices with High Density Self-Assembled Tungsten Nano-dot

    PEI Yanli, FUKUSHIMA Takafumi, TANAKA Tetsu, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2007 242-243 2007年9月19日

  122. New Reconfigurable Memory Architecture for Parallel Image Processing LSI with Three-Dimensional Structure

    KODAMA Shigeo, AMANO Daijiro, SUGIMURA Takeaki, FUKUSHIMA Takafumi, TANAKA Tetsu, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2007 1064-1065 2007年9月19日

  123. Development of Power Supply System for Three-Dimensionally Staked Retinal Prosthesis Chip

    KOMIYA Ken, KOBAYASHI Risato, KOBAYASHI Takafumi, SATO Keigo, FUKUSHIMA Takafumi, TOMITA Hiroshi, KURINO Hiroyuki, TANAKA Tetsu, TAMAI Makoto, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2007 658-659 2007年9月19日

  124. VCSEL のインターコネクションへの応用

    小柳光正, 福島誉史, 田中徹, 藤原誠

    O Plus E (特集:VCSELの最先端技術と応用, そして将来展望) 29 (4) 348-352 2007年4月

    出版者・発行元:新技術コミュニケーションズ

  125. 金属ナノドットフローティングゲートMOSキャパシタのメモリ特性

    PEI Y., 福島誉史, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 68th (2) 2007年

  126. 3次元実装技術とスーパーチップインテグレーション

    田中徹, 福島誉史, 小柳光正

    電子情報通信学会技術研究報告 106 (467(CPM2006 129-154)) 2007年

    ISSN:0913-5685

  127. VCSELの最先端技術と応用,そして将来展望 VCSELのインターコネクションへの応用

    小柳光正, 福島誉史, 田中徹, 藤原誠, 藤原誠

    O plus E (329) 2007年

    ISSN:0911-5943

  128. 三次元集積化のための高アスペクト比シリコンエッチング技術の開発

    菊池宏和, 山田裕介, 福島誉史, 田中徹, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集 21st 2007年

    ISSN:1880-4616

  129. 3次元積層型LSIチップを用いた人工視覚システム

    田中徹, 福島誉史, 小柳光正

    日本生体医工学会大会プログラム・論文集(CD-ROM) 46th 2007年

  130. Investigation of FePt Nano-Dots Fabricated by Self-Assembled Nano-Dot Deposition Method Using X-ray Photoelectron Spectroscopy

    M. Murugesan, J. C. Bea, C-K. Yin, H. Nohira, E. Ikenaga, T. Hattori, M. Nishijima, T. Fukushima, T. Tanaka, M.Miyao, M. Koyanagi

    Extended abstracts of the ... Conference on Solid State Devices and Materials CDROM 1026-1027 2007年

  131. 積層型人工網膜チップへの電力供給方法の開発-ショットキーバリアダイオードの設計と試作-

    小宮謙, 渡部泰一郎, 小林貴史, 小林吏悟, 福島誉史, LI H. G., 富田浩史, 菅野江里子, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学関係連合講演会講演予稿集 54th (3) 1376 2007年

  132. 人工網膜システム用可変バイアス電圧生成回路の設計

    小林貴史, 小宮謙, 渡部泰一郎, 福島誉史, LI H. G., 富田浩史, 菅野江里子, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学関係連合講演会講演予稿集 54th (3) 1375 2007年

  133. 人工網膜用データ受信回路の試作と評価

    小林貴史, 小宮謙, 佐藤圭悟, 福島誉史, 富田浩史, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学会学術講演会講演予稿集 68th (3) 1307 2007年

  134. 網膜刺激電極のインピーダンス特性に対する電極材料および寸法の影響

    佐藤圭悟, 小宮謙, 小林貴史, 小林吏悟, 福島誉史, 富田浩史, 栗野浩之, 田中徹, 小柳光正, 小柳光正

    応用物理学会学術講演会講演予稿集 68th (3) 1308 2007年

  135. 三次元積層型人工網膜チップへの電力供給用2次コイルの開発

    小宮謙, 小林貴史, 佐藤圭吾, 小林吏悟, 福島誉史, 富田浩史, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学会学術講演会講演予稿集 68th (3) 1308 2007年

  136. 三次元集積回路技術を用いた並列画像処理のための再構成可能な積層型メモリシステムの設計

    天野 大二朗, 杉村 武昭, 小西 雄太, 福島 誉史, 田中 徹, 小柳 光正

    情報処理学会研究報告システムLSI設計技術(SLDM) 2006 (111) 147-152 2006年10月27日

    出版者・発行元:一般社団法人情報処理学会

    ISSN:0919-6072

    詳細を見る 詳細を閉じる

    ロボットビジョンのような視覚情報処理においてはビデオレポートを大幅に超える実時間高速画像処理システムが必要とされる。このような画像処理システムとして、これまでにイメージセンサ、メモリ、処理回路を積層した三次元積層型並列画像処理システムが提案されている。このシステムではイメージセンサから得られた画像は分割され、処理回路と1対1で結合された複数のメモリに格納される。そして、処理回路により並列に画像処理を行う。しかし、演算対象の画素だけではなく、その近傍の画像データを用いるフィルタリングのような処理では、分割画像間の境界部分のデータのロード・ストアが複雑になっている。これは演算対象の分割画像を格納するメモリだけでなく、近傍の画像を格納するメモリへのアクセスが必要となるからである。そこで、メモリ構成を動的に再構成することによって、分割画像間の境界を自由に移動することが可能なメモリシステムの設計を行った。提案するメモリシステムを用いることで対象画素の演算の際に近傍のメモリにアクセスする必要がなくなり、実行サイクル数が減少して、従来よりも高速に画像処理が可能である。提案したメモリシステムをFPGAに実装し画像処理の動作を確認した。The real-time image processing system with a frame rate beyond video rate is required for the high-speed visual information processing which is employed in the robot vision and moving target tracking. So far the parallel image processing system using a three-dimensional integrated circuit was proposed. This system has several layers where the image sensor circuit, the memory circuit, and the processing circuit are incorporated into the respective layers. In this system, the image data captured by the image sensor is divided into many units and stored in the memories. The stored image data is processed in parallel by the processing circuit. However, it becomes difficult to perform the processing operation such as filtering which needs the data processing beyond the boundary between the divided image units. In the filtering operation, we use not only the pixel data of target unit but also the peripheral pixel data in the neighboring units. Therefore, it is needed to access both memories of the target unit and the neighboring units. In order to overcome such difficulties in memory access, we proposed a novel memory system using three-dimensional LSI technology. In this system, the image can be easily divided into many image units without any restrictions by dynamically changing the memory configuration. This system does not need to access the pixel memories of the neighboring units as a result of dynamically changing the memory configuration. Consequently, the number of execution cycles is decreased, and the image data processing with higher speed compared with the previous system is possible. We implenmented this memory system on FPGA and confirmed the basic operations for the image processing.

  137. 三次元集積回路を用いた並列画像処理システムのためのばらつき補正回路を有する並列AD変換器の設計

    小西 雄太, 杉村 武昭, 天野 大二朗, 福島 誉史, 田中 徹, 小柳 光正

    情報処理学会研究報告システムLSI設計技術(SLDM) 2006 (111) 153-158 2006年10月27日

    出版者・発行元:一般社団法人情報処理学会

    ISSN:0919-6072

    詳細を見る 詳細を閉じる

    近年、ロボット技術の発展により高速で高性能の画像処理システムの開発が望まれている。三次元集積回路を用いた画像処理システムは、配線長の短縮による高速化、低消費電力化、並列化のしやすさなどの利点からこのような高速、高性能の画像処理システムへの応用が期待されている。この画像処理システムでは、入力画像をいくつかのブロックに分割し、ブロックごとにAD変換器、メモリ、画像処理PEを割り当てる。この構成により平列数を任意に増やすことが出来るため、高速での画像処理を行うことが可能になる。その一方で、並列AD変換器の変換特性のばらつきにより並列ブロック間で出力画像がばらつくという問題が生じる。本研究では、AD変換器の変換特性を処理回路で抽出し、各AD変換器にフィードバックすることでばらつきを除去するシステムを提案する。また、同様に処理回路からの命令によってプログラマブルにAD変換を行うシステムについて提案する。Recently, the demand for high-speed and high-performance robot-vision system increases with the progress of the robot technology. The image processing system using three-dimensional integration technology is expected to dramatically improve the perfomance of robot-vision system because it has advantages of high speed operation due to shortening of wiring length, low power consumption and parallel processing capability. In this system, input image is divided into many parallel image blocks. A/D converter, frame memory, and image processing element are allocated to one image block. We can increase the number of parallel blocks if it is necessary. This system achieves high speed image processing by employing a highly parallel processing with the three-dimensionally stacked structure. On the other hand, there is problem that the quality of output image is seriously degraded by the variations of conversion characteristics in parallel A/D converters which are distributed to many image blocks. Then we propose the new parallel image processing system to improve the quality of output image by minimizing the variations of conversion characteristics of the A/D converters using the respective processing elements. We also propose the system to execute programmable A/D conversion according to the instructions of processing elements.

  138. New Magnetic Nano-Dot Memory with FePt Nano-Dots

    YIN Cheng-Kuan, BEA Ji-Chel, MURUGESAN Mariappan, OOGANE Mikihiko, FUKUSHIMA Takafumi, TANAKA Tetsu, NATORI Kenji, MIYAO Masanobu, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2006 994-995 2006年9月13日

  139. Low Power Spin-Transfer MRAM Writing Scheme with Selective Word Line Bootstrap

    SUGIMURA Takeaki, SAKAGUCHI Takeshi, AMANO Daijiro, FUKUSHIMA Takafumi, TANAKA Tetsu, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2006 602-603 2006年9月13日

  140. Sub-Atmospheric Chemical Vapor Deposition Process for Chip-to-Wafer 3-Dimensional Integration

    KIKUCHI Hirokazu, YAMADA Yusuke, ALI Atif Mossad, FUKUSHIMA Takafumi, TANAKA Tetsu, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2006 490-491 2006年9月13日

  141. Evaluation of Electrical Stimulus Current to Retina Cells for Retinal Prosthesis by Using Platinum-Black (Pt-b) Stimulus Electrode Array

    WATANABE Taiichiro, KOMIYA Ken, KOBAYASHI Takafumi, KOBAYASHI Risato, FUKUSHIMA Takafumi, TOMITA Hiroshi, SUGANO Eriko, SATO Manami, KURINO Hiroyuki, TANAKA Tetsu, TAMAI Makoto, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2006 890-891 2006年9月13日

  142. ウェーハレベル三次元集積化技術の開発

    福島誉史, 山田祐介, 菊池宏和, 田中徹, 小柳光正

    エレクトロニクス実装学会講演大会講演論文集 20th 2006年

    ISSN:1880-4616

  143. 脳深部解析のためのSi製測定探針の開発

    小林吏悟, 渡部泰一郎, 坂本一寛, 片山統裕, 本波啓太, 出口淳, 小宮謙, 福島誉史, 栗野浩之, 田中徹, 虫明元, 小柳光正

    応用物理学関係連合講演会講演予稿集 53rd (3) 2006年

  144. 神経細胞同時多点計測のためのSi微小探針アレイの開発

    小林吏悟, 渡部泰一郎, 小宮謙, 福島誉史, 坂本一寛, 栗野浩之, 田中徹, 片山統裕, 虫明元, 小柳光正

    応用物理学会学術講演会講演予稿集 67th (3) 2006年

  145. 3次元集積化技術とリコンフィギャラブル3D-SoC

    小柳光正, 杉村武昭, 福島誉史, 田中徹

    電子情報通信学会技術研究報告 106 (49(RECONF2006 1-10)) 2006年

    ISSN:0913-5685

  146. 三次元集積回路技術を用いた並列画像処理のための再構成可能な積層型メモリシステムの設計

    天野大二朗, 杉村武昭, 小西雄太, 福島誉史, 田中徹, 小柳光正

    電子情報通信学会技術研究報告 106 (317(ICD2006 127-142)) 2006年

    ISSN:0913-5685

  147. チップ-ウェーハ張り合わせによる三次元LSI作製技術

    福島誉史, 山田裕介, 菊池宏和, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 67th (2) 2006年

  148. In-situアニールによる自己組織化FePt磁気ナノドットの形成

    YIN C. K., BEA J. C., BEA J. C., CHOI H., CHOI H., 西嶋雅彦, 福島誉史, 田中徹, 名取研二, 宮尾正信, 小柳光正

    応用物理学関係連合講演会講演予稿集 53rd (1) 2006年

  149. 三次元集積回路を用いた並列画像処理システムのためのばらつき補正回路を有する並列AD変換器の設計

    小西雄太, 杉村武昭, 天野大二朗, 福島誉史, 田中徹, 小柳光正

    電子情報通信学会技術研究報告 106 (317(ICD2006 127-142)) 2006年

    ISSN:0913-5685

  150. 三次元集積化のための高ステップカバレージ絶縁膜の形成

    菊池宏和, 山田裕介, 福島誉史, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 67th (2) 2006年

  151. ノルボルネン樹脂光導波路を用いた光電気複合基板の開発

    藤原誠, 藤原誠, 白土洋次, 尾張洋史, 渡辺啓, 松山睦宏, 高浜啓造, 森哲也, 宮尾憲治, 長木浩司, 福島誉史, 田中徹, 小柳光正

    応用物理学会学術講演会講演予稿集 67th (3) 2006年

  152. 積層型人工網膜に用いるPt刺激電極のin-vivo評価

    渡部泰一郎, 本波啓太, 出口淳, 小林吏悟, 小宮謙, 福島誉史, 富田浩史, 菅野江里子, 佐藤まなみ, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学関係連合講演会講演予稿集 53rd (3) 1381 2006年

  153. 積層型人工網膜チップ用基本回路の改良

    小林貴史, 出口淳, 渡部泰一郎, 小宮謙, 小林吏悟, 福島誉史, LI H., 富田浩史, 菅野江里子, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学会学術講演会講演予稿集 67th (3) 1187 2006年

  154. 眼球内埋め込み型人工網膜システムへの電力供給方法の開発

    小宮謙, 渡部泰一郎, 小林吏悟, 小林貴史, 福島誉史, LI H., 富田浩史, 菅野江里子, 栗野浩之, 田中徹, 玉井信, 小柳光正, 小柳光正

    応用物理学会学術講演会講演予稿集 67th (3) 1188 2006年

  155. 視覚にせまる最先端技術 三次元集積化人工網膜デバイス

    小柳光正, 福島誉史, 田中徹, 富田浩史

    光アライアンス 17 (11) 16-21 2006年

    ISSN:0917-026X

  156. Evaluation of Electrical Stimulus Current to Retina Cells for Retinal Prosthesis

    MOTONAMI Keita, WATANABER Taiichiro, DEGUCHI Jun, FUKUSHIMA Takafumi, TOMITA Hiroshi, SUGANO Eriko, SATO Manami, KURINO Hiroyuki, TAMAI Makoto, KOYANAGI Mitsumasa

    Extended abstracts of the ... Conference on Solid State Devices and Materials 2005 464-465 2005年9月13日

  157. マルチチップボンディング技術を用いた脳インプラント集積化デバイスの開発

    渡部泰一郎, 小林吏悟, 坂本一寛, 本波啓太, 小宮謙, 出口淳, 福島誉史, 虫明元, 栗野浩之, 小柳光正

    応用物理学会学術講演会講演予稿集 66th (3) 2005年

  158. チップ間光インターコネクションを有するSRAMメモリモジュールの試作

    栗原宏文, 二藤部隆太郎, 福島誉史, 栗野浩之, 小柳光正

    応用物理学関係連合講演会講演予稿集 52nd (3) 2005年

  159. 基板バイアス電圧制御プリアンプを用いたMRAMの低消費電力読み出し手法

    杉村武昭, 出口淳, CHOI H., 坂口武史, OH H., 福島誉史, 小柳光正

    応用物理学会学術講演会講演予稿集 66th (2) 2005年

  160. FePt磁気ナノドットの不揮発性メモリへの適用

    YIN Cheng-Kuan, BEA JiChel, HONG YounGi, 坂口武史, OH Hyuck-Jae, 福島誉史, 栗野浩之, 名取研二, 宮尾正信

    応用物理学関係連合講演会講演予稿集 52nd (3) 2005年

  161. チップ・ウェーハ張り合わせによる三次元集積化技術

    菊池宏和, 木島均, 大石壮一郎, 山田裕介, 福島誉史, 栗野浩之, 小柳光正

    応用物理学関係連合講演会講演予稿集 52nd (2) 2005年

  162. 犠牲サイドウォール手法による極薄SOI MOSFETの作製

    坂口武史, OH Hyuckjae, BEA Jicheol, SHIM JeoungChill, 福島誉史, 栗野浩之, 小柳光正

    応用物理学関係連合講演会講演予稿集 52nd (2) 2005年

  163. 動き検出・エッジ検出同時処理可能なCMOSイメージセンサの開発

    辻孝司, 出口淳, 杉村武昭, 福島誉史, 小柳光正

    映像情報メディア学会技術報告 29 (61(IST2005 74-80)) 2005年

    ISSN:1342-6893

  164. 三次元集積化技術のための高アスペクト比エッチング技術の開発

    菊池宏和, 山田裕介, 福島誉史, 小柳光正

    応用物理学会学術講演会講演予稿集 66th (1) 2005年

  165. 配線長分布を用いた三次元集積回路の総配線長・最大配線長の評価

    出口淳, 中谷好博, 杉村武昭, 福島誉史, 小柳光正

    応用物理学会学術講演会講演予稿集 66th (2) 2005年

  166. チップ間光インターコネクションのためのビームリード電極を用いたVCSEL実装技術

    栗原宏文, 福島誉史, 小柳光正

    応用物理学会学術講演会講演予稿集 66th (3) 2005年

  167. 積層型人工眼システム用刺激電極ケーブルのin-vivo評価

    本波啓太, 渡部泰一郎, 出口淳, 福島誉史, 菅野江里子, 佐藤まなみ, 富田浩史, 栗野浩之, 玉井信

    応用物理学関係連合講演会講演予稿集 52nd (3) 1465 2005年

  168. 眼内埋め込み用積層型人工網膜のための刺激パルス電流のin-vivo評価

    本波啓太, 渡部泰一郎, 出口淳, 福島誉史, 富田浩史, 菅野江里子, 佐藤まなみ, 栗野浩之, 玉井信, 小柳光正

    応用物理学会学術講演会講演予稿集 66th (3) 1138 2005年

  169. 三次元集積回路のための層間絶縁膜を貫通する高アスペクトホールの形成

    菊池宏和, 山田裕介, 福島誉史, 栗野浩之, 小柳光正

    電子情報通信学会大会講演論文集 2004 2004年

    ISSN:1349-1369

  170. 活動電位の同時多点計測のための集積化神経インプラントの開発

    渡部泰一郎, 本波啓太, 坂本一寛, 出口淳, 福島誉史, SHIM J C, 虫明元, 栗野浩之, 小柳光正

    応用物理学会学術講演会講演予稿集 65th (3) 2004年

  171. Ultimate Functional Multi-Electrode System (UFMES) Based on Multi-Chip Bonding Technique

    Taiichiro Watanabe, Keita Motonami, Kazuhiro Sakamoto, Jun Deguchi, Takafumi Fukushima

    Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials 2004年

  172. 錐状刺激電極を有する人工眼システムに関する研究

    本波啓太, 渡部泰一郎, 出口淳, 福島誉史, 富田浩史, SHIM J-C, 玉井信, 栗野浩之, 小柳光正

    応用物理学会学術講演会講演予稿集 65th (3) 1146 2004年

  173. ポリイミドを組み込んだ超高速非線形伝送線路

    八木修一, 板谷太郎, 川浪仁志, GORWADKAR S, 上村貴之, 福島誉史, 板谷博, 友井正男, 鷹野致和

    明星大学理工学部研究紀要 (39) 2003年

    ISSN:1346-7239

  174. 反応現像型感光性エンプラ ポリマー構造と感光特性との関連

    大山俊幸, 川上由紀子, 喜多村明, 福島誉史, 友井正男

    高分子学会予稿集 52 (12) 2003年

  175. 反応現像型感光性含フッ素ポリイミド

    川上由紀子, 福島誉史, 大山俊幸, 友井正男

    高分子学会予稿集 52 (4) 2003年

  176. low-kポリイミドを組み込んだ伝送線路のネットワークアナライザーによる評価

    八木修一, 板谷太郎, 川浪仁志, GORWADKAR S, 上村貴之, 福島誉史, 板谷博, 友井正男, 鷹野致和

    応用物理学関係連合講演会講演予稿集 50th (3) 2003年

  177. 反応現像型感光性ポリアリレート:ポリマー構造と感光特性の関連

    喜多村明, 福島誉史, 大山俊幸, 友井正男

    高分子学会予稿集 52 (4) 2003年

  178. Positive Photosensitive Polyimides Based on Novel Imaging Principle: Reaction Development Patterning (RDP)

    T. Fukushima, T. Oyama, M. Tomoi

    POLYIMIDE & HIGH PERFORMANCE POLYMERES: STEPI 6 229-238 2002年12月

  179. エンプラを感光性ポリマーに変える新原理:反応現像画像形成法

    大山俊幸, 福島誉史, 友井正男

    マテリアルステージ 2 (4) 90-96 2002年4月

    出版者・発行元:技術情報協会

    ISSN:1346-3926

  180. 光導電スイッチと集積化されたIow-kポリイミドを取り入れた超高速伝送線路

    八木修一, 板谷太郎, 川浪仁志, GORWADKAR S, 上村貴之, 福島誉史, 板谷博, 友井正男, 鷹野致和

    応用物理学関係連合講演会講演予稿集 49th (3) 2002年

  181. 反応現像型感光性ポリアリレート

    大山俊幸, 喜多村明, 福島誉史, 飯島孝雄, 友井正男

    高分子学会予稿集 51 (4) 2002年

  182. イオン結合型ネガ型感光性ポリイミドの開発

    福島誉史, 大山俊幸, 友井正男

    高分子学会予稿集 51 (12) 2002年

  183. 反応現像型感光性エンジニアリングプラスチック

    大山俊幸, 川上由紀子, 喜多村明, 福島誉史, 友井正男

    高分子学会予稿集 51 (12) 2002年

  184. 反応現像型感光性ポリカーボネート

    大山俊幸, 川上由紀子, 福島誉史, 飯島孝雄, 友井正男

    高分子学会予稿集 51 (4) 2002年

  185. 反応現像型感光性ポリエーテルイミド

    大山俊幸, 川上由紀子, 福島誉史, 飯島孝雄, 友井正男

    高分子学会予稿集 51 (4) 2002年

  186. イオン結合型ネガ型感光性ポリイミドの開発

    福島誉史, 大山俊幸, 飯島孝雄, 友井正男

    高分子学会予稿集 51 (4) 160-163 2002年

  187. 光機能性高分子材料の最新動向 反応現像型フォトレジスト

    福島誉史, 大山俊幸, 友井正男

    機能材料 22 (5) 24-33 2002年

    ISSN:0286-4835

  188. 感光性ポリイミドの新しいコンセプト 反応現像画像形成(RDP)原理

    福島誉史, 大山俊幸, 飯島孝雄, 友井正男

    ポリマー材料フォーラム講演要旨集 10th 2001年

  189. 感光性ポリイミドの新しいコンセプト 反応現像画像形成原理

    福島誉史, 友井正男

    高分子加工 50 (12) 553-560 2001年

    ISSN:0023-2564

  190. ポジ型感光性ブロック共重合ポリイミドのCSP-IPへの適用

    松本俊一, 板谷博, 金行洲, 福島誉史, 上村貴之, 友井正男

    エレクトロニクス実装学術講演大会講演論文集 14th 2000年

    ISSN:1346-2199

  191. ポジ型感光性ブロック共重合ポリイミドのレジスト特性

    福島誉史, 大山俊幸, 飯島孝雄, 友井正男, 板谷博

    高分子学会予稿集 49 (4) 2000年

  192. ポジ型感光性ブロック共重合ポリイミドのリソグラフィー特性

    福島誉史, 大山俊幸, 飯島孝雄, 友井正男, 板谷博

    ポリマー材料フォーラム講演要旨集 9th 2000年

  193. ペンダントフェノール性水酸基含有ポリイミドの合成とフォトレジストへの応用

    早川光太郎, 福島誉史, 大山俊彦, 飯島孝雄, 友井正男, 板谷博

    高分子学会予稿集 49 (10) 2000年

  194. ブロック共重合法によるポジ型感光性ポリイミドによる0.4μmパターニング

    板谷太郎, GORWADKAR S, 山本芳久, 福島誉史, 古室昌徳, 坂本統徳, 板谷博

    応用物理学会学術講演会講演予稿集 60th (2) 1999年

  195. ポジ型感光性ポリイミドの開発

    福島誉史, 細川勝元, 飯島孝雄, 友井正男, 板谷博

    エレクトロニクス実装学術講演大会講演論文集 13th 1999年

    ISSN:1346-2199

  196. ポジ型感光性ポリイミドの開発

    細川勝元, 福島誉史, 飯島孝雄, 友井正男, 板谷博

    高分子学会予稿集 47 (10) 1998年

︎全件表示 ︎最初の5件までを表示

書籍等出版物 8

  1. ポリイミドの高機能設計と応用技術

    技術情報協会

    技術情報協会 2022年8月

    ISBN: 9784861048876

  2. マイクロLEDディスプレイ ~市場と要素技術の開発動向~

    福島誉史

    Science & Technology 2021年8月

  3. Flexible, Wearable, and Stretchable Electronics 1st Edition (Editor: Katsuyuki Sakuma)

    CRC Press 2020年11月

  4. 次世代ディスプレイの応用に向けた材料、プロセス技術の開発動向

    福島誉史

    技術情報協会 2020年2月

  5. 3D Integration in VLSI Circuits: Implementation Technologies and Application (Editor: Katsuyuki Sakuma)

    CRC Press 2018年4月

  6. Handbook of 3D Integration – Volume 3: 3D Process Technology (Editors: Phil Garrou, Mitsumasa Koyanagi, Peter Ramm)

    Wiley-VCH 2014年6月

  7. 3D Integration for VLSI Systems

    Pan Stanford Publishing 2011年5月

  8. MEMS/NEMS工学大全

    福島誉史

    テクノシステム 2009年4月22日

︎全件表示 ︎最初の5件までを表示

講演・口頭発表等 98

  1. <ECTC2023での発表を解説> 先端半導体パッケージング・実装技術の研究開発動向 ~チップレット・RDLインターポーザ・Siブリッジ・FOWLPに加え、50件のハイブリッド接合技術を紹介~ 招待有り

    福島 誉史

    サイエンス&テクノロジー主催セミナー 2023年9月14日

  2. 先端半導体パッケージングの技術トレンド: IEDMやECTCで発表されたハイブリッド接合やチップレットインテグレーション技術を中心に、3D-IC/TSVからFOWLPまで ~材料を含めた個別プロセスを詳細に解説~ 招待有り

    福島 誉史

    情報機構主催セミナー 2023年7月27日

  3. 短TATを実現する3D-ICのラピッドプロトタイピングと最新技術 招待有り

    Fukushima Takafumi

    くまもと3D連携コンソーシアム 第2回オープンセミナー 2023年7月27日

  4. 三次元実装/TSVおよび先端半導体パッケージの最新製造技術・信頼性解析技術と研究開発動向 招待有り

    福島誉史

    R&D支援センター主催セミナー 2023年5月19日

  5. 3D Super Chip Concept to Build a New Era of Chiplet and Heterogeneous Integration 招待有り

    Takafumi Fukushima

    ICEP (International Conference on Electronics Packaging) 2023年4月21日

  6. 進化する三次元実装・集積化技術 招待有り

    福島誉史

    第37回ネプコン ジャパン(エレクトロニクス開発・実装展)最先端のロジックおよびパワーデバイスの3D実装技術: ISP-2 半導体・センサ パッケージング展 専門セミナー② 2023年1月

  7. 先端半導体パッケージングの技術トレンドと今後の方向性、課題 招待有り

    福島誉史

    情報機構主催セミナー 2022年10月25日

  8. <ECTC2022での発表を解説>先端半導体パッケージング・実装技術の研究開発動向 招待有り

    福島誉史

    Science & Technology主催セミナー 2022年9月27日

  9. 先端半導体パッケージングの技術トレンド: 3D-IC/チップレットからFOWLP、FHEまで ~材料を含めた個別プロセスを詳細に解説~ 招待有り

    福島誉史

    情報機構主催のセミナー 2022年7月28日

  10. In-mold Flexible Hybrid Electronics (iFHE) Based on Holistic System Integration with FOWLP, 3D-IC/TSV, and Chiplets 招待有り

    福島誉史

    the 20th International Symposium on the Physics of Semiconductors and Applications (ISPSA 2022) 2022年7月17日

  11. 半導体産業のこれからを担う3D-IC実装技術の現状と課題、アカデミアからの提案 招待有り

    福島誉史

    一般社団法人日本電子回路工業会(JPCA)が主催するJPCA Show 2022などを含む「電子機器トータルソリューション展2022」(東京ビッグサイト)一般社団法人エレクトロニクス実装学会(JIEP)主催 JIEP最先端実装技術シンポジウム 2022年6月17日

  12. 新たな実装技術で創るフレキシブルデバイス”インモールド・フレキシブル・ハイブリッド・エレクトロニクス(iFHE) 招待有り

    福島誉史

    一般社団法人日本電子回路工業会(JPCA)が主催するJPCA Show 2022などを含む「電子機器トータルソリューション展2022」(東京ビッグサイト) 2022年6月16日

  13. 三次元実装/ TSV および 先端半導体パッケージの最新製造技術/信頼性解析技術と研究開発動向 招待有り

    福島誉史

    R&D支援センター主催のセミナー 2022年4月26日

  14. 東北大学GINTIの取り組みとダイレベル&マルチチップ・ツー・ウエハ三次元集積 招待有り

    福島誉史

    第112回ミニマル3DICファブ開発研究会コア・オープン会議 2022年3月29日

  15. 先端半導体パッケージング技術と最新動向: ~FOWLP, 3D-IC/TSV, 各種インターポーザ, チップレット, Si Bridge等で多様化する実装形態の進化について~ 招待有り

    福島誉史

    サイエンス&テクノロジー主催セミナー 2022年3月18日

  16. 東北大発3D-IC 試作製造拠点GINTI の取り組みと多様化する先端半導体パッケージングの動向 招待有り

    福島誉史

    日本実装技術振興協会主催 第213 回定例講演会『先端半導体後工程(More than Moore)技術』 2022年3月17日

  17. 三次元実装/TSVを基盤としたヘテロインテグレーション技術の研究開発動向 招待有り

    福島誉史

    電子情報通信学会総合大会 企画講演セッション「電子デバイスの性能を最大限に引き出す高周波・高出力実装技術」 2022年3月16日

  18. 先端3DIC半導体パッケージの最新技術と開発状況(先端3DIC半導體封裝最新技術與開發動向) 招待有り

    福島誉史

    三建産情(台湾)主催の公開セミナー(台湾身分証明書所有者限定) 2022年2月17日

  19. 先端半導体パッケージング技術で創るインモールド・フレキシブル・ハイブリッド・エレクトロニクス(iFHE) 招待有り

    福島誉史

    エレクトロニクス実装学会(JIEP) 電子部品・実装技術委員会 プリンタブルデバイス研究会主催 2022年2月16日

  20. 半導体事業を牽引する3D実装の技術動向とホリスティック実装工学の歩み 招待有り

    福島誉史

    よこはま高度実装技術コンソーシアム(YJC)主催 第52回YJC実装技術セミナー 2021年12月8日

  21. 3D-IC/TSVの最新動向と自己組織化による三次元実装/ヘテロ集積 招待有り

    福島誉史

    公益社団法⼈化学⼯学会 エレクトロニクス部会主催 2021先端技術シンポジウム: 次世代半導体の展望 〜原理と⽣産技術〜 2021年12月7日

  22. 半導体パッケージング技術の最新動向: FOWLP, 3D-IC/TSV, チップレットが融合する実装形態の進化について 招待有り

    福島誉史

    トリケップス主催セミナー 2021年11月25日

  23. 未来の産業を担う三次元積層半導体(3D-IC)の現況と今後の展開 ―東北大学3D-IC研究開発拠点「GINTI」の活動成果よりー 招待有り

    福島誉史

    未来科学オープンセミナー 2021年11月19日

  24. iFHE: In-Mold Flexible Hybrid Electronics Using Fan-Out Wafer-Level Packaging with Chiplets 招待有り

    Takafumi Fukushima

    2021 Materials Research Society Taiwan International Conference (MRSTIC)

  25. 300mmウエハを用いた三次元積層型半導体チップ試作製造拠点GINTIの取り組みと研究開発動向 招待有り

    福島誉史

    第33回マイクロエレクトロニクス研究会 2021年11月13日

  26. インモールド・フレキシブル・ハイブリッド・エレクトロニクス(FHE)と医療応用 招待有り

    福島誉史

    NEDIA 第8回 電子デバイスフォーラム京都(2021) 2021年10月29日

  27. In-Mold Flexible Hybrid Electronics (FHE) Based on Advanced Wafer-Level Packaging with Chiplets 招待有り

    Takafumi Fukushima

    34th International Microprocesses and Nanotechnology Conference (MNC 2021) 2021年10月28日

  28. ECTC2021を解説: 先端半導体パッケージの開発動向と材料・プロセス技術” 招待有り

    福島誉史

    サイエンス&テクノロジー主催セミナー 2021年10月12日

  29. Heterogeneous, 3D, and Flexible System Integration Technology Based on Chiplet-on-Wafer Assembly 招待有り

    福島誉史

    一般社団法人電子実装工学研究所(IMSI) 接合界面創成技術研究会(LTB 研究会) 2021年9月16日

  30. 自己組織化実装によるチップレットのアセンブリとインターコネクト~基礎から応用、最近の3D-IC/FOWLP/VCSEL・μLEDの集積化まで~ 招待有り

    福島誉史

    サイエンス&テクノロジー主催セミナー 2021年8月5日

  31. ホリスティック・システム・インテグレーションに向けた三次元実装の技術動向と課題 招待有り

    福島誉史

    エレクトロニクス実装学会(JIEP)主催 先端ファブリケーション研究会 第8回公開研究会 2021年7月28日

  32. 先端半導体のパッケージング技術: FOWLPから3D-IC/TSV、チップレット、FHEやμLEDまで ~半導体後工程最大の国際会議ECTCを中心に個別プロセスや材料を詳細解説~ 招待有り

    福島誉史

    情報機構主催セミナー 2021年7月20日

  33. Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE 招待有り

    Takafumi Fukushima

    The 2021 Symposia on VLSI Technology and Circuits, Technology / Circuits Joint Focus Session 2021年6月17日

  34. 自己組織化実装とマイクロLEDディスプレイへの応用 招待有り

    福島誉史

    技術情報協会主催マイクロLEDディスプレイの実装、製造技術と市場動向に関するセミナー 2021年5月25日

  35. 三次元実装/TSVおよび先端半導体パッケージの最新技術と研究開発動向 招待有り

    福島誉史

    R&D支援センター主催セミナー 2021年4月22日

  36. 先端半導体パッケージのキーテクノロジーと研究動向 ―国際会議ECTCの発表を中心にTSV,Cu/Cu接合,FOWLP,チップレット, FHE, μLED, 自己組織化実装まで― 招待有り

    福島誉史

    サイエンス&テクノロジー主催セミナー 2021年2月25日

  37. Flexible In-Mold Electronics: Advanced FHE Technologies and Applications 招待有り

    Takafumi Fukushima

    2021FLEX 2021年2月24日

  38. Thin Film Deposition, Characterization, and Application of Polyimides by Vapor-Phase Polymerization 招待有り

    Takafumi Fukushima

    Webinar on Polymer Science and Chemistry (LongDom Conferences) 2020年11月8日

  39. Multilithic 3D and Heterogeneous Integration Using Capillary Self-Assembly 招待有り

    Takafumi Fukushima

    ”, 4th IEEE Electron Devices Technology and Manufacturing Conference (EDTM)

  40. Multichip-to-Wafer 3D Integration Technology 招待有り

    Takafumi Fukushima

    2020 International Conference on Electronics Packaging (ICEP 2020)

  41. Self-Assembly Based 3D Integration: Capillary Self-Assembly and Directed Self-Assembly 招待有り

    Takafumi Fukushima

    Huawei Workshop in 3D-IC 2019年11月22日

  42. FOWLP-based Flexible Hybrid Sensor Systems with Dieletsand 3D-IC 招待有り

    Takafumi Fukushima

    The 18th International Symposium on Microelectronics and Packaging and 21st International Conference on Electronic Materials and Packaging (ISMP-EMAP 2019) 2019年11月15日

  43. 誘導自己組織化配線を用いた三次元積層型集積回路の高性能化(Performance Scaling of 3D Integration with DSA Technology) 招待有り

    福島誉史

    日本学術振興会「先端ナノデバイス・材料テクノロジー第151委員会」 平成31年度第4回研究会「機能性デバイスの三次元化とその展開」 2019年11月15日

  44. New Flexible Hybrid Electronics Technologies for Biomedical Application 招待有り

    Takafumi Fukushima

    EMN Meeting on Flexible Electronics 2019年10月22日

  45. 三次元集積技術を用いたAIチップの開発 招待有り

    福島誉史

    電気化学会電子材料委員会, 第83回半導体・集積路技術シンポジウム 2019年8月28日

  46. 自己組織化実装の基礎原理と応用: FOWLPから、FHE、マイクロLEDディスプレイまで 招待有り

    福島誉史

    技術情報協会セミナー 2019年7月26日

  47. New Flexible Hybrid Electronics (FHE) Using Advanced Wafer-Level Packaging Technology 招待有り

    Takafumi Fukushima

    ”, International Congress on Advanced Materials Sciences and Engineering 2019 (AMSE-2019) 2019年7月22日

  48. 誘導自己組織化による極微細三次元配線形成技術 招待有り

    福島誉史

    応用物理学会・シリコンテクノロジー分科会多層配線委員会および電子情報通信学会・シリコン材料・デバイス研究会(SDM) 「配線・実装技術と関連材料技術」研究会 2019年2月7日

  49. 先端三次元積層LSIから高集積FHEへの展開 招待有り

    福島誉史

    日本学術振興会産学協力研究委員会 情報科学用有機材料 学振142委員会 2018年11月15日

  50. 三次元実装とフレキシブルハイブリッドエレクトロニクスに(FHE)向けた取り組み 招待有り

    福島誉史

    , 第155回有機エレクトロニクス研究センター講演会 2018年9月27日

  51. Moor’s Law for Packaging 招待有り

    Takafumi Fukushima, S. S. Iyer

    The 2018 International Conference on Solid-State Devices and Materials (SSDM) 2018年9月12日

  52. Capillary Self-Assembly Based Multichip-to-Wafer System Integration Technologies 招待有り

    Takafumi Fukushima

    The annual International Conference on Manipulation, Automation and Robotics at Small Scales (MARSS) 2018年7月6日

  53. 人工知能チップの開発に向けた自己組織化ヘテロ集積技術 招待有り

    福島誉史

    東北大学NICHe戦略セミナーシリーズ(第3回)『考える』イメージ・センサーの将来 2018年7月5日

  54. テンポラリー接合を用いたマルチリシック集積化技術 招待有り

    福島誉史

    日本学術振興会産学協力研究委員会 接合界面創成技術 第191委員会 2018年3月23日

  55. 自己組織化TSV/3次元実装と高集積フレキシブル・ハイブリッド・エレクトロニクス(FHE)技術 招待有り

    福島誉史

    第189回高密度実装技術部会 定例会 2018年3月15日

  56. SOG/a-Si:Hを用いたテンポラリー接合技術, FOWLPを応用した高集積フレキシブルデバイス基板「FlexTrateTM」 招待有り

    福島誉史

    第37回IEEE CPMT Society Japan Chapter イブニングミーティング37th IEEE CPMT Society Japan Chapter Evening Meeting 2017年10月6日

  57. FlexTrateTM Characterization 国際会議 招待有り

    福島 誉史

    Flex2017 2017年7月20日

  58. Directed Self-Assembly Patterning for 3D LSI 国際会議 招待有り

    福島 誉史

    INC (International Nanotechnology Conference on Communication and Cooperation) Global Conference and Workshops 2017年5月10日

  59. FlexTrate™: High Interconnect Density Fan-Out Wafer Level Processing for Flexible Bio-compatible Electronics 招待有り

    Takafumi Fukushima

    ”, NBMC (Nano-Bio Manufacturing Consortium) Workshop: Blood, Sweat and Tears III 2016年11月6日

  60. Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration 招待有り

    Takafumi Fukushima

    ”, The 230th ECS Meeting: PRiME (Pacific Rim Meeting) 2016年10月5日

  61. シリコン貫通配線(TSV)と三次元集積化技術の研究開発動向 招待有り

    福島誉史

    第32回センサ・マイクロマシンと応用システム」シンポジウム 2015年10月28日

  62. 高分子材料を用いた三次元集積技術 招待有り

    福島誉史

    第41回 よこはま高度実装技術コンソーシアム(YJC)実装技術セミナー 2015年6月11日

  63. Die-to-Wafer Self-Assembly by Droplet Surface Tension for 3D LSI & Advanced System Integration 招待有り

    Takafumi Fukushima

    EMN Meeting on Droplets 2015年5月15日

  64. 3D/TSV技術と最近の動向 招待有り

    福島誉史

    日本学術振興会 結晶加工と評価技術 第145委員会 2014年12月18日

  65. HETEROGENEOUS 3D INTEGRATION FOR INTERNET OF THINGS 招待有り

    Takafumi Fukushima

    2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2014) 2014年11月30日

  66. 気相堆積重合ポリイミドを用いたTSVライナー形成 招待有り

    福島誉史

    応用物理学会シリコンテクノロジー分科会 第169回 配線技術研究集会 2014年2月28日

  67. 研究施設の被害と教訓、復興への展望 招待有り

    福島誉史

    第37回YJC実装技術セミナー 2013年6月13日

  68. Development of 3D Integration Technologies and Recent Challenges 招待有り

    Takafumi Fukushima

    ADMETA Plus 2012 Advanced Metallization Conference 2012:the 22nd Asian Session 2012年10月23日

  69. 3D Integration Technologies Based on Surface-Tension Driven Multi-Chip Self-Assembly Techniques 招待有り

    Takafumi Fukushima

    The 222nd ECS Meeting: PRiME (Pacific Rim Meeting) 2012年10月8日

  70. 先端三次元積層型LSIの技術動向と展望 招待有り

    福島誉史

    SEMI Forum Japan 2012: TSV/3次元積層化技術セミナー(1)-いよいよ量産へ、ここまで来たTSV技術 2012年6月13日

  71. Wafer-Level 3D Integration Technology Using Self-Assembly 招待有り

    Takafumi Fukushima

    MSPNEX (International Micro System Packaging Forum) 2012 2012年4月12日

  72. 3D Chip Stacking Technologies and Hetero System Integration (三次元チップ積層技術と異種デバイスの集積) 招待有り

    福島誉史

    SEMIテクノロジーシンポジウム(STS)2011 STS Session 4 パッケージング 2011年12月8日

  73. Development of Wafer-Level 3D System Integration Technologies 招待有り

    Takafumi Fukushima

    The International Union of Materials Research Societies-International Conference in Asia (IUMRS-ICA) 12th International Conference in Asia 2011年9月20日

  74. 3D and Hetero Integration Based on Chip-to-Wafer Bonding Using Self-Assembly Technologies 招待有り

    2011年5月9日

  75. シリコン貫通光インターコネクション(TSPV)を用いた光電子三次元集積化技術 招待有り

    福島誉史

    2011年春季 第58回 応用物理学関係連合講演会 文科内総合講演 高集積微細デバイスにおける今後の信号伝達 / 配線技術 2011年3月25日

  76. バッチ式Die-to-Wafer三次元集積化技術 招待有り

    福島誉史

    関西ワークショップ2010 2010年7月9日

  77. セルフアセンブリを基盤としたウェーハレベル三次元集積化技術 招待有り

    福島誉史

    応用物理学会 シリコンテクノロジー分科会/電子情報通信学会 シリコン材料•デバイス研究会(SDM) 第118回研究集会 IEDM特集(先端CMOSデバイス・プロセス技術) 2010年1月29日

  78. 3D積層技術 招待有り

    福島誉史

    IEEE Electron Devices Society (EDS) Japan Chapter総会・2009 International Electron Devices Meeting (IEDM) 報告会 2010年1月26日

  79. Self-Assembled 3D Chip Stacking Technology 招待有り

    2009年10月5日

  80. セルフアセンブリ法を用いた新しいヘテロインテグレーション技術 招待有り

    福島誉史, 田中徹, 小柳光正

    応用物理学会シリコンテクノロジー分科会 2009年8月3日

  81. 自己組織化によるヘテロインテグレーション技術 招待有り

    第12回低温接合による3D集積化研究会 2009年4月22日

  82. Super Hetero-Integration Technology for LSI /MEMS Integration 国際会議 招待有り

    M. Koyanagi, K.-W. Lee, T. Fukushima, T. Tanaka

    International Conference on Electronics Packaging (ICEP) 2009年4月14日

  83. Super Chip Integration Technology for Three-Dimensionally Stacked Retinal 国際会議 招待有り

    T. Fukushima, T. Tanaka, M. Koyanagi

    Smart System Integration Conference 2009 2009年3月10日

  84. 自己組織化を用いた高密度実装技術とスーパーチップインテグレーション” 招待有り

    福島誉史

    第10回半導体パッケージング技術展 専門技術セミナー 2009年1月30日

  85. Three-Dimensional Integration Technology to Achieve Super Chip 国際会議 招待有り

    T. Fukushima, T. Tanaka, M. Koyanagi

    Electropackage System and Interconnect Product Seminar, SEMICON Korea 2009 STS(SEMI Technology Symposium) 2009年1月20日

  86. New Heterogeneous Multi-Chip Module Integration Technology Using Self-Assembly Method 国際会議 招待有り

    T. Fukushima, T. Konno, K. Kiyoyama, M. Murugesan, K. Sato, W.-C.Jeong, Y. Ohara, A. Noriki, S. Kanno, Y. Kaiho, H. Kino, K. Makita, R.Kobayashi, C.-K. Yin, K. Inamura, K.-W. Lee, J.-C. Bea, T. Tanaka, M.Koyanagi

    IEEE The International Solid-State Circuits Conference (ISSCC) 2009年1月8日

  87. Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking 国際会議 招待有り

    T. Fukushima, T. Tanaka, M.Koyanagi

    MRS (Material Research Society) fall meeting 2008年12月1日

  88. 実装プロセス・膜形成技術概論 招待有り

    福島誉史

    神奈川県産業競争力強化戦略推進事業 よこはま高度実装技術コンソーシアム(YJC)が実施する実力派実装技術者育成プログラム JISSO スクール2008 深掘コース(実装インターコネクションコース) 2008年10月14日

  89. セルフアセンブリーを用いた3次元集積化技術 招待有り

    福島 誉史, 田中 徹, 小柳 光正

    九州学術研究都市 第8回 産学連携フェア Advanced Business Model for Semiconductor(ABMS)セミナー北九州 2008年10月9日

  90. 3D system integration technology and 3D systems 国際会議 招待有り

    T. Fukushima, T. Tanaka, M. Koyanagi

    Advanced Metallization Conference (AMC) 2008 2008年9月23日

  91. 自己組織化によるウェーハレベル三次元集積化技術 招待有り

    福島 誉史, 田中 徹, 小柳 光正

    2008 最先端実装シンポジウム 2008年6月12日

  92. A New Nano-System with Three-Dimensional Structure for Real Time Parallel Image Processing 国際会議 招待有り

    T. Fukushima, M. Koyanagi

    The 5th International Conference on Mechanical Science based on Nanotechnology 2008年3月6日

  93. 3D system integration technology and 3D systems 国際会議 招待有り

    Takafumi FUKUSHIMA Tetsu TANAKA, Mitsumasa KOYANAGI

    European Workshop Materials for Advanced Metallization (MAM) 2008 2008年3月2日

  94. 自己組織化ウェーハ張り合わせによる三次元集積化技術 招待有り

    福島誉史, 田中徹, 小柳光正

    電子情報通信学会 シリコン材料・デバイス研究会(SDM) 応用物理学会シリコンテクノロジー分科会多層配線システム研究委員会 2008年2月8日

  95. 「次世代インテリジェント実装技術」 3次元実装技術 招待有り

    福島 誉史, 田中 徹, 小柳 光正

    エレクトロニクス実装学会/材料技術委員会公開研究会 2007年11月29日

  96. Thermal Issues of 3D ICs 国際会議 招待有り

    T. Fukushima, T. Tanaka, M. Koyanagi

    Workshop on Driving the future of interconnect in 3D: Thermal and Design Issues in 3D ICs 2007年10月11日

  97. 3D Integration Technology Based on Chip-to-Wafer Bonding with Through-Si Vias (TSV) 招待有り

    第2回 低温接合による3D集積化研究会 2007年9月18日

  98. チップーウエハ3D 実装を用いたスーパーチップ積層技術 招待有り

    福島誉史

    長野実装フォーラム2007 2007年6月29日

︎全件表示 ︎最初の5件までを表示

産業財産権 48

  1. 基材、塗布方法及び塗布装置

    圓崎諭, 寺田豊治, 小柳光正, 李康旭, 田中徹, 福島誉史, 谷義則

    特許6842660

    産業財産権の種類: 特許権

  2. 半導体装置およびその製造方法

    特許10483240

    産業財産権の種類: 特許権

  3. 液体を用いて基板に対するチップ部品のアライメントを行う方法

    特許10553455

    産業財産権の種類: 特許権

  4. FLEXIBLE FAN-OUT WAFER LEVEL PROCESS AND STRUCTURE

    Subramanian, S. IYER, Takafumi FUKUSHIMA, Adeel A. BAJWA

    特許708313

    産業財産権の種類: 特許権

  5. 液体を用いて基板に対するチップ部品のアライメントを行う方法

    特許10553455

    産業財産権の種類: 特許権

  6. 液体を用いて基板に対するチップ部品のアライメントを行う方法

    菊田真也, 星野聡彦, 福島誉史, 小柳光正, 李康旭

    特許6600922

    産業財産権の種類: 特許権

  7. 半導体デバイスの製造方法

    小柳光正, 田中徹, 福島誉史, 李康旭, 阿部洋史, 堀田吉則

    特許6473897

    産業財産権の種類: 特許権

  8. 半導体装置およびその製造

    小柳光正, 李康旭, 浅海一志, 福島誉史, 鈴木拓

    特許6467981

    産業財産権の種類: 特許権

  9. 半導体装置およびその製造方法

    Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, Kang-Wook Lee

    特許10177118

    産業財産権の種類: 特許権

  10. 半導体装置

    小柳光正, 福島誉史, 李康旭

    6225771

    産業財産権の種類: 特許権

  11. 三次元集積回路の製造方法及び装置

    Mitsumasa Koyanagi, Takafumi Fukushima, Sugiyama Masahiko

    特許1276625

    産業財産権の種類: 特許権

  12. 光導波路モジュール、光導波路モジュールの製造方法

    小柳光正, 田中徹, 福島誉史

    特許5389490

    産業財産権の種類: 特許権

  13. 反応現像画像形成法

    特許100440041

    産業財産権の種類: 特許権

  14. 反応現像画像形成法

    友井正男, 福島誉史, 板谷博

    特許3965434

    産業財産権の種類: 特許権

  15. 反応現像画像形成法

    特許1005980050000

    産業財産権の種類: 特許権

  16. チップ支持基板、それを用いた三次元集積回路及びそれらの製造方法並びにアセンブリ装置

    9,449,948

    産業財産権の種類: 特許権

  17. マイクロLEDアレイの製造方法、及びマイクロLEDディスプレイの製造方法、並びにマイクロLEDアレイ、及びマイクロLEDディスプレイ

    福島誉史, 小柳光正, 田中徹, 元吉真

    産業財産権の種類: 特許権

  18. 半導体装置およびその製造方法

    福島誉史, 小柳光正, 裵志哲, 佐久山真一

    産業財産権の種類: 特許権

  19. FLEXIBLE AND STRETCHABLE INTERCONNECTS FOR FLEXIBLE SYSTEMS

    IYER SUBRAMANIAN S, ALAM ARSALAN, HANNA AMIR, FUKUSHIMA TAKAFUMI

    産業財産権の種類: 特許権

  20. 微細配線構造の製造方法および微細配線構造の製造装置

    福島誉史, Mariappan Murugesan, 小柳光正

    産業財産権の種類: 特許権

  21. 延伸装置、及び延伸方法

    福島誉史, 元吉真

    産業財産権の種類: 特許権

  22. FLEXIBLE AND STRETCHABLE INTERCONNECTS FOR FLEXIBLE SYSTEMS

    IYER SUBRAMANIAN S, ALAM ARSALAN, HANNA AMIR, FUKUSHIMA TAKAFUMI

    産業財産権の種類: 特許権

  23. 液体を用いて基板に対するチップ部品のアライメントを行う方法

    産業財産権の種類: 特許権

  24. 液体を用いて基板に対するチップ部品のアライメントを行う方法

    産業財産権の種類: 特許権

  25. 半導体装置およびその製造方法

    小柳光正, 田中徹, 福島誉史

    産業財産権の種類: 特許権

  26. FLEXIBLE FAN-OUT WAFER LEVEL PROCESS AND STRUCTURE

    IYER SUBRAMANIAN S, FUKUSHIMA TAKAFUMI, BAJWA ADEEL A

    産業財産権の種類: 特許権

  27. 液体を用いて基板に対するチップ部品のアライメントを行う方法

    産業財産権の種類: 特許権

  28. 半導体装置およびその製造方法

    産業財産権の種類: 特許権

  29. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE(半導体デバイスおよび半導体デバイスの製造方法)TOHOKU UNIVERSITY/FUJIFILM CORP

    KOYANAGI MITSUMASA, TANAKA TETSU, FUKUSHIMA TAKAFUMI, LEE KANGWOOK, ABE HIROFUMI, HOTTA YOSHINORI

    産業財産権の種類: 特許権

  30. 半導体デバイスおよび半導体デバイスの製造方法

    産業財産権の種類: 特許権

  31. 半導体装置およびその製造方法

    産業財産権の種類: 特許権

  32. チップ支持基板、それを用いた三次元集積回路及びそれらの製造方法並びにアセンブリ装置

    産業財産権の種類: 特許権

  33. チップ支持基板、それを用いた三次元集積回路及びそれらの製造方法並びにアセンブリ装置

    産業財産権の種類: 特許権

  34. チップ支持基板、それを用いた三次元集積回路及びそれらの製造方法並びにアセンブリ装置

    産業財産権の種類: 特許権

  35. 三次元集積回路の製造方法及び装置

    8,349,652

    産業財産権の種類: 特許権

  36. 一括保持トレイ及び三次元集積回路製造装置

    小柳光正, 福島誉史

    産業財産権の種類: 特許権

  37. 三次元集積回路の製造方法及び装置

    産業財産権の種類: 特許権

  38. 三次元集積回路の製造方法及び装置

    433294

    産業財産権の種類: 特許権

  39. Method for forming image through reaction development

    Masao Tomoi, Takafumi Fukushima, Hiroshi Itatani

    7638255 B2

    産業財産権の種類: 特許権

  40. 反応現像画像形成法

    産業財産権の種類: 特許権

  41. 半導体装置およびその製造方法

    6363868

    産業財産権の種類: 特許権

  42. 半導体装置およびその製造方法

    6362254

    産業財産権の種類: 特許権

    権利者: 小柳 光正, 李 康旭, 福島 誉史

  43. チップ支持基板、チップ支持方法、三次元集積回路、アセンブリ装置及び三次元集積回路の製造方法

    小柳 光正, 田中 徹, 福島 誉史

    5963374

    産業財産権の種類: 特許権

  44. チップ支持基板、それを用いた三次元集積回路及びそれらの製造方法並びにアセンブリ装置

    1681437

    産業財産権の種類: 特許権

  45. イメージセンサ

    6011409

    産業財産権の種類: 特許権

  46. 素子の実装方法および光モジュール

    小柳光正, 田中徹, 福島誉史, 伊藤有香

    6027828

    産業財産権の種類: 特許権

  47. 三次元集積回路の製造方法及び装置

    小柳 光正, 福島 誉史

    5389490

    産業財産権の種類: 特許権

  48. 回路基板、電子デバイス内蔵基板、集積回路デバイス、集積回路付き光導波路、電子デバイス内蔵基板の組立方法

    小柳光正, 田中徹, 福島誉史

    5142103

    産業財産権の種類: 特許権

︎全件表示 ︎最初の5件までを表示

共同研究・競争的資金等の研究課題 48

  1. ダイレット集積インモールドエレクトロニクスの基盤創成と浅皮下情報可視化シート開発

    福島 誉史

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research

    研究種目:Grant-in-Aid for Scientific Research (A)

    研究機関:Tohoku University

    2021年4月5日 ~ 2025年3月31日

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    高い柔軟性を有するフレキシブルデバイスの課題である性能を解決するため、微小な無機単結晶半導体チップ(チップレット)の概念を拡張した「ダイレット」をSiウエハ上で柔軟な樹脂に埋め込み圧縮成型するインモールド・エレクトロニクスの技術基盤を創成する。この新しい電子システム集積学を構築するため、毛髪の直径(100μm)以下の一辺を有する微小チップ(ここではMicro-LED)を目的の場所に搭載する超並列アセンブリの技術開発を行う。また、研究代表者が長年かけて学理の体系化に尽力した脳型の三次元積層集積回路(3D-IC)と微小チップのインテグレーションを基軸とし、従来の半導体技術では実現が難しい浅皮下生体情報(主に血管)可視化シートを作製する。本研究の成果は、電子デバイスの可能性を広げて電気電子工学や医工学分野の発展に大きく貢献するだけでなく、曲がるデバイスの応用に限らず、立体的なエレクトロニクスのシステム集積にインパクトをもたらす。本研究では、チップレットの概念を発展させ、受動素子やLED等の小型化するベアダイまで含めた「ダイレット」をウエハレベルでフレキシブル基板に埋め込んで成型し、微細配線でチップ間を短距離接続した高集積なインモールド・エレクトロニクスと呼ぶシステム集積方法論の技術基盤を創成する。基板レスで微細化でき、高性能で柔軟且つ立体成型可能なこの集積手法の鍵となるのは、微小チップ「ダイレット」の超並列アセンブリ技術とインターコネクト技術となる。

  2. 人と同じ視野角と情報処理機能を有する極低侵襲ピクセル分散型完全埋植人工網膜の開発

    田中 徹, 福島 誉史, 木野 久志, 富田 浩史, 清山 浩司, 菅野 江里子

    2021年4月5日 ~ 2024年3月31日

  3. 不揮発性トンネルFETメモリによる超低消費電力ニューラルネットワークチップの開発

    木野 久志, 福島 誉史, 田中 徹

    2020年4月1日 ~ 2023年3月31日

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    本研究ではシナプスの特性を再現した不揮発性トンネルFETメモリによる大規模演算に向けたニューラルネットワークの実現を目指す。近年、脳の階層的情報処理を模したディープニューラルネットワークの活躍は目覚ましいものがある。一方で、神経細胞の発火スパイクの影響まで模したスパイキングニューラルネットワーク(Spiking Neural Network; SNN)には次世代の大規模ニューラルネットワークとして高い関心が寄せられており、様々なメモリデバイスによるシナプスの再現が提案されている。一般に、SNNはシナプスの結合の強さを示す”重み”を保存するメモリ素子とニューロンを模したスパイク生成回路で構成される。本研究ではこれまでのメモリにない特長を有する不揮発性トンネルFETメモリを活用した大規模な超低消費電力ニューラルネットワークを研究開発する。 昨年度までにシナプスの特性の一つであるスパイクタイミング依存可塑性(Spike Timing Dependent Plasticity: STDP)を有する不揮発性トンネルFETメモリの開発を終えた。 本年年度はシナプス回路とニューロン回路をマイクロバンプを介した電気的接続による積層技術に関する研究を行った。回路素子の特性を維持するためには積層プロセスを低温に抑制することが望まれる。本研究ではIn/Auバンプを用いたTLP(Transient-Liquid-Phase)接合を用いることで、接合時は約150度の低温でありながら、500度以上の融点を有する合金を形成するため、非常に高い熱安定性を有する接合を得ることが可能である。 本研究ではIn/Auバンプによる低温接合により、メモリ素子に影響を与えない接合技術を確立した。

  4. マルチスケール応力エンジニアリングが拓く高集積フレキシブルエレクトロニクス

    福島 誉史, マリアッパン ムルゲサン, 木野 久志, 清山 浩司

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Fund for the Promotion of Joint International Research (Fostering Joint International Research (B))

    研究種目:Fund for the Promotion of Joint International Research (Fostering Joint International Research (B))

    研究機関:Tohoku University

    2019年10月7日 ~ 2023年3月31日

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    米国UCLAの電気工学科Distinguished Professor Subramanian Iyerと共同で開発した新構造フレキシブル・ハイブリッド・エレクトロニクス(FHE)の応力解析や曲げ特性の物理を探索し、信頼性の高いシステム集積を創出するための基盤技術研究を行う。我々が「FlexTrate」と名付けた先端ウエハレベルパッケージング技術を応用したこの高集積なFHEでは、厚さ100μm程度で小さく分割した集積回路チップ(チップレットと呼ぶ)をエラストマーに埋め込み、フォトリソグラフィを利用して高密度配線を形成してチップレット間を接続するので、フレキシブルデバイスの性能とスケーラビリティを格段に高めることができる。本研究では、分子レベル、材料レベル、システムレベルの階層的なマルチスケール応力エンジニアリングを駆使し、機械的/電気的信頼性を取得してこの高集積FHEの有用性を工学的に体系化する。高伸縮性基板の変形によりかかる応力の作用機序を深く理解し、配線の信頼性の鍵を握る「応力緩衝層」の構造設計を追求し、デザインルールを策定する。東北大のシリコン貫通配線(TSV: Through-Silicon Via)を用いた三次元積層チップ(3D-IC)をチップレット化し、UCLAのシステム集積技術を融合させ、PDMS(Polydimethylsiloxane)に内蔵した医療用の高集積フレキシブルシステムを創製する。

  5. チップレット内蔵ウェアラブルマイクロLEDディスプレイの開発

    2021年1月 ~ 2023年3月

  6. 染色で誘導自己組織化ナノ配線を創る

    福島 誉史, マリアッパン ムルゲサン

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research

    研究種目:Grant-in-Aid for Challenging Research (Exploratory)

    研究機関:Tohoku University

    2020年7月30日 ~ 2022年3月31日

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    誘導自己組織化(DSA)によりナノ規則構造を構成する一方の高分子ブロック成分に、特定の金属酸化物や有機金属を選択的に物理吸着、化学吸着させる「染色」を応用した配線形成原理を実証した。ポリスチレンとポリメチルメタクリレート(分子量比2:1)から構成されるブロック高分子をφ3μm、深さ10μmのSi深穴に充填させ染色した。染色剤として酸化ルテニウムⅧ(0.5%水溶液)による液相拡散では制御性が低い結果となったが、四酸化ルテニウム(RuO4)による気相拡散では、シリンダ型のナノ周期構造が観察された(ピッチ約30nm)。また、ナノプローバを用いた電気的特性評価より、オーミックな特性を得ることができた。

  7. インモールド・エレクトロニクス用伸縮配線

    2021年4月 ~ 2022年3月

  8. 広視野の視覚を再建する眼球内完全埋植・低侵襲フレキシブル人工網膜の開発

    田中 徹, 福島 誉史, 木野 久志, 富田 浩史, 清山 浩司, 菅野 江里子

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research

    研究種目:Grant-in-Aid for Scientific Research (A)

    研究機関:Tohoku University

    2018年4月1日 ~ 2021年3月31日

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    本研究は失明患者の視覚を工学的手法で再建する人工網膜を開発する。光電変換素子・視覚情報処理回路・刺激電流生成回路を積層した複数個の三次元積層人工網膜チップをフレキシブル基板上に高密度集積する。それを網膜の中心窩及びその周辺部に完全埋植することで現在の単チップ埋植の4倍以上の視野角を実現する。 (1)人工網膜回路設計・試作:広視野角を得るために2.5mm角・9チップ搭載を目指して人工網膜回路の設計試作を行った。これまでの3mm角・4チップ搭載より1000ピクセル以上増加する。チップ選択回路も実装し、広視野角と低消費電力動作を両立できた。また、エッジ強調後の非動作ピクセルの完全停止回路を改良し、動作判別のしきい値を調整可能にした。エッジの鮮明化と低消費電力化が可能になった。 (2)積層化・マルチチップフレキシブル人工網膜作製:複数個の人工網膜チップを生体適合性フレキシブル材料に集積・内蔵するFOWLPベース実装プロセス技術を開発している。フレキシブル基板上の金属配線は曲げ応力による断線が懸念されるが、金配線の一部を周期的に基板から剥離する皺状金配線による解決を提案し、繰り返し曲げ信頼性が向上することを実証した。また、複数チップ搭載では熱応力低減のため200℃以下の低温プロセスが望ましい。OER-TEOSを用いて150℃のTSV低温作製に成功し、良好な電気特性を得た。 (3)細胞・動物実験評価:人工網膜チップの光変換感度向上と刺激電流による細胞ダメージ低減を両立するために透明刺激電極を開発している。単層で電気特性を取得するため、フォトダイオードを有する視覚情報処理・刺激電流生成チップ上に透明刺激電極を作製した。AlやBをドープしたZnO電極を実チップに成膜することに成功しているが、チップ接触抵抗が大きいという問題が発生しており、コンタクトホールの形成プロセス最適化を行っている。

  9. ウエハ検査用微細TSV集積化プローブカードの実用化開発

    2020年10月 ~ 2021年3月

  10. 高密度ナノ配線形成に資する金属含有ブロック高分子のグラフォ・ケミカルエピタキシ

    2018年4月 ~ 2021年3月

  11. 三次元集積技術を基盤としたナノプローブカードの試作と事業性検証

    2019年10月 ~ 2020年9月

  12. 高集積ハイドロゲル創製への挑戦

    福島 誉史, ベ ジチョル

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Research (Exploratory)

    研究種目:Grant-in-Aid for Challenging Research (Exploratory)

    研究機関:Tohoku University

    2018年6月29日 ~ 2020年3月31日

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    本研究では、フレキシブルデバイスで一般的に利用されるPETやポリイミド、あるいはPDMSなどのフレキシブル基板材料をハイドロゲルに置き換え、高集積なフレキシブルハイブリッドエレクトロニクス(FHE)を創出するための要素技術の創出、およびシステム集積まで検討した。先端のウエハレベル半導体パッケージング技術を応用し、微小なLEDチップとLSIチップをハイドロゲルに埋め込んで高密度配線で接続したウエアラブルパッチを作製するために必要な技術を立ち上げることに成功した。

  13. 自己組織化支援拡散法による極微細シリコン貫通配線形成技術

    2019年6月 ~ 2020年3月

  14. 硬い単結晶半導体で創る曲面集積フレキシブルデバイス創製

    2018年6月 ~ 2019年6月

  15. 次世代積層LSIを志向した誘導自己組織化配線の形成とメカニズム解析

    福島 誉史, 大山 俊幸, ベ ジチョル, 橋本 宏之

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    研究種目:Grant-in-Aid for Scientific Research (B)

    研究機関:Tohoku University

    2016年4月1日 ~ 2019年3月31日

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    本研究は人工知能の普及に伴い更なる需要が見込まれる次世代の大規模集積回路(LSI)と呼ばれる「三次元積層型集積回路(3D-LSI)」の性能を高めるための立体配線の微細化を追求する。従来、リソグラフィ、エッチング、電解めっきなどを組み合わせたトップダウン的な手法であったが、ここではボトムアップ的な手法と考案した。高分子材料と金属からなるナノコンポジットのナノ相分離を利用した極微細構造形成「誘導自己組織化」により従来比1/100以下の直径を有する三次元配線TSV (Through-Si Via: Si貫通配線)を形成できた。

  16. 高信頼性フレキシブルFOWLP技術に関する研究

    2018年4月 ~ 2019年3月

  17. ウエハ圧縮成型による柔軟な樹脂の高集積化

    2018年4月 ~ 2019年3月

  18. 人の視覚と同じ高次情報処理を実現する眼球内完全埋め込み型人工網膜システムの開発

    田中 徹, 福島 誉史, 富田 浩史, 清山 浩司, 小柳 光正, 菅野 江里子, 木野 久志

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)

    研究種目:Grant-in-Aid for Scientific Research (A)

    研究機関:Tohoku University

    2015年4月1日 ~ 2018年3月31日

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    高次情報処理を実現する超低消費電力三次元積層人工網膜LSI回路において、視覚再建に寄与しない40Hz以下の刺激及び両極性電流パルス間において回路動作を止める機構を考案し、62%の消費電力削減に成功した。また、暗電流補償や温度検出の回路設計と試作を行って動作を検証した。人工網膜の光電変換感度向上のためにAl-doped ZnO (AZO)を用いて透明刺激電極を開発した。その結果、網膜刺激電極として適切な電荷注入能力と電極インピーダンスの値を有し、積層化プロセスに対応可能な透明AZO電極の開発に成功した。これにより画素当たりの刺激電極面積(光電変換感度)を3倍以上に増やすことが可能になった。

  19. 高集積ストレッチャブルデバイス作製に資する基盤技術研究

    2017年8月 ~ 2018年3月

  20. 高集積フレキシブル無機単結晶デバイス作製に資する機械加工と信頼性評価

    2017年8月 ~ 2018年3月

  21. ナノコンポジットの拡張誘導自己組織化による超微細配線の一括形成

    2017年4月 ~ 2018年3月

  22. 誘導自己組織化による超立体高密度配線で構築する脳型コンピューティング システム研究

    2016年3月 ~ 2017年7月

  23. ブロック高分子と金属ナノ粒子が創出する拡張誘導自己組織化配線に関する技術開発

    2017年4月 ~

  24. ガラス/高分子界面のデンドリティックアンカー効果発現機構の解明

    福島 誉史, 裵 志哲, 大西 正樹, 長井 千里

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research

    研究種目:Grant-in-Aid for Challenging Exploratory Research

    研究機関:Tohoku University

    2015年4月1日 ~ 2017年3月31日

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    200℃の低温のプラズマCVDで成膜したSiO2と、200℃の気相堆積で成膜したポリイミドの接着に関する研究を行った。特に次世代の三次元積層型集積回路の基幹配線となるTSV(シリコン貫通配線)の信頼性向上を目的として、デンドリティックなアンカー効果を発現させて接着強度を高めることを試みた。その接着強度向上のメカニズムは、物理的な浅いアンカー効果に加えて、自己組織化単分子膜をベースとした密着助剤による界面分子間力の増大によるものと判明した。

  25. 高集積フレキシブルSiデバイス作製技術の開発

    2014年4月 ~ 2015年5月

  26. 原子層堆積重合による縮合系耐熱高分子の積層膜形成と応用

    福島 誉史, マリアッパン ムルゲサン, 裵 志哲

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research

    研究種目:Grant-in-Aid for Challenging Exploratory Research

    研究機関:Tohoku University

    2013年4月1日 ~ 2015年3月31日

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    気相堆積法によりポリイミド薄膜を次世代集積回路の基幹配線として期待されるSi貫通配線(TSV: Through-Silicon Via)のライナー絶縁膜として応用できる可能性を示すことができた。原子層気相堆積(ALD)のような緻密で高制御な超薄膜形成には至らなかったが、100nm以下の膜厚を10nm単位で制御でき、ALDに比べて高い成膜速度(およそ100-200nm/min)で高純度なKapton-H型のポリイミド薄膜を形成できた。アスペクト10、直径5μm以下のSi深穴に80%を超える高い被覆率で堆積でき、既存のプラズマCVDによるSiO2薄膜よりも低い応力でTSVを形成することができた。

  27. 高次視覚情報処理機能を有する完全埋込型低電力三次元積層人工網膜システムの研究

    田中 徹, 清山 浩司, 冨田 浩, 福島 誉史, 小柳 光正

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)

    研究種目:Grant-in-Aid for Scientific Research (A)

    研究機関:Tohoku University

    2012年4月1日 ~ 2015年3月31日

    詳細を見る 詳細を閉じる

    光電変換素子/高次視覚情報処理回路/刺激電流生成回路を1チップに三次元積層して眼球内に埋め込むことで、患者に高いQOLを提供できる「高次視覚情報処理機能を有する完全埋込型低電力三次元積層人工網膜システム」の研究を行った。各回路チップをTSVで三次元積層化して人工網膜チップを作製する技術と、三次元積層人工網膜チップとフレキシブルケーブルをダメージ無くモジュール集積化する技術を開発した。約1300画素の感度切替型受光回路チップ及びエッジ強調機能付き刺激電流生成回路チップを開発した。人工網膜チップのウサギ眼球内埋め込み実験を行い、網膜が変性したウサギへの光刺激によるEEP信号の取得に成功した。

  28. 超微細電極接合のための金属・有機無機ハイブリッド異種材料の精密切削

    2014年8月 ~ 2015年3月

  29. 気相堆積重縮合によるシリコン貫通高分子光導波路の形成と評価

    2014年4月 ~ 2015年3月

  30. 複合Siウェハを用いた高性能・低電力ヘテロCMOSトランジスタの開発

    李 康旭, 福島 誉史, 田中 徹, 裵 志哲, ムルゲサン マリアッパン, 小柳 光正, 裴 艶麗

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    研究種目:Grant-in-Aid for Scientific Research (B)

    研究機関:Tohoku University

    2011年4月1日 ~ 2014年3月31日

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    本研究では、InGaAsを用いてNMOSトランジスタを、Geを用いてPMOSトランジスタを大口径Siウェハ上に混在させて、低コストで高性能・低電力ヘテロCMOSトランジスタを作製できる新しい技術を創出した。Siウェハ上にInGaAsとGe化合物半導体チップを高い位置合わせ精度(<1um)と接合強度で(20MPa)張り合わせる出来るセルフアセンブリー技術を開発した。ヘテロCMOSトランジスタ実現の鍵を握る浅いp-n接合を形成するためのイオン打ち込みとアニール技術を確立した。Siウェハ上に張り合わしたGeおよびInGaAsチップからなるフォトダイオードを試作し、基本動作を確認した。

  31. グラフォアセンブリーによる三次元積層型光電子集積システム・オン・チップ

    小柳 光正, 福島 誉史, 田中 徹, 羽根 一博, 三浦 英生, 裴 艶麗, 清山 浩司

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (S)

    研究種目:Grant-in-Aid for Scientific Research (S)

    研究機関:Tohoku University

    2009年5月11日 ~ 2014年3月31日

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    三次元積層型光電子集積システム・オン・チップの実現を目指して、その鍵となるグラフォアセンブリー技術、シリコンフォト二クス技術の検討を行った。チップ表面の表面状態を制御することによって液体を制御してチップの位置合わせ精度を向上させるグラフォアセンブリー技術を開発し、寸法の異なる500個以上のチップを8インチ・シリコンウェハ上に一括位置合わせ、接合することに成功した。また、シリコンフォト二クス技術については、垂直方向光インターコネクション(TSPV)技術を確立するとともに、高い結合効率を有する微細グレーティングカップラを開発し、三次元積層型光集積システム・オン・チップの実現可能性を明らかにした。

  32. 三次元LSI積層用ウェーハ転写技術の開発

    2011年7月 ~ 2012年3月

  33. 機能性液体による集積回路の自己組織化三次元積層に関する研究

    2011年4月 ~ 2012年3月

  34. 三次元チップ積層のためのウェーハレベル圧縮成形技術の開発

    2011年4月 ~ 2012年3月

  35. リコンフィギャラブル接合を基盤とした三次元集積化研究

    福島 誉史

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    研究種目:Grant-in-Aid for Scientific Research (B)

    研究機関:Tohoku University

    2010年 ~ 2012年

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    三次元集積回路(3DIC)をウェーハレベル、且つ高歩留りで作製するための鍵となるリコンフィギュラブル接合技術を開発し、良品チップにSi貫通配線(TSV:Through-SiVia)を形成して多段積層する新たな三次元集積化技術を創出した。リコンフィギュラブル接合とは、液体の表面張力を駆動源として多数のチップを一括で支持ウェーハ上に位置合わせすると同時に接合させ、高温・高真空下のTSV形成工程を経た後に、チップを剥離して別のウェーハに転写できるインテリジェントな接合が可能であった。これにより従来の(二次元)ICチップにTSVを容易に形成することが可能となるため、3DICの多品種少量生産を目的としたアジャイル集積の実現可能性が検証できた。

  36. 眼球内埋め込み用低電力三次元積層型人工網膜システムの研究

    田中 徹, 富田 浩史, 福島 誉史, 清山 浩司, 小柳 光正

    2010年 ~ 2011年

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    (1)LSIチップ積層化技術及び眼球内に埋め込む各部品の一体化集積技術 導電性高分子であるPEDOT電極の作製技術、及び人工網膜チップのフレキシブルケーブル実装技術を確立した。チップの実装にはフレキシブルケーブル上のAu配線の拡散断線防止を工夫したCuSnマイクロバンプを用いて、300℃以下の低温接合を実現した。また、フォトダイオード受光用貫通孔を有する網膜下刺激フレキシブルケーブルの開発に成功し、網膜内に埋め込まれた人工網膜チップにおいて外界からの光を適切に受光することが可能となった。これらを組み合わせて、人工網膜チップ動作に悪影響を与えない一体化集積技術を確立し、網膜下刺激人工網膜モジュールの電気特性の取得にも成功した。 (2)眼球内で長期間安全に動作する超低消費電力人工網膜LSI回路技術 1300画素の感度切替型光電変換回路チップと近傍4画素ラプラシアン法を用いた視覚情報処理回路チップの設計、及びファウンドリによるチップ試作を行った。人の眼球における明暗感度を忠実に再現する回路を検討するとともに、使用環境に応じた感度手動切替型の高感度受光回路の設計を行った。試作チップを評価した結果、仕様を満たす感度曲線が得られることを確認した。また、4近傍ラプラシアンフィルタを用いた完全埋め込み型人工網膜のためのエッジ強調回路を設計した。画素回路面積は75μm角、画素数は約1300である。試作チップを評価した結果、視覚情報のエッジを強調する十分な性能を確認した。この回路を実装した人工網膜により失明患者に高いQOLを提供することが可能である。 (3)眼球内埋め込みモジュールの生物・臨床評価 今年度開発した網膜下刺激人工網膜モジュールを眼球内に埋め込む術式を確立した。透明ガイドを用いることで眼球に大きなダメージを与えることなく網膜下へのモジュール挿入を可能とした。網膜下へ埋め込むことで、従来使用していた金属タックを使用せずに人工網膜モジュールの固定が可能となった。また、網膜下に埋め込んだPEDOT刺激電極から網膜刺激を行い、EEPの取得にも成功した。

  37. 脳機能の統合的研究の支援と推進 競争的資金

    制度名:Grant-in-Aid for Scientific Research

    2005年4月 ~ 2010年3月

  38. 自己組織化による異種デバイス混載積層型チップの創製

    福島 誉史, 小柳 光正, 田中 徹

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (A)

    研究種目:Grant-in-Aid for Young Scientists (A)

    研究機関:Tohoku University

    2007年 ~ 2009年

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    液体の表面張力を駆動力とした自己組織化チップ位置合わせ、および接合技術を基盤とした三次元集積化技術の基礎を開拓し、異種デバイスを混載したテストモジュールを試作した。平均位置合わせ精度は1μm以内であり、500個以上の5mm角チップを一括して0.1秒以内の瞬時に位置合わせさせることに成功した。また、常温で荷重をかけずにチップを基板上に直接接合することも可能にした。

  39. 金属ナノドット不揮発性メモリのナノインテグレーション

    田中 徹, 福島 誉史, 裴 艶麗

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research on Priority Areas

    研究種目:Grant-in-Aid for Scientific Research on Priority Areas

    研究機関:Tohoku University

    2006年 ~ 2009年

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    Self-Assembled Nanodot Deposition法を用いて、超微細(~1.5nm)・高密度(1.3x10^<13>/cm^2)の世界トップレベルの金属ナノドットの形成に成功した。制御ゲート用High-k絶縁膜と金属ナノドットフローティングゲートを有する不揮発性メモリの作製にも成功し、大きな仕事関数を有するコバルトナノドットによって、長い電荷保持時間・優れた耐久性・大きなメモリウィンドウを得た。また、ポテンシャル変調ゲートスタックを有する多層金属ナノドットメモリの基本動作検証に成功した。

  40. 超高集積、低電力メモリデバイスに関する研究:金属ナノドットメモリの開発 競争的資金

    制度名:JST Basic Research Programs (Core Research for Evolutional Science and Technology :CREST)

    2003年3月 ~ 2008年4月

  41. ナノテクノロジー基盤機械科学フロンティア:ナノテクノロジーとIT、バイオテクノロジーを駆使して、新しいナノデバイス、ナノマシン、バイオナノマシンの実現 競争的資金

    制度名:SCF System for Establishment and Support of Center's of Excellence

    2003年4月 ~ 2008年3月

  42. トンネル注入制御Geナノデバイスを用いた超高周波キャリア伝導機構の解明

    田中 徹, 福島 誉史, 福島 誉史, MOSSAD Ali Atif

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    研究種目:Grant-in-Aid for Scientific Research (B)

    研究機関:Tohoku University

    2007年 ~ 2008年

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    従来のCMOS技術の延長では実現不可能であるナノメートル領域で動作する新しいトンネル注入制御ゲルマニウムナノデバイスを提案し、キーテクノロジである高純度ゲルマニウム層の作製技術を確立した。また、高透磁率金属ナノドットを有する高周波動作用インダクタの作製に成功した。キャリア伝導メカニズムの実験的解析法として、超高周波領域で測定した散乱パラメータ(Sパラメータ)を用いたキャリアの反射/透過現象のモデル化手法を確立した。

  43. 自己組織化による三次元集積回路の開発 競争的資金

    制度名:Grant-in-Aid for Scientific Research

    2003年4月 ~ 2007年3月

  44. 文部科学省ITプログラム:MRAMの回路技術、シミュレーションとメモリセルの試作 競争的資金

    制度名:The Other Research Programs

    2002年4月 ~ 2007年3月

  45. 積層型人工網膜システムの開発 競争的資金

    制度名:SCF System for Establishment and Support of Center's of Excellence

    2002年4月 ~ 2007年3月

  46. 三次元積層型プロセッサチップを用いた超高性能並列処理システム

    小柳 光正, 羽根 一博, 寒川 誠二, 田中 徹, 福島 誉史, 栗野 浩之, 沈 正七, 宮川 宣明

    提供機関:Japan Society for the Promotion of Science

    制度名:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (S)

    研究種目:Grant-in-Aid for Scientific Research (S)

    研究機関:Tohoku University

    2003年 ~ 2007年

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    新しい共有メモリ結合型並列処理システムを提案し、実際に設計して性能評価を行った。設計したシステムでは、共有データは光インターコネクションより成る高速のマルチポート・リングバスを介して各プロセッサ(PE)に送られるようになっている。積層構造のノード共有キャッシュメモリを用いことによってミス率を減少させて、システム性能を向上させることができた。接続するプロセッサの台数にほぼ比例する性能が得られており、本研究で提案したシステムの有効性を確認できた。以上のような並列処理システム実現のかぎを握る光インターコネクション技術と三次元集積化技術について検討した。光導波路に関しては、0.029dB/cmという極めて損失の少ない光導波路の作製に成功した。この低損失光導波路を用いて、10Gbps(導波路長:5cm)の高速データ転送を確認した。また、ビームリードボンディング法という新しい手法を開発して、発光・受光素子をLSIテストチップ上への直接搭載することに成功した。これらの技術を用いて、キャッシュメモリとなるSRAMテストチップを光導波路で接続したテストモジュールを試作し、メモリチップ間で光によるデータ転送に成功した。三次元集積化技術に関しては、ウェーハ張り合わせによる三次元集積化技術を開発し、この技術を用いて世界初の三次元積層型プロセッサ・テストチップの試作に成功した。更に、10層積層の三次元積層型メモリ・テストチップの試作にも成功した。また、より大規模で高性能のプロセッサチップとメモリチップを積層するために、異なったサイズのチップを張り合わせることのできる新しい三次元集積化技術(スーパーチップインテグレーション技術)を開発した。

  47. ナノフィラーを含む熱硬化性樹脂の分子設計と次世代集積回路への応用 競争的資金

    福島 誉史

    制度名:Grant-in-Aid for Scientific Research

    2005年 ~ 2006年

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    Si基板上に塗布・硬化後に発生する反りの測定から、粒径50nmのナノフィラーを含むエポキシ樹脂の熱膨張係数(CTE)は、粒径の大きな(200-2000nm)フィラーを含むエポキシ樹脂のそれと比較して大きな差はないことが判明した。CTE値はフィラー含有率に依存するが、フィラー含有率の増大により樹脂の粘度が著しく上昇する。また、ナノサイズのフィラーは樹脂の硬化を阻害するため、樹脂のガラス転移温度を低下させる。次世代集積回路として注目されている三次元積層型チップのアンダーフィル剤として使用するには、約4μmの間隙に粘性の樹脂を流し込む必要がある。そのためには、樹脂に混合するフィラーの粒径はナノサイズにすることが必要であるが、樹脂粘性の増大を抑制することが必要不可欠である。 本研究では、積層型チップ間の狭ギャップに低粘性の樹脂を短時間で注入し且つ、反りの発生を最小限に抑えることができるように樹脂の分子設計を行った。ここで用いた樹脂の特徴を以下に示す。 1.樹脂A:エポキシ樹脂、粘度:400cPs、表面張力:45mN/m 2.樹脂B:シリコーン樹脂、粘度:1000cPs、表面張力:20mN/m シリコーン樹脂の塗布膜厚が30μmの時の反り量は低く約5μmであったが、アンダーフィル後の研磨、CMP工程ではその低弾性率(約50MPa)が信頼性に欠ける。一方、発生する反り量は、樹脂膜厚に強く依存し、エポキシ樹脂の膜厚が10μmの場合、反り量は+15μmであった。このエポキシ樹脂を用いて注入を行った結果、Peripheral bumpを形成した5mm角チップの充填に要する時間は約110秒であり、計算式から求めた理論注入時間150秒より短い。この理由は、注入前、チップ端に滴下する樹脂の容量に強く依存するためである。適量な樹脂を滴下することにより十分に実用的な時間内で注入できることが分かった。

  48. 先導的研究等の推進:Nano-CMOS超低消費電力デバイス技術 競争的資金

    制度名:Special Coordination Funds for Promoting Science and Technology

    2002年3月 ~ 2005年4月

︎全件表示 ︎最初の5件までを表示

担当経験のある科目(授業) 12

  1. 電気電子回路II 東北大学

  2. 数学物理学演習I 東北大学

  3. 機械設計学II(英語コース) 東北大学

  4. バイオナノテクノロジー特論 東北大学

  5. 脳神経システム学(ニューロモーフィックデバイス工学) 東北大学

  6. 計画及び製図I(英語コース) 東北大学

  7. 機械知能・航空実験II「集積回路設計の基礎」 東北大学

  8. 医工学概論、医工学基礎 東北大学

  9. 機械知能・航空工学科 特別講義Ⅱ(人と機械のハーモニー) 東北大学

  10. バイオロボットシステム入門(国際機械工学コース入門) 東北大学

  11. Organic/Polymer Materials for Microelectronics in Special Topics of Physical and Wave Electronics Electric Engineering Department, UCLA

  12. コンピュータ実習 東北大学

︎全件表示 ︎最初の5件までを表示

社会貢献活動 1

  1. 学外授業

    2009年6月26日 ~

    詳細を見る 詳細を閉じる

    宮城県立泉高校にて大学紹介、および出張講義を行った

メディア報道 19

  1. 半導体、「チップレット」で進化 微細化代替へ産学連携

    日本経済新聞 https://www.nikkei.com/article/DGXZQOUC230G90T21C22A0000000/

    2022年11月3日

    メディア報道種別: インターネットメディア

  2. 最小要素のチップレット集積技術を開発 広帯域接続と集積規模のスケーラビリティを実現

    大阪大学 ResOU https://resou.osaka-u.ac.jp/ja/research/2022/20221005_2

    2022年10月5日

  3. 最小要素のチップレット集積技術を開発 広帯域接続と集積規模のスケーラビリティを実現

    東京工業大学 https://www.titech.ac.jp/news/2022/064932

    2022年10月5日

    メディア報道種別: その他

  4. 2016年度 田中貴金属記念財団研究助成 プラチナ賞 受賞

    日刊金属

    2017年4月3日

    メディア報道種別: 新聞・雑誌

    詳細を見る 詳細を閉じる

    田中貴金属 記念財団 「貴金属に関わる研究助成」の受賞者を発表 「ブロック高分子と金属ナノ粒子が創出する拡張誘導自己組織化配線に関する技術開発 」で 東北大学 福島誉史准教授がプラチナ賞 を受賞 ~貴金属ナノ粒子の特性を活用した、次世代半導体の性能向上や製造コストの削減が可能となる技術開発で受賞~

  5. 田中貴金属記念財団、研究助成の受賞者決定

    鉄鋼新聞

    2017年3月31日

    メディア報道種別: 新聞・雑誌

    詳細を見る 詳細を閉じる

    2016年度 田中貴金属記念財団 研究助成 プラチナ賞受賞

  6. 東北大 新システム集積化技術を開発 自己組織化で一括作製

    半導体産業新聞

    2009年3月4日

    メディア報道種別: 新聞・雑誌

  7. 3次元積層へのセルフ・アセンブリ技術の適用 東北大が成果示す

    日経マイクロデバイス

    2009年3月1日

    メディア報道種別: 新聞・雑誌

  8. セルフ・アセンブル技術の適用 東北大が成果示す

    日系エレクトロニクス

    2009年2月10日

    メディア報道種別: 新聞・雑誌

  9. 異種デバイスを一括搭載 独自のシステム集積化技術開発

    科学新聞

    2009年1月23日

    メディア報道種別: 新聞・雑誌

  10. 異種チップ基板に集積 東北大 水の表面張力利用

    日経産業新聞

    2009年1月15日

    メディア報道種別: 新聞・雑誌

  11. 半導体ウエハ 異種デバイス一括搭載 製造時間短縮 東北大が技術

    日刊工業新聞

    2009年1月14日

    メディア報道種別: 新聞・雑誌

  12. 異種部品一括し基板に 製造コスト大幅減

    河北新報

    2009年1月14日

    メディア報道種別: 新聞・雑誌

  13. 患者の目に光を!世界初の人工網膜(資料提供 テレビ 仙台放送)(2007)

    2007年8月21日

    メディア報道種別: テレビ・ラジオ番組

  14. 3-D chip vendor corrects course

    2005年12月28日

    メディア報道種別: その他

  15. チップ10層立体LSI(厚さ0.3ミリ 微細化の壁 突破に期待)

    2005年12月28日

    メディア報道種別: 新聞・雑誌

  16. 三次元集積回路を開発

    2005年12月23日

    メディア報道種別: 新聞・雑誌

  17. チップ積み上げLSI(東北大が新手法 10層が可能 消費電力も期待)

    2005年12月23日

    メディア報道種別: 新聞・雑誌

  18. 三次元LSIを試作(積層構造を高速処理)

    2005年12月23日

    メディア報道種別: 新聞・雑誌

  19. 自己組織化法によるスーパーチップ技術の開発

    2005年12月22日

    メディア報道種別: テレビ・ラジオ番組

︎全件表示 ︎最初の5件までを表示

その他 13

  1. ナノコンポジットの拡張誘導自己組織化による超微細配線の一括形成

    詳細を見る 詳細を閉じる

    ナノコンポジットの拡張誘導自己組織化による超微細配線の一括形成

  2. 高集積フレキシブル無機単結晶デバイス作製に資する機械加工と信頼性評価

    詳細を見る 詳細を閉じる

    高集積フレキシブル無機単結晶デバイス作製に資する機械加工と信頼性評価

  3. ブロック高分子と金属ナノ粒子が創出する拡張誘導自己組織化配線に関する技術開発

    詳細を見る 詳細を閉じる

    ブロック高分子と金属ナノ粒子が創出する拡張誘導自己組織化配線に関する技術開発

  4. 高集積ストレッチャブルデバイス作製に資する基盤技術研究

    詳細を見る 詳細を閉じる

    高集積ストレッチャブルデバイス作製に資する基盤技術研究

  5. 気相堆積重縮合によるシリコン貫通高分子光導波路の形成と評価

    詳細を見る 詳細を閉じる

    気相堆積重縮合によるシリコン貫通高分子光導波路の形成と評価

  6. 高集積フレキシブルSiデバイス作製技術の開発

    詳細を見る 詳細を閉じる

    高集積フレキシブルSiデバイス作製技術の開発

  7. 超微細電極接合のための金属・有機無機ハイブリッド異種材料の精密切削

    詳細を見る 詳細を閉じる

    超微細電極接合のための金属・有機無機ハイブリッド異種材料の精密切削

  8. 三次元LSI積層用ウェーハ転写技術の開発

    詳細を見る 詳細を閉じる

    三次元LSI積層用ウェーハ転写技術の開発

  9. 三次元チップ積層のためのウェーハレベル圧縮成形技術の開発

    詳細を見る 詳細を閉じる

    三次元チップ積層のためのウェーハレベル圧縮成形技術の開発

  10. 機能性液体による集積回路の自己組織化三次元積層に関する研究

    詳細を見る 詳細を閉じる

    機能性液体による集積回路の自己組織化三次元積層に関する研究

  11. 三次元積層型プロセッサチップを用いた超高性能並列処理システム

    詳細を見る 詳細を閉じる

    三次元積層型プロセッサチップを用いた超高性能並列処理システム 構築するための要素技術の開発、および試作チップの作製

  12. 科学技術振興調整費 先導的研究等の推進

    詳細を見る 詳細を閉じる

    ”Nano-CMOS超低消費電力デバイス技術”の開発

  13. 戦略的創造研究推進事業

    詳細を見る 詳細を閉じる

    共鳴磁気トンネル・ナノドット不揮発性メモリの創製

︎全件表示 ︎最初の5件までを表示