Details of the Researcher

PHOTO

Naoya Onizawa
Section
Research Institute of Electrical Communication
Job title
Associate Professor
Degree

  • 博士（工学）（東北大学）

  • 修士（工学）（東北大学）

Research History 11

  • 2020/11 - Present
    Tohoku University　Research Institute of Electrical Communication　Associate Professor

  • 2020/05 - Present
    Tohoku University

  • 2021/01 - 2024/03
    文部科学省「世界で活躍できる研究者戦略育成事業・学際融合グローバル研究者育成東北イニシアティブ」　育成対象者

  • 2018/10 - 2022/03
    JST　PRESTO researcher

  • 2018/12 - 2020/10
    Tohoku University　Research Institute of Electrical Communication　Assistant Professor

  • 2013/12 - 2018/11
    Tohoku University　Frontier Research Institute for Interdisciplinary Sciences　Assistant Professor

  • 2013/10 - 2013/11
    Tohoku University　Research Institute of Electrical Communication

  • 2012/04 - 2013/09
    McGill University　Department of Electrical and Computer Engineering　Postdoc fellow

  • 2011/10 - 2012/03
    University of Waterloo　Department of Electrical and Computer Engineering　Postdoc fellow

  • 2011/04 - 2011/09
    McGill University　Department of Electrical and Computer Engineering　Postdoc fellow

  • 2015/06 -
    University of Southern Brittany　Guest associate professor

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Committee Memberships 14

  • 2025 東北支部連合大会　庶務担当

    2024/10 - Present

  • 情報処理学会東北支部　庶務幹事

    2024/06 - Present

  • Technical Program Committee　2025 IEEE International Symposium on Asynchronous Circuits and Systems

    2024/09 - 2025/06

  • 2025 IEEE International Symposium on Multiple-Valued Logic　Program Co-Chair

    2024/09 - 2025/06

  • 電子情報通信学会　英文論文誌A編集委員

    2020/06 - 2024/05

  • 電子情報通信学会　和文論文誌A編集委員

    2020/06 - 2024/05

  • IEEE Transactions on Nanotechnology　Guest Editor for special issue of Nanoarch 2021

    2022/01 - 2022/12

  • 16th ACM/IEEE International Symposium on Nanoscale Architectures　Program Co-Chair

    2021/04 - 2021/10

  • 2021 IEEE International Symposium on Multiple-Valued Logic　Program Co-Chair

    2020/10 - 2021/05

  • IEEE International Symposium on Asynchronous Circuits and Systems　Technical Program Committee

    2018/09 - 2021/05

  • IEEE International Symposium on Multiple-Valued Logic　Technical Program Committee

    2016/09 - 2021/05

  • Technical Committee on Multiple-Valued Logic of IEEE Computer Society　Members-at-Large

    2017/01 - 2019/12

  • 2019 IEEE International Symposium on Asynchronous Circuits and Systems　Publication chair

    2017/09 - 2019/05

  • 2016 IEEE International Symposium on Multiple Valued Logic　Secretary

    2014/09 - 2016/05

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Professional Memberships 2

  • IEICE

  • IEEE

Research Interests 9

  • Invertible logic

  • FPGA

  • Annealing

  • Probabilistic information processing

  • Hardware algorithm

  • Network on Chip

  • Associative memory

  • Asynchronous circuits

  • Stochastic computing

Research Areas 3

  • Informatics / Computational science /

  • Informatics / Soft computing /

  • Informatics / Computer systems /

Awards 10

  1. 2024年度キオクシア奨励研究 優秀研究賞

    2025/07　キオクシア　確率ビットに基づく次世代省エネルギーコンピュータの実現に向けた精度評価ベンチマークの開発

  2. 第16回青葉工学振興会賞

    2022/12　一般財団法人青葉工学振興会　確率的コンピューティングに基づく脳型情報処理

  3. 令和2年度科学技術分野の文部科学大臣表彰・若手科学者賞

    2020/04　文部科学省　確率的コンピューティングに 基づく脳型情報処理システム 研究

  4. 平成29年度電気・情報系若手優秀研究賞

    2018/03　東北大学電気・情報系研究教授会

  5. Kenneth C. Smith Early Career Award for Microelectronics Research in 46th IEEE International Symposium on Multiple-Valued Logic (ISMVL)

    2016/05　IEEE Technical Committee on Multiple-Valued Logic

  6. 一般財団法人青葉工学振興会第20回青葉工学研究奨励賞

    2014/12/05　一般財団法人青葉工学振興会　非同期式信号処理に基づく高速・低電力VLSIの実現に関する研究

  7. 3rd place at Falling Walls Lab Sendai 2014

    2014/08/21　Falling Walls Lab　Paradigm Shift in Computing

  8. Best Paper Finalist (2014 IEEE International Symposium on Asynchronous Circuits and Systems)

    2014/05　IEEE

  9. Best Paper Award (2010 IEEE Computer Society Annual Symposium on VLSI)

    2010/07　IEEE

  10. 学生優秀論文賞受賞(平成１６年度電子情報通信学会東北支部)

    2004/12/01　電子情報通信学会

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Papers 139

  1. GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    Scientific Reports　15　(1)　2025/02/19

    Publisher: Springer Science and Business Media LLC

    DOI： 10.1038/s41598-025-90520-3 　

    eISSN： 2045-2322

  2. Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning Peer-reviewed

    R. Kanda, N. Onizawa, M. Leonardon, V. Gripon, T. Hanyu

    2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS)　928-931　2024/08/11

    Publisher: IEEE

    DOI： 10.1109/mwscas60917.2024.10658789 　

  3. Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems Peer-reviewed

    Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

    IEEE Access　12　102050-102060　2024/07

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/access.2024.3431540 　

    eISSN： 2169-3536

  4. Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    Scientific Reports　14　(1)　1339　2024/01/16

    Publisher: Springer Science and Business Media LLC

    DOI： 10.1038/s41598-024-51639-x 　

    eISSN： 2045-2322

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    Abstract This article critically investigates the limitations of the simulated annealing algorithm using probabilistic bits (pSA) in solving large-scale combinatorial optimization problems. The study begins with an in-depth analysis of the pSA process, focusing on the issues resulting from unexpected oscillations among p-bits. These oscillations hinder the energy reduction of the Ising model and thus obstruct the successful execution of pSA in complex tasks. Through detailed simulations, we unravel the root cause of this energy stagnation, identifying the feedback mechanism inherent to the pSA operation as the primary contributor to these disruptive oscillations. To address this challenge, we propose two novel algorithms, time average pSA (TApSA) and stalled pSA (SpSA). These algorithms are designed based on partial deactivation of p-bits and are thoroughly tested using Python simulations on maximum cut benchmarks that are typical combinatorial optimization problems. On the 16 benchmarks from 800 to 5000 nodes, the proposed methods improve the normalized cut value from 0.8 to 98.4% on average in comparison with the conventional pSA.

  5. Stochastic Implementation of Simulated Quantum Annealing on PYNQ

    Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

    2023 International Conference on Field Programmable Technology (ICFPT)　2023/12/12

    Publisher: IEEE

    DOI： 10.1109/icfpt59805.2023.00042 　

  6. Improving Stochastic Quantum-Like Annealing Based on Rerandomization Peer-reviewed

    Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

    2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)　2023/12/04

    Publisher: IEEE

    DOI： 10.1109/icecs58634.2023.10382735 　

  7. Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

    Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

    IEEE Transactions on Neural Networks and Learning Systems　34　(12)　10999-11005　2023/12

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/tnnls.2022.3159713 　

    ISSN： 2162-237X

    eISSN： 2162-2388

  8. Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing Peer-reviewed

    Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu

    IEEE Open Journal of Signal Processing　4　452-461　2023/11

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/ojsp.2023.3329756 　

    eISSN： 2644-1322

  9. Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic Peer-reviewed

    Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

    IEEE Access　11　44923-44931　2023/05

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/access.2023.3272867 　

    eISSN： 2169-3536

  10. Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing Peer-reviewed

    Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

    IEEE Journal on Emerging and Selected Topics in Circuits and Systems　13　(1)　108-118　2023/03

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/jetcas.2023.3243260 　

    ISSN： 2156-3357

    eISSN： 2156-3365

  11. Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing Peer-reviewed

    Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

    2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)　2022/10/24

    Publisher: IEEE

    DOI： 10.1109/icecs202256217.2022.9971124 　

  12. Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN Peer-reviewed

    D. Shin, N. Onizawa, T. Hanyu

    Journal of Applied Logics　9　(3)　585-606　2022/06

  13. CMOS Invertible Logic: Bidirectional operation based on the probabilistic device model and stochastic computing Invited Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    IEEE Nanotechnology Magazine　16　(1)　33-46　2022/02

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/mnano.2021.3126094 　

    ISSN： 1932-4510

    eISSN： 1942-7808

  14. Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices Peer-reviewed

    Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

    2021 IEEE Workshop on Signal Processing Systems (SiPS)　2021/10

    Publisher: IEEE

    DOI： 10.1109/sips52927.2021.00047 　

  15. Design Automation of Invertible Logic Circuit From a Standard HDL Description Peer-reviewed

    M. Kato, N. Onizawa, T. Hanyu

    Journal of Applied Logics　8　(5)　1311-1333　2021/06

  16. High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    2021 IEEE International Symposium on Circuits and Systems (ISCAS)　2021/05

    Publisher: IEEE

    DOI： 10.1109/iscas51556.2021.9401278 　

  17. A Design Framework for Invertible Logic Peer-reviewed

    Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems　40　(4)　655-665　2021/04

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/tcad.2020.3003906 　

    ISSN： 0278-0070

    eISSN： 1937-4151

  18. Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices Peer-reviewed

    Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

    IEEE Open Journal of Circuits and Systems　2　782-791　2021

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/ojcas.2021.3116584 　

    eISSN： 2644-1225

  19. Sparse Random Signals for Fast Convergence on Invertible Logic Peer-reviewed

    Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

    IEEE Access　9　62890-62898　2021

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/access.2021.3072048 　

    eISSN： 2169-3536

  20. Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN Peer-reviewed

    Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu

    IEEE Transactions on Circuits and Systems I: Regular Papers　68　(1)　67-76　2021/01

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/tcsi.2020.3030104 　

    ISSN： 1549-8328

    eISSN： 1558-0806

  21. Memristive Computational Memory Using Memristor Overwrite Logic (MOL) Peer-reviewed

    Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems　28　(11)　2370-2382　2020/11

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/tvlsi.2020.3011522 　

    ISSN： 1063-8210

    eISSN： 1557-9999

  22. Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic Peer-reviewed

    Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

    IEEE Access　8　188004-188014　2020/10

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/access.2020.3029576 　

    eISSN： 2169-3536

  23. High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter Peer-reviewed

    Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems　28　(10)　2171-2181　2020/10

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/tvlsi.2020.3005413 　

    ISSN： 1063-8210

    eISSN： 1557-9999

  24. Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices Peer-reviewed

    A. Tamakoshi, N. Onizawa, H. Yamagata, H. Fujita, T. Hanyu

    Proc. 18th IEEE International New Circuits and Systems Conference (NEWCAS)　283-286　2020/06

  25. In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning Peer-reviewed

    Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu

    IEEE Transactions on Circuits and Systems I: Regular Papers　67　(5)　1541-1550　2020/05

    Publisher: Institute of Electrical and Electronics Engineers (IEEE)

    DOI： 10.1109/tcsi.2019.2960383 　

    ISSN： 1549-8328

    eISSN： 1558-0806

  26. Design of an MTJ-based Nonvolatile Multi-context Ternary Content-Addressable Memory Peer-reviewed

    N. Onizawa, R. Arakawa, T. Hanyu

    Journal of Applied Logics　7　(1)　89-105　2020/01

  27. Fast Hardware-based Learning Algorithm for Binarized Perceptron Using CMOS Invertible Logic Peer-reviewed

    N. Onizawa, D. Shin, T. Hanyu

    Journal of Applied Logics　7　(1)　41-58　2020/01

  28. A Design Framework for Invertible Logic Peer-reviewed

    N. Onizawa, K. Nishino, S. Smithson, B. Meyer, W. Gross, H. Yamagata, H. Fujita, T. Hanyu

    2019 53rd Asilomar Conference on Signals, Systems, and Computers　2019/11

    Publisher: IEEE

    DOI： 10.1109/ieeeconf44664.2019.9048700 　

  29. Multi-Context TCAM-Based Selective Computing Architecture for a Low-Power NN International-journal Peer-reviewed

    R. Arakawa, N. Onizawa, T. Hanyu

    Proc. 26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS) 2019　117-118　2019/11

    DOI： 10.1109/ICECS46596.2019.8964869 　

  30. FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic International-journal Peer-reviewed

    D. Shin, N. Onizawa, T. Hanyu

    Proc. 26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS) 2019,　115-116　2019/11

    DOI： 10.1109/ICECS46596.2019.8965097 　

  31. Stochastic-Computing Based Branware LSI Towards an Intelligence Edge Invited Peer-reviewed

    N. ONizawa, W. J. Gross, T. Hanyu

    Proc. 26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS) 2019,　2019/11

  32. Efficient CMOS Invertible Logic Using Stochastic Computing Peer-reviewed

    S. Smithson, N. Onizawa, B. H. Meyer, W. J. Gross, T. Hanyu

    IEEE Trans. on Circuits and Syst. I Reg. Papers　66　(6)　2263-2274　2019/06

    DOI： 10.1109/TCSI.2018.2889732 　

  33. Brain-inspired computing

    Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

    Stochastic Computing: Techniques and Applications　185-199　2019/02/18

    Publisher: Springer International Publishing

    DOI： 10.1007/978-3-030-03730-7_10 　

  34. Study of Stochastic Invertible Multiplier Designs Peer-reviewed

    K. Nishino, S. Smituhson, N. Onizawa, B. H. Myer, W. J. Gross, H. Yamagata, H. Fujita, T. Hanyu

    Proc. IEEE International Conference on Electronics, Circuits & Systems (ICECS) 2018　649-650　2018/12

  35. MTJ-Based Asynchronous Circuits for Re-Initialization Free Computing against Power Failures Peer-reviewed

    N. Onizawa, M. Imai, T. Yoneda, T. Hanyu

    Microelectronics Journal　82　46-61　2018/12

    DOI： 10.1016/j.mejo.2018.10.012 　

  36. Networked Power-Gated MRAMs for Memory-Based Computing Peer-reviewed

    J.-P. Diguet, N. Onizawa, M. Rizk, M. J. Sepulveda, A. Baghdadi, T. Hanyu

    IEEE Trans. on Very Large Scale Integration (VLSI) Systems,　26　(12)　2696-2708　2018/12

    DOI： 10.1109/TVLSI.2018.2856458 　

  37. Application of Stochastic Computing in Brainware Invited Peer-reviewed

    W. J. Gross, N. Onizawa, K. Matsumiya, T. Hanyu

    Nonlinear Theory and Its Applications, IEICE,　E9-N　(4)　406-422　2018/10

    DOI： 10.1587/nolta.9.406 　

  38. An Area/Power-Aware 32-Channel Compressive Gammachirp Filterbank Chip Based on Hybrid Stochastic/Binary Computation Peer-reviewed

    N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, T. Hanyu

    Nonlinear Theory and Its Applications, IEICE,　E9-N　(4)　23-435　2018/10

    DOI： 10.1587/nolta.9.423 　

  39. An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation with Dynamic Voltage-Frequency-Length Scaling Peer-reviewed

    Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

    IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)　8　(3)　444-453　2018/09

    DOI： 10.1109/JETCAS.2018.2844329 　

  40. A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception Peer-reviewed

    Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross

    Journal of Signal Processing Systems　90　(5)　709-725　2018/05/01

    Publisher: Springer New York LLC

    DOI： 10.1007/s11265-016-1197-3 　

    ISSN： 1939-8115 1939-8018

  41. Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter Peer-reviewed

    S. Mukaida, N. Onizawa, T. Hanyu

    48th International Symposium on Multiple-Valued Logic (ISMVL)　156-161　2018/05

  42. High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure Peer-reviewed

    S. Koshita, N. Onizawa, M. Abe, T. Hanyu, M. Kawamata

    ISCAS 2018　2018/05

  43. Design of stochastic asymmetric compensation filters for auditory signal processing Peer-reviewed

    Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu

    2017 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2017 - Proceedings　2018-　1315-1319　2018/03/07

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/GlobalSIP.2017.8309174 　

  44. Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing Peer-reviewed

    M. Imai, N. Onizawa, T. Hanyu, T. Yoneda

    21st Workshop on Synthesis And System Integration of Mixed Information Technologies　283-288　2018/03

  45. MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures Peer-reviewed

    Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda

    Proceedings - International Symposium on Asynchronous Circuits and Systems　2017-　118-125　2017/11/03

    Publisher: IEEE Computer Society

    DOI： 10.1109/ASYNC.2017.11 　

    ISSN： 1522-8681

  46. Accuracy/energy-flexible stochastic configurable 2D gabor filter with instant-on capability Peer-reviewed

    Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

    ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference　43-46　2017/11/02

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/ESSCIRC.2017.8094521 　

  47. VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing Peer-reviewed

    Arash Ardakani, Francois Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　25　(10)　2688-2699　2017/10

    DOI： 10.1109/TVLSI.2017.2654298 　

    ISSN： 1063-8210

    eISSN： 1557-9999

  48. Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation Peer-reviewed

    Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　25　(10)　2724-2735　2017/10

    DOI： 10.1109/TVLSI.2017.2687404 　

    ISSN： 1063-8210

    eISSN： 1557-9999

  49. NoC-MRAM architecture for memory-based computing: Database-search case study Peer-reviewed

    M. Rizk, J-Ph. Diguet, N. Onizawa, A. Baghdadi, M. J. Sepulveda, Y. Akgul, V. Gripon, T. Hanyu

    Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017　309-312　2017/08/11

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/NEWCAS.2017.8010167 　

  50. Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications Peer-reviewed

    Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

    JAPANESE JOURNAL OF APPLIED PHYSICS　56　(8)　0802B7-1-0802B7-7　2017/08

    DOI： 10.7567/JJAP.56.0802B7 　

    ISSN： 0021-4922

    eISSN： 1347-4065

  51. High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation Peer-reviewed

    Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E100D　(8)　1592-1602　2017/08

    DOI： 10.1587/transinf.2016LOP0011 　

    ISSN： 1745-1361

  52. Evaluation of Stochastic Cascaded IIR Filters Peer-reviewed

    Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu

    Proceedings of The International Symposium on Multiple-Valued Logic　224-229　2017/06/30

    Publisher: IEEE Computer Society

    DOI： 10.1109/ISMVL.2017.25 　

    ISSN： 0195-623X

  53. Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors Peer-reviewed

    Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

    IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING　5　(2)　151-163　2017/04

    DOI： 10.1109/TETC.2016.2604083 　

    ISSN： 2168-6750

  54. Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing Peer-reviewed

    N. Onizawa, T. Hanyu

    Japanese Journal of Applied Physics　56　(3)　04CF12.1-04CF12.6　2017/03

    Publisher: Institute of Physics

    DOI： 10.7567/JJAP.56.04CF12 　

    ISSN： 0021-4922

    More details Close

    A soft/write-error-resilient nonvolatile flip-flop (NVFF) using three-terminal magnetic tunnel junctions (MTJs) is presented. The proposed NVFF exploits a redundant structure with a majority bit implicitly stored, which is tolerant to soft errors including both single-event transients (SETs) and single-event upsets (SEUs). For write-error resilience, all the bits of the redundant MTJs are written using the majority bit with a shared write-current path, exhibiting 1-bit soft-error correction and 1-bit write-error masking. In addition, the shared writing scheme reduces the number of write-current paths to one-third of that with a redundant NVFF with 1-bit soft/write-error masking. Using 65 nm CMOS/MTJ technologies, the proposed NVFF achieves a few orders-of-magnitude reduction in the failure in time (FIT), a 31% reduction in the transistor count, and a 65% reduction in the write energy in comparison with the redundant NVFF.

  55. Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor Invited Peer-reviewed

    Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui

    PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)　548-553　2017

    DOI： 10.23919/DATE.2017.7927048 　

    ISSN： 1530-1591

  56. Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing Peer-reviewed

    Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno

    PROCEEDINGS OF THE IEEE　104　(10)　1844-1863　2016/10

    DOI： 10.1109/JPROC.2016.2574939 　

    ISSN： 0018-9219

    eISSN： 1558-2256

  57. Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips Peer-reviewed

    Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu

    IEEE TRANSACTIONS ON NANOTECHNOLOGY　15　(5)　705-714　2016/09

    DOI： 10.1109/TNANO.2015.2511151 　

    ISSN： 1536-125X

    eISSN： 1941-0085

  58. A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing Peer-reviewed

    N. Onizawa, T. Hanyu

    2016 International Conference on Solid State Devices and Materials (SSDM)　79-80　2016/09

  59. Power-Gated Single-Track Asynchronous Circuits Using Three-Terminal MTJ-Based Nonvolatile Devices for Energy Harvesting Systems Peer-reviewed

    T. Yoneda, N. Onizawa, M. Imai, T. Hanyu

    22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Fresh Idea Track　9-10　2016/05

  60. Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks Peer-reviewed

    Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross

    IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS　6　(1)　13-24　2016/03

    DOI： 10.1109/JETCAS.2016.2528721 　

    ISSN： 2156-3357

  61. Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory Peer-reviewed

    N. Onizawa, N. Sakimura, R. Nebashi, T. Sugibayashi, T. Hanyu

    JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　26　(1-2)　125-140　2016

    ISSN： 1542-3980

    eISSN： 1542-3999

  62. Gammatone Filter Based on Stochastic Computation Peer-reviewed

    Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu

    2016 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING PROCEEDINGS　1036-1040　2016

    DOI： 10.1109/ICASSP.2016.7471833 　

    ISSN： 1520-6149

  63. Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation Peer-reviewed

    Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

    2016 IEEE 46TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2016)　223-228　2016

    DOI： 10.1109/ISMVL.2016.40 　

    ISSN： 0195-623X

  64. Redundant STT-MTJ-Based Nonvolatile Flip-Flops for Low Write-Error-Rate Operations Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　1-4　2016

    DOI： 10.1109/NEWCAS.2016.7604792 　

    ISSN： 2472-467X

  65. VLSI Implementation of Deep Neural Networks Using Integral Stochastic Computing Peer-reviewed

    Arash Ardakani, Fracois Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

    2016 9TH INTERNATIONAL SYMPOSIUM ON TURBO CODES AND ITERATIVE INFORMATION PROCESSING (ISTC)　216-220　2016

    DOI： 10.1109/ISTC.2016.7593108 　

    ISSN： 2165-4700

  66. Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing Invited Peer-reviewed

    Takahiro Hanyu, Masanori Natsui, Daisuke Suzuki, Akira Mochizuki, Naoya Onizawa, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno

    2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015　57-59　2015/11/20

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/S3S.2015.7333502 　

  67. Gabor Filter Based on Stochastic Computation Peer-reviewed

    Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

    IEEE SIGNAL PROCESSING LETTERS　22　(9)　1224-1228　2015/09

    DOI： 10.1109/LSP.2015.2392123 　

    ISSN： 1070-9908

    eISSN： 1558-2361

  68. Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks Peer-reviewed

    Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　23　(4)　642-653　2015/04

    DOI： 10.1109/TVLSI.2014.2316733 　

    ISSN： 1063-8210

    eISSN： 1557-9999

  69. Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm Invited Peer-reviewed

    Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki

    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)　1006-+　2015

    ISSN： 1530-1591

  70. Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors Peer-reviewed

    Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu

    2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　109-114　2015

    DOI： 10.1109/ISMVL.2015.28 　

    ISSN： 0195-623X

  71. Design of an STT-MTJ Based True Random Number Generator Using Digitally Controlled Probability-Locked Loop Peer-reviewed

    Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu

    2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　1-4　2015

    DOI： 10.1109/NEWCAS.2015.7182089 　

    ISSN： 2472-467X

  72. Frequency-Flexible Stochastic Gabor Filter Peer-reviewed

    Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

    2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP)　458-462　2015

    DOI： 10.1109/ICDSP.2015.7251914 　

  73. A Sudden Power-Outage Resilient Nonvolatile Microprocessor for Immediate System Recovery Peer-reviewed

    Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

    PROCEEDINGS OF THE 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 15)　39-44　2015

    DOI： 10.1109/NANOARCH.2015.7180584 　

    ISSN： 2327-8218

  74. Scaled IIR Filter Based on Stochastic Computation Peer-reviewed

    Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu

    2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)　297-300　2015

    DOI： 10.1109/MWSCAS.2015.7282118 　

    ISSN： 1548-3746

  75. Stochastic Implementation of the Disparity Energy Model for Depth Perception Peer-reviewed

    Kaushik Boga, Naoya Onizawa, Francois Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross

    2015 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2015)　1-6　2015

    DOI： 10.1109/SiPS.2015.7344982 　

  76. Multiple-Event-Transient Soft-Error Gate-Level Simulator for Harsh Radiation Environments Peer-reviewed

    Akira Mochizuki, Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

    TENCON 2015 - 2015 IEEE REGION 10 CONFERENCE　1658.1-1658.6　2015

    ISSN： 2159-3442

  77. Stochastic Implementation of the Disparity Energy Model for Depth Perception Peer-reviewed

    Kaushik Boga, Naoya Onizawa, Francois Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross

    2015 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2015)　90　(5)　709-725　2015

    DOI： 10.1007/s11265-016-1197-3 　

  78. Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories Peer-reviewed

    Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross

    IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation　133-138　2014/12/15

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/SiPS.2014.6986075 　

    ISSN： 1520-6130

  79. Challenge of MOS/MTJ-Hybrid Nonvolatile Logic-in-Memory Architecture in Dark-Silicon Era Invited Peer-reviewed

    Takahiro Hanyu, Daisuke Suzuki, Akira Mochizuki, Masanori Natsui, Naoya Onizawa, Tadahiko Sugibayashi, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno

    2014 IEEE International Electron Devices Meeting (IEDM2014)　28.2.1-28.2.3　2014/12

    DOI： 10.1109/IEDM.2014.7047124 　

  80. A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture Peer-reviewed

    Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross

    IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS　4　(4)　460-474　2014/12

    DOI： 10.1109/JETCAS.2014.2361061 　

    ISSN： 2156-3357

  81. Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model Peer-reviewed

    Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E97D　(9)　2286-2295　2014/09

    DOI： 10.1587/transinf.2013LOP0010 　

    ISSN： 1745-1361

  82. Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks Peer-reviewed

    Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross

    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY　76　(3)　235-247　2014/09

    DOI： 10.1007/s11265-014-0886-z 　

    ISSN： 1939-8018

    eISSN： 1939-8115

  83. Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model Peer-reviewed

    Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY　76　(2)　185-194　2014/08

    DOI： 10.1007/s11265-013-0854-z 　

    ISSN： 1939-8018

    eISSN： 1939-8115

  84. High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs Peer-reviewed

    Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E97D　(6)　1546-1556　2014/06

    DOI： 10.1587/transinf.E97.D.1546 　

    ISSN： 1745-1361

  85. High-Throughput Compact Delay-Insensitive Asynchronous NoC Router Peer-reviewed

    Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu

    IEEE TRANSACTIONS ON COMPUTERS　63　(3)　637-649　2014/03

    DOI： 10.1109/TC.2013.81 　

    ISSN： 0018-9340

    eISSN： 1557-9956

  86. High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism Peer-reviewed

    Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS　61　(3)　865-876　2014/03

    DOI： 10.1109/TCSI.2013.2283997 　

    ISSN： 1549-8328

    eISSN： 1558-0806

  87. A compact soft-error tolerant asynchronous TCAM based on a transistor/magnetic-tunnel-junction hybrid dual-rail word structure Peer-reviewed

    Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

    Proceedings - International Symposium on Asynchronous Circuits and Systems　1-8　2014

    Publisher: IEEE Computer Society

    DOI： 10.1109/ASYNC.2014.9 　

    ISSN： 1522-8681

  88. Soft-Delay-Error Evaluation in Content-Addressable Memory Peer-reviewed

    Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu

    2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014)　220-225　2014

    DOI： 10.1109/ISMVL.2014.46 　

    ISSN： 0195-623X

  89. Associative Memories Based on Multiple-Valued Sparse Clustered Networks Peer-reviewed

    Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

    2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014)　208-213　2014

    DOI： 10.1109/ISMVL.2014.44 　

    ISSN： 0195-623X

  90. Design of a Soft-Error Tolerant 9-Transistor/6-Magnetic-Tunnel-Junction Hybrid Cell Based Nonvolatile TCAM Peer-reviewed

    Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

    2014 IEEE 12TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　193-196　2014

    DOI： 10.1109/NEWCAS.2014.6934016 　

    ISSN： 2472-467X

  91. Analog-to-Stochastic Converter Using Magnetic-Tunnel Junction Devices Peer-reviewed

    Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu

    2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH)　59-64　2014

    DOI： 10.1109/NANOARCH.2014.6880490 　

    ISSN： 2327-8218

  92. Highly Reliable Single-Ended Current-Mode Circuit for an Inter-Chip Asynchronous Communication Link Peer-reviewed

    Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu

    2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)　683-686　2014

  93. Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element Peer-reviewed

    Naoya Onizawail, Takahiro Hanyu

    IEICE ELECTRONICS EXPRESS　11　(24)　20141017　2014

    DOI： 10.1587/elex.11.20141017 　

    ISSN： 1349-2543

  94. Probabilistic Search Schemes for High-Speed Low-Power Content-Addressable Memories Peer-reviewed

    N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, T. Hanyu

    2013 International Conference on Analog VLSI Circuit　100-105　2013/10

  95. Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links Peer-reviewed

    Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E96D　(9)　1952-1961　2013/09

    DOI： 10.1587/transinf.E96.D.1952 　

    ISSN： 0916-8532

    eISSN： 1745-1361

  96. Control-Information Sharing Asynchronous Fine-Grained Power-Gating Techniques and Its Application to On-Chip Routers Peer-reviewed

    A. Matsumoto, T. Kawano, N. Onizawa, T. Hanyu

    IEICE Trans. on Electronics　J96-C　(5)　73-84　2013/05/01

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 1345-2827

  97. High-throughput CAM based on a synchronous overlapped search scheme Peer-reviewed

    Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

    IEICE ELECTRONICS EXPRESS　10　(7)　20130148　2013

    DOI： 10.1587/elex.10.20130148 　

    ISSN： 1349-2543

  98. REDUCED-COMPLEXITY BINARY-WEIGHT-CODED ASSOCIATIVE MEMORIES Peer-reviewed

    Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross

    2013 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING (ICASSP)　2523-2527　2013

    DOI： 10.1109/ICASSP.2013.6638110 　

    ISSN： 1520-6149

  99. A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems Peer-reviewed

    Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

    2013 IEEE 19TH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC)　8-15　2013

    DOI： 10.1109/ASYNC.2013.16 　

    ISSN： 1522-8681

  100. Lowering error floors in stochastic decoding of ldpc codes based on wire-delay dependent asynchronous updating Peer-reviewed

    Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

    Proceedings of The International Symposium on Multiple-Valued Logic　254-259　2013

    DOI： 10.1109/ISMVL.2013.35 　

    ISSN： 0195-623X

  101. A Low-Power Content-Addressable Memory Based on Clustered-Sparse Networks Peer-reviewed

    Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross

    PROCEEDINGS OF THE 2013 IEEE 24TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP 13)　305-308　2013

    DOI： 10.1109/ASAP.2013.6567594 　

    ISSN： 2160-0511

  102. Low-Power Area-Efficient Large-Scale IP Lookup Engine Based on Binary-Weighted Clustered Networks Peer-reviewed

    Naoya Onizawa, Warren J. Gross

    2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC)　1-8　2013

    DOI： 10.1145/2463209.2488801 　

    ISSN： 0738-100X

  103. Selective Decoding in Associative Memories Based on Sparse-Clustered Networks Invited Peer-reviewed

    Hooman Jarollahi, Naoya Onizawa, Warren J. Gross

    2013 IEEE GLOBAL CONFERENCE ON SIGNAL AND INFORMATION PROCESSING (GLOBALSIP)　1270-1273　2013

    DOI： 10.1109/GlobalSIP.2013.6737140 　

    ISSN： 2376-4066

  104. Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling Peer-reviewed

    Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E95A　(6)　1018-1029　2012/06

    DOI： 10.1587/transfun.E95.A.1018 　

    ISSN： 1745-1337

  105. Clockless stochasic decoding of low-density parity-check codes Peer-reviewed

    N. Onizawa, W. J. Gross, T. Hanyu, V. C. Gaudet

    IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation　143-148　2012

    DOI： 10.1109/SiPS.2012.53 　

    ISSN： 1520-6130

  106. Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes Peer-reviewed

    Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross

    2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　92-97　2012

    DOI： 10.1109/ISMVL.2012.35 　

    ISSN： 0195-623X

  107. Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links Peer-reviewed

    Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

    2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　13-18　2012

    DOI： 10.1109/ISMVL.2012.51 　

    ISSN： 0195-623X

  108. Architecture and Implementation of an Associative Memory Using Sparse Clustered Networks Peer-reviewed

    Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross

    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)　2901-2904　2012

    DOI： 10.1109/ISCAS.2012.6271922 　

    ISSN： 0271-4302

  109. High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism Peer-reviewed

    Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu

    2012 18TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC)　41-48　2012

    DOI： 10.1109/ASYNC.2012.25 　

    ISSN： 1522-8681

  110. CLOCKLESS STOCHASIC DECODING OF LOW-DENSITY PARITY-CHECK CODES Peer-reviewed

    N. Onizawa, W. J. Gross, T. Hanyu, V. C. Gaudet

    2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS)　143-148　2012

    DOI： 10.1109/SiPS.2012.53 　

    ISSN： 2162-3562

  111. Multi-chip NoCs for automotive applications Peer-reviewed

    Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

    Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC　105-110　2012

    DOI： 10.1109/PRDC.2012.20 　

    ISSN： 1541-0110

  112. Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding Peer-reviewed

    Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS　58　(8)　1933-1943　2011/08

    DOI： 10.1109/TCSI.2011.2107271 　

    ISSN： 1549-8328

  113. Accurate asynchronous network-on-chip simulation based on a delay-aware model Peer-reviewed

    Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

    Lecture Notes in Electrical Engineering　105　17-30　2011

    DOI： 10.1007/978-94-007-1488-5_2 　

    ISSN： 1876-1100 1876-1119

  114. Adjacent-state monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system Peer-reviewed

    Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

    Proceedings - IEEE International Symposium on Circuits and Systems　2067-2070　2011

    DOI： 10.1109/ISCAS.2011.5938004 　

    ISSN： 0271-4310

  115. Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring Peer-reviewed

    Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

    2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)　776-781　2011

    ISSN： 1530-1591

  116. Adjacent-State Monitoring Based Fine-Grained Power-Gating Scheme for a Low-Power Asynchronous Pipelined System Peer-reviewed

    Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

    2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)　2067-2070　2011

    DOI： 10.1109/ISCAS.2011.5938004 　

    ISSN： 0271-4302

  117. Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links Peer-reviewed

    Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

    2011 41ST IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　236-241　2011

    DOI： 10.1109/ISMVL.2011.30 　

    ISSN： 0195-623X

  118. Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E93D　(8)　2089-2099　2010/08

    DOI： 10.1587/transinf.E93.D.2089 　

    ISSN： 1745-1361

  119. Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet

    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　18　(3)　482-489　2010/03

    DOI： 10.1109/TVLSI.2008.2011360 　

    ISSN： 1063-8210

  120. High-Throughput Protocol Converter Based on an Independent Encoding/Decoding Scheme for Asynchronous Network-on-Chip Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS　157-160　2010

    DOI： 10.1109/ISCAS.2010.5538027 　

    ISSN： 0271-4302

  121. One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control Peer-reviewed

    Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

    40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010　211-216　2010

    DOI： 10.1109/ISMVL.2010.47 　

    ISSN： 0195-623X

  122. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model Peer-reviewed

    Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

    IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010)　357-362　2010

    DOI： 10.1109/ISVLSI.2010.45 　

    ISSN： 2159-3469

    eISSN： 2159-3477

  123. High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet

    IEICE TRANSACTIONS ON ELECTRONICS　E92C　(6)　867-874　2009/06

    DOI： 10.1587/transele.E92.C.867 　

    ISSN： 1745-1353

  124. 双方向シングルトラック非同期転送方式に基づく高速・低電力LDPCデコーダLSIの構成 Invited

    鬼沢直哉, 羽生貴弘, Vincent Gaudet

    LSIとシステムのワークショップ2009講演論文集　354-356　2009/05

  125. High-Performance Asynchronous Intra-Chip Communication Link Based on a Multiple-Valued Current-Mode Single-Track Scheme Peer-reviewed

    Yo Ohtake, Naoya Onizawa, Takahiro Hanyu

    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5　1000-1003　2009

    DOI： 10.1109/ISCAS.2009.5117927 　

  126. Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    ISMVL: 2009 39TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　36-41　2009

    DOI： 10.1109/ISMVL.2009.44 　

  127. Asynchronous Data-Transfer Interface for an Interleaver in Fully-Parallel Low-Density Parity-Check Decoders Invited

    Naoya Onizawa, Takahiro Hanyu

    Proceedings of the 1st Student Organizing International Mini-Conference on Information Electronics Systems　1　(S2K-4)　131-132　2008/10

  128. Asynchronous Multiple-Valued Data Transfer and Its Application Invited

    Tomoyoshi Funazaki, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

    Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information　186　2008/10

  129. 電流モードsingle-track方式に基づく非同期データ転送の高速化 Invited

    大竹遥, 鬼沢直哉, 松本敦, 羽生貴弘

    平成20年度電気関係学会東北支部連合大会講演論文集　(2J18)　370　2008/08

  130. Power-aware asynchronous peer-to-peer duplex communication system based on multiple-valued one-phase signaling Peer-reviewed

    Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu

    IEICE TRANSACTIONS ON ELECTRONICS　E91C　(4)　581-588　2008/04

    DOI： 10.1093/ietele/e91-c.4.581 　

    ISSN： 1745-1353

  131. High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit Peer-reviewed

    Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu

    Proceedings of The International Symposium on Multiple-Valued Logic　70-75　2008

    DOI： 10.1109/ISMVL.2008.12 　

    ISSN： 0195-623X

  132. 多値非同期データ転送方式に基づく高性能LDPCデコーダLSIの実現 Invited

    鬼沢直哉, 羽生貴弘, Vincent Gaudet

    第11回システムLSIワークショップ講演資料集およびポスター資料集　272-274　2007/11

  133. Implementation of an Asynchronous LDPC Decoder Chip Using Multiple-Valued Duplex Interleaving Peer-reviewed

    N. Onizawa, T. Hanyu, V.C. Gaudet

    2007 Analog Decoding Workshop　2007/05

  134. 3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm Peer-reviewed

    Naoya Onizawa, Tomokazu Ikeda, Takahiro Hanyu, Vincent C. Gaudet

    2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3　182-+　2007

    DOI： 10.1109/MWSCAS.2007.4488574 　

    ISSN： 1548-3746

  135. Automatic Place and Route Scheme in Multiple-Valued Current-Mode Circuit Design

    Tasuku Nagai, Tomohiro Takahashi, Naoya Onizawa, Takahiro Hanyu

    Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.　57-58　2006/11

    More details Close

    通研インポート200703

  136. Design and evaluation of a NULL-convention circuit based on dual-rail current-mode differential logic Peer-reviewed

    Naoya Onizawa, Takahiro Hanyu

    IEICE TRANSACTIONS ON ELECTRONICS　E89C　(11)　1575-1580　2006/11

    DOI： 10.1093/ietele/e89-c.11.1575 　

    ISSN： 1745-1353

  137. 隣接データの類似性に着目した高速LDPC復号化とその評価

    池田智和, 鬼沢直哉, 羽生貴弘

    平成18年度電気関係学会東北支部連合大会講演論文集　70　2006/08

    More details Close

    通研インポート200703

  138. Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders Peer-reviewed

    N Onizawa, A Mochizuki, T Hanyu, VC Gaudet

    35TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　138-143　2005

    ISSN： 0195-623X

  139. Differential operation oriented multiple-valued encoding and circuit realization for asynchronous data transfer Peer-reviewed

    T Takahashi, N Onizawa, T Hanyu

    IEICE TRANSACTIONS ON ELECTRONICS　E87C　(11)　1928-1934　2004/11

    ISSN： 1745-1353

Show all ︎Show first 5

Misc. 28

  1. CMOSインバーティブルロジック［Ⅲ・完］――ハードウェア実現と応用例―― Invited

    鬼沢直哉

    電子情報通信学会学会誌　106　(1)　58-65　2023/01

  2. CMOSインバーティブルロジック［Ⅱ］――設計手法とツール―― Invited

    鬼沢直哉

    電子情報通信学会学会誌　105　(12)　1458-1465　2022/12

  3. CMOSインバーティブルロジック［I］――確率的双方向計算手法の基礎―― Invited

    鬼沢直哉

    電子情報通信学会学会誌　105　(10)　1241-1247　2022/10

  4. Energy-efficient brainware LSI based on stochastic computing Invited

    N. Onizawa, K. Matsumiya, T. Hanyu

    IEICE Fundamental Review　11　(1)　28-39　2017/07

    Publisher: IEICE

    DOI： 10.1587/essfr.11.1_28 　

  5. Stochastic Computation for Energy-Efficient Brainware LSI

    30　202-207　2017/05/11

    Publisher: [電子情報通信学会]

  6. Measurement of Magnitude Response of FIR Filters Based on Stochastic Computation

    30　38-40　2017/05/11

    Publisher: [電子情報通信学会]

  7. On Measurement Methods of Frequency Magnitude Responses for Digital Filters Based on Stochastic Computation

    2017　(19)　1-6　2017/03/13

    Publisher: 電気学会

  8. 視覚的注意計算モデルのハードウェア実装に向けた基礎的考察

    西野海斗, 鬼沢直哉, 松宮一道, 塩入論, 羽生貴弘

    電気関係学会東北支部連合大会講演論文集(CD-ROM)　2017　2017

  9. Hardware Implementation of Stochastic Gammatone Filter

    116　(95)　29-34　2016/06/16

    Publisher: 電子情報通信学会

    ISSN： 0913-5685

  10. Design of a Stochastic Gabor Filter for Highly Parallel Feature-Extraction Hardware

    115　(318)　35-40　2015/11/20

    Publisher: 電子情報通信学会

    ISSN： 0913-5685

  11. C-12-27 Design of an MTJ-Based True Random Number Generator with Probability-Variation Suppressing

    Oosawa Satoshi, Konishi Takayuki, Onizawa Naoya, Hanyu Takahiro

    Proceedings of the IEICE General Conference　2015　(2)　88-88　2015/02/24

    Publisher: The Institute of Electronics, Information and Communication Engineers

  12. Nonvolatile Logic-in-Memory Architecture and Its Application to Low-Power VLSI Systems

    羽生貴弘, 羽生貴弘, 羽生貴弘, 鈴木大輔, 鈴木大輔, 望月明, 望月明, 夏井雅典, 夏井雅典, 夏井雅典, 鬼沢直哉, 鬼沢直哉, 鬼沢直哉, 杉林直彦, 池田正二, 池田正二, 池田正二, 遠藤哲郎, 遠藤哲郎, 遠藤哲郎, 大野英男, 大野英男, 大野英男

    電子情報通信学会技術研究報告　115　(6(ICD2015 1-15))　2015

    ISSN： 0913-5685

  13. Fault-Tolerant Logical Integrated Circuits Based on Stochastic Computation

    KATAGIRI Daisaku, ONIZAWA Naoya, HANYU Takahiro

    IEICE technical report. Dependable computing　114　(22)　27-31　2014/04/25

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    This paper introduces fault-tolerant logical integrated circuits based on stochastic computation. In the stochastic computation realized in a probabilistic domain, a probability is represented by a Bernoulli sequence that consists of a random sequence of bits. If an error occurs that flips a bit in the sequence, the probability is rarely affected because it is represented by the frequency of ones or zeros in the sequence. As a design example, an edge-detection circuit based on stochastic computation is designed using Verilog-HDL that shows comparison results with a conventional edge-detection circuit.

  14. Low-Power IP Lookup LSI Based on Sparse Clustered Networks

    ONIZAWA Naoya, GROSS Warren, HANYU Takahiro

    IEICE technical report. Circuits and systems　113　(463)　193-198　2014/03/06

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    In this paper, a novel architecture for low-power IP lookup engines is introduced. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry brute-force search of input addresses in TCAMs. The proposed hardware is designed under TSMC 65nm CMOS technology and is evaluated using HSPICE to show the energy efficiency compared to a conventional approach.

  15. Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

    KAWANO Takao, ONIZAWA Naoya, Matsumoto Atsushi, HANYU Takahiro

    Technical report of IEICE. VLD　111　(324)　215-220　2011/11/28

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    In this paper, a new fine-grained power-gating technique is proposed. Fine-grained power-gating technique has the potential to much leakage power dissipation of idle circuit blocks. A fine-grained power-gating controller tends to be large because of complexity of power-gating control. Since asynchronous signals generated by asynchronous controllers are local control signals, these signals indicate conditions of circuit blocks. Therefore, a fine-grained power-gating technique with a small power-gating controller is realized by sharing the asynchronous controller in asynchronous pipelined system. The proposed power-gating technique is applied to a Network-on-Chip (NoC) router. As a result, leakage power reduction of the NoC router is realized.

  16. Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

    KAWANO Takao, ONIZAWA Naoya, Matsumoto Atsushi, HANYU Takahiro

    IEICE technical report. Dependable computing　111　(325)　215-220　2011/11/28

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    In this paper, a new fine-grained power-gating technique is proposed. Fine-grained power-gating technique has the potential to much leakage power dissipation of idle circuit blocks. A fine-grained power-gating controller tends to be large because of complexity of power-gating control. Since asynchronous signals generated by asynchronous controllers are local control signals, these signals indicate conditions of circuit blocks. Therefore, a fine-grained power-gating technique with a small power-gating controller is realized by sharing the asynchronous controller in asynchronous pipelined system. The proposed power-gating technique is applied to a Network-on-Chip (NoC) router. As a result, leakage power reduction of the NoC router is realized.

  17. Fault-Detectable 2-Color Code for Asynchronous Bidirectional Communication Links

    MATSUMOTO Atsushi, ONIZAWA Naoya, HANYU Takahiro

    IEICE technical report. Dependable computing　111　(325)　37-42　2011/11/28

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    In this paper, we propose an encoding scheme for multiple-valued two-color data representation with open-wire fault detectability in bidirectional asynchronous links. Correct signal states are detected by using the summation of current signals in a data transmission based on multiple-valued encoding. Therefore, by using proposed "Complementary Encoding" based data representation, a data transmission is always stopped when there is any open-wire fault in the link. As a result, open-wire fault can be detected. In this paper, mathematical proof of open-wire fault detectability by using proposed encoding is discussed. Furthermore, as a simple application, an asynchronous bidirectional link based on proposed encoding is demonstrated.

  18. Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

    2011　(38)　1-6　2011/11/21

  19. C-12-10 非同期式チップ間リンク速度の定量的評価手法(センサ・有線通信,C-12.集積回路,一般セッション)

    鬼沢 直哉, 羽生 貴弘

    電子情報通信学会ソサイエティ大会講演論文集　2010　(2)　71-71　2010/08/31

    Publisher: 一般社団法人電子情報通信学会

  20. C-007 Asynchronous Communication Scheme based on Multiple-valued 1-color Encoding and Its Application toward Network-on-Chip

    Matsumoto Atsushi, Onizawa Naoya, Hanyu Takahiro

    9　(1)　385-386　2010/08/20

    Publisher: Forum on Information Technology

  21. Fault-Resilient Multiple-Valued Asynchronous Data-Transfer Scheme

    MATSUMOTO Atsushi, ONIZAWA Naoya, HANYU Takahiro

    IEICE technical report　110　(168)　7-11　2010/07/28

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    In this paper, we propose an asynchronous data-transmission scheme which is robust against a wire-fault on the communication links. Even if a wire-fault occurs, the quantity of data-transmission can be kept as same as it before the wire-fault by utilizing data representation of multiple-valued encoding which is defined on the rest non-fault wires. In other words, the capability of data-transmission before and after the wire-fault can be maintained in the proposed scheme. Furthermore, to clarify the usefulness of the proposed scheme, the detailed mechanism of the proposed scheme through the three-wire data-transmission and its hardware implementation example by utilizing multiple-valued current-mode circuit technique are shown.

  22. Accurate Asynchronous Network-on-Chip Simulation Based on Reactive Delay Model

    FUNAZAKI Tomoyoshi, ONIZAWA Naoya, MATSUMOTO Atsushi, HANYU Takahiro

    IEICE technical report　110　(3)　9-14　2010/04/06

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip(NoC)architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a reactive delay model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this "reactive delay" model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spidergon NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator.

  23. A-1-44 Design of Fully-Parallel LDPC Decoders Based on Stochastic Computation

    Onizawa Naoya, Hanyu Takahiro

    Proceedings of the IEICE General Conference　2010　44-44　2010/03/02

    Publisher: The Institute of Electronics, Information and Communication Engineers

  24. C-036 Design of a Circuit-Level Verification Environment for Asynchronous Network-on-Chip

    Matsumoto Atsushi, Funazaki Tomoyosi, Onizawa Naoya, Hanyu Takahiro

    8　(1)　519-520　2009/08/20

    Publisher: Forum on Information Technology

  25. A robust on-chip asynchronous data-transfer scheme based on multi-level current-mode signalling

    ONIZAWA Naoya, MATSUMOTO Atsushi, HANYU Takahiro, YONEDA Tomohiro

    IEICE technical report　109　(169)　1-6　2009/07/29

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    This paper presents a robust on-chip asynchronous data-trasnfer circuit based on multi-level current-mode signalling under the power-supply/voltage and process variations. Since distance between two multi-level codewords which includes data and control information are minimized, the maximum logical value can be reduced with a correct asynchronous data transfer. Moreover, a logical value used for detection of an asynchronous signal is assigned a large amount of current in comparison that which is not used for detection, which increases a voltage margin of a unit logical value. In the circuit implementation, a compensation circuit with a characteristic which is inversely changed to that of an operation circuit under the power/voltage variations is closely placed on the operation circuit, thus the characteristic of the operation circuit becomes almost stable.

  26. C-12-8 Implementation of an LDPC Decoder LSI Based on Multiple-Valued Asynchronous Data-Transfer Scheme

    Onizawa Naoya, Hanyu Takahiro

    Proceedings of the IEICE General Conference　2007　(2)　87-87　2007/03/07

    Publisher: The Institute of Electronics, Information and Communication Engineers

  27. Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic

    ONIZAWA Naoya, HANYU Takahiro

    IEICE transactions on electronics　89　(11)　1575-1580　2006/11/01

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0916-8524

    More details Close

    A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18μm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

  28. Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer

    TAKAHASHI Tomohiro, ONIZAWA Naoya, HANYU Takahiro

    IEICE Trans. Electron., C　87　(11)　1928-1934　2004/11/01

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0916-8524

    More details Close

    This paper presents an asynchronous data transfer scheme using 2-color 2-phase dual-rail encoding based on a differential operation and its circuit realization. The proposed encoding enables seamless asynchronous data transfer without inserting a spacer, because each logic value is represented by two kinds of codewords with dual-rail, called "color" data. Since the difference x-x' between components of a codeword (x, x') becomes constant in every valid state, the data-arrival state can be detected by calculating the difference x-x'. From the viewpoint of circuit implementation, during the state transition, since the dual-rail x and x' are defined so as to transit differentially, the compatibility with a comparator using a differential amplifier becomes high, which results in reduction of the cycle time. It is evaluated using HSPICE simulation with a 0.18μm CMOS technology that communication speed using the proposed dual-rail encoding becomes 1.4 times faster than that using conventional dual-rail encoding.

Show all ︎Show first 5

Books and Other Publications 4

  1. Design and Applications of Emerging Computer Systems

    Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

    Springer　2024/01

    ISBN: 9783031424779

  2. Stochastic Computing: Techniques and Applications,

    N. Onizawa, W. J. Gross, T. Hanyu

    Springer　2019/02

    ISBN: 9783030037291

  3. 百花繚覧 vol. 1

    鬼沢 直哉

    東北大学出版　2019/01

    ISBN: 9784861633133

  4. VLSI 2010 Annual Symposium

    N. Onizawa, T. Funazaki, A. Matsumoto, T. Hanyu

    Springer　2012

    ISBN: 9789400714885

Presentations 34

  1. Few-Shot Learning に基づくエッジAIハードウェアの設計環境の構築に関する基礎的研究

    神田 凌輔, 鬼沢 直哉, 羽生 貴弘

    2024年度 電気関係学会東北支部連合大会　2024/08

  2. Brainware Information Processing Based on Stochastic Computing Invited

    Naoya Onizawa

    Conference, IMT Atlantique　2022/11

  3. Fast-Conversing Simulated Annealing of Ising Models Based on Integral Stochastic Computing Invited

    Naoya Onizawa

    Edge Intelligence Workshop 2022,　2022/09/20

  4. 最適化問題が実現する幸せな未来社会：量子と古典コンピューターの共創「古典コンピュータ ーによる最適化問題」 Invited

    鬼沢直哉

    第14回実践データ駆動科学オンラインセミナー　2022/09/02

  5. 大規模 SC-SA 法の高速求解向け FPGA 実装と評価

    口分田大芽, シントッキュ, 鬼沢直哉, 羽生貴弘

    2022 年度電気関係学会東北支部連合大会　2022/09

  6. Stochastic演算に基づくQMCによるアニーリング処理の高速化

    佐々木 遼真, 鬼沢 直哉, 羽生 貴弘

    2022年度 電気関係学会東北支部連合講演論文集　2022/08

  7. Integral Stochastic演算に基づくSimulated Annealing法の高速化

    勝木康太, シントッキュ, 鬼沢直哉, 羽生 貴弘

    2021年度電気関係学会東北支部連合大会講演論文集　2021/08/26

  8. In-Hardware Training Chip Based on CMOS Invertible Logic

    N. Onizawa

    The 7th International Symposium on Brainware LSI　2021/03/31

  9. CMOSインバーティブルロジックとその学習ハードウェアへの応用展開 Invited

    鬼沢直哉

    第42回IBISML研究会　2021/03/02

  10. 大規模CMOSインバーティブルロジック回路実現向け設計自動化ツールの構築

    加藤諒, 鬼沢直哉, 羽生 貴弘

    信学会第2種研究会「多値論理とその応用」　2021/01/09

  11. 大規模インバーティブルロジック回路実現へ向けた設計自動化手法

    加藤諒, 鬼沢直哉, 羽生 貴弘

    2020年度電気関係学会東北支部連合大会　2020/08/27

  12. Stochastic Computing for Brainware LSI Invited

    N. Onizawa

    2019 International Workshop on Emerging Technologies for Brainwrae LSI and Its Applications　2019/12/13

  13. Probabilistic learning algorithm based on CMOS invertible logic

    2019/11

  14. Design of MTJ-based true random number generator

    2019/09

  15. High-speed learning hardware based on CMOS invertible logic

    2019/08

  16. Multi-context TCAM for approximate computing

    2019年度電気関係学会東北支部連合大会　2019/08

  17. Stochastic Computing for Brainwrae LSI International-presentation Invited

    N. Onizawa, W. J. Gross, T. Hanyu

    26th IEEE International Symposium on Asynchronous Circuits and Systems, Special Session　2019/05/12

  18. Stochastic Computing for Brainware LSI International-presentation Invited

    N. Onizawa, S. Koshita, S. Sakamoto, M. Kawamata, T. Hanyu, W. J. Gross, T. Hanyu

    The 2019 RIKEN International Workshop on Neuromorphic Computing　2019/03/11

  19. Efficient CMOS Invertible Logic Using Stochastic Computing International-presentation

    N. Onizawa, S. C. Smithson, B. H. Meyer, W. J. Gross, T. Hanyu Naoya

    The 6th International Symposium on Brainware LSI　2019/03/02

  20. Energy-Efficient Brainwave LSI Based on Stochastic Computation Invited

    ONIZAWA Naoya

    2018/09/14

  21. ストカスティック演算に基づくインバーティブルロジック回路の構成

    西野海斗, 鬼沢直哉, 羽生貴弘

    2018年電子情報通信学会ソサイエティ大会　2018/09/12

  22. Energy-Efficient Configurable Search Hardware Based on Sparse Neural Networks International-presentation Invited

    ONIZAWA Naoya

    Energy-Efficient Configurable Search Hardware Based on Sparse Neural Networks　2018/05/11

  23. Energy-Efficient Brainware LSI Based on Stochastic Computation International-presentation Invited

    ONIZAWA Naoya

    2018 Emerging Technologies CMOS (ETCMOS)　2018/05/09

  24. 複数個の電圧電流変換特性を用いた低電力MTJベース真性乱数生成器の設計

    向田渉吾, 鬼沢直哉, 羽生貴弘

    信学会第2種研究会「多値論理とその応用」　2018/01/07

  25. Contextual Cueing Model に基づく実時間画像認識プリプロセッサの検討

    西野海斗, 鬼沢直哉, 袁正雄, 松宮一道, 塩入諭, 羽生貴弘

    信学会第2種研究会「多値論理とその応用」　2018/01/07

  26. Energy-Efficient Brainware LSI Based on Stochastic Computation International-presentation Invited

    ONIZAWA Naoya

    5th IEEE Global Conference on Signal and Information Processing (GlobalSIP)　2017/11/14

  27. ディジタル信号処理におけるストカスティック演算の課題 Invited

    越田俊介, 鬼沢直哉, 阿部正英, 羽生 貴弘, 川又政征

    2017年電子情報通信学会ソサイエティ大会　2017/09/12

  28. ストカスティック演算に基づく省面積・省エネルギー脳型LSI実現 Invited

    鬼沢直哉, 松宮一道, 羽生 貴弘

    2017年電子情報通信学会ソサイエティ大会　2017/09/12

  29. 視覚的注意計算モデルのハードウェア実装に向けた基礎的考察

    西野海斗, 鬼沢直哉, 松宮一道, 塩入諭, 羽生 貴弘

    平成29年度電気関係学会東北支部連合大会講演論文集　2017/08

  30. MTJ素子を用いた待機電力フリーの不揮発性非同期SRラッチの設計・評価

    向田渉吾, 鬼沢直哉, 羽生 貴弘

    平成29年度電気関係学会東北支部連合大会講演論文集　2017/08

  31. ストカスティック演算に基づく省エネルギー脳型LSI実現の展望 Invited

    鬼沢 直哉

    第30回回路とシステムのワークショップ　2017/05/11

  32. ストカスティック演算による脳型LSI実現の展望 Invited

    鬼沢 直哉

    IEEE広島支部共催講演会　2016/11/07

  33. CMOS/MTJ Hybrid Nonvolatile Processors Based on Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Applications International-presentation Invited

    ONIZAWA Naoya

    ECE seminar at McGill University　2016/06/23

  34. Stochastic Implementation of Gammatone Filters for Auditory Processing, International-presentation Invited

    ONIZAWA Naoya

    1st Workshop on Stochastic Computing and Related Topics　2016/06/20

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Industrial Property Rights 7

  1. 半導体装置

    羽生 貴弘, 望月 明, 鬼沢 直哉, 玉越 晃, 大野 英男

    Property Type: Patent

  2. 記憶装置

    羽生 貴弘, 鬼沢 直哉, 大野 英男

    Property Type: Patent

  3. 半導体記憶装置及びその駆動方法

    羽生 貴弘, 松永 翔雲, 鬼沢 直哉, ガウデット,ヴィンセント

    Property Type: Patent

  4. 半導体記憶装置

    羽生 貴弘, 松永 翔雲, 鬼沢 直哉, ガウデット,ヴィンセント

    特許第5998381号

    Property Type: Patent

  5. 非同期データ転送装置

    羽生 貴弘, 鬼沢 直哉, 松本 敦

    Property Type: Patent

  6. 非同期プロトコル変換装置

    羽生 貴弘, 鬼沢 直哉

    Property Type: Patent

  7. 非同期プロトコル変換装置

    羽生 貴弘, 鬼沢 直哉

    特許第5935105号

    Property Type: Patent

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Research Projects 9

  1. 自己修復型 Few-shot Learning アルゴリズムの FPGA 実装によるエッジ AI 高度化

    鬼沢直哉

    Offer Organization: 公益財団法人村田学術振興・教育財団

    System: 研究助成

    Institution: 東北大学

    2025/04 - 2027/03

  2. 確率ビットに基づく次世代省エネルギーコンピュータの実現に向けた回路アーキテクチャの研究

    鬼沢直哉

    Offer Organization: キオクシア

    System: 奨励研究

    Institution: 東北大学

    2025/06 - 2026/03

  3. 確率ビットに基づく次世代省エネルギーコンピュータの実現に向けた精度評価ベンチマークの開発

    鬼沢直哉

    Offer Organization: キオクシア

    System: 奨励研究

    Institution: 東北大学

    2024/06 - 2025/03

  4. Development of Quantum Monte-Carlo Hardware Based on Probabilistic Device Model

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    Category: Grant-in-Aid for Scientific Research (B)

    Institution: Tohoku University

    2021/04 - 2025/03

  5. Study of Invertible logic for edge-type learning hardware Competitive

    ONIZAWA Naoya

    Offer Organization: JST

    System: Basic Research Programs (Precursory Research for Embryonic Science and Technology :PRESTO)

    Category: PRESTO

    Institution: Tohoku University

    2018/10 - 2022/03

  6. Development of Dark Silicon Logic LSI for Brainware Computing

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (S)

    Category: Grant-in-Aid for Scientific Research (S)

    Institution: Tohoku University

    2016/05 - 2021/03

  7. Brainware Large-Scale Vision Hardware Based on Parallel Stochastic Computing

    ONIZAWA Naoya

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research

    Category: Grant-in-Aid for Challenging Exploratory Research

    Institution: Tohoku University

    2016/04 - 2019/03

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    Recently, brain-inspired vision processing provides better accuracy than human begins in specific applications. However, the current brain-inspired computing works well in only one application previously trained, and hence is lack of flexibility in unknown various applications, unlike human beings. In this study, a brain-inspired vision-processing filter is realized that can extract millions of different features, like human beings. In addition, as the hardware is implemented using stochastic computing that exhibits a similar behavior to human neurons, the power dissipation is reduced by 97% while maintaining the throughput in comparison with a traditional binary implementation.

  8. Design of Ultra-Low Power IP-Packet-Processing LSI Based on Probabilistic Computing

    Onizawa Naoya

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (A)

    Category: Grant-in-Aid for Young Scientists (A)

    Institution: Tohoku University

    2014/04 - 2018/03

    More details Close

    Recently, internet traffic has been expected to be rapidly increased. IP routers used as repeaters need to handle enormous packets while achieving high-speed and ultra-low power processing. In this research, a probabilistic-computing based partial search algorithm has been presented for IP packet processing. Compared with a conventional method that requires a brute-force search, the proposed method achieves the comparable search capability using the partial searching, leading to an order-of-magnitude reduction in power dissipation. As a result, this research results are summarized in 17 journals including well-known IEEE journals in the field and 38 conference presentations.

  9. 脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発

    羽生 貴弘, 米田 友洋, 今井 雅, 鬼沢 直哉

    Offer Organization: 日本学術振興会

    System: 科学研究費助成事業

    Category: 基盤研究(A)

    Institution: 東北大学

    2016/04/01 - 2017/03/31

    More details Close

    脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術を開発するために，初年度であるH28年度は，ダーク・シリコン非同期基本論理ゲート構成とその小規模演算回路の設計，並びにCMOS等価回路による原理動作検証を計画していた． 提案のダーク・シリコン非同期基本ゲートを検討し，いくつかの回路で動作シミュレーションを行った．シミュレーション環境としては，不揮発性素子であるMagnetic Tunnel Junction (MTJ)素子とCMOS回路を用いて，SPICEによるトランジスタレベルシミュレーションを行った．シミュレーションにより，基本的なパワーげティング動作までを確認した． また研究資料収集として，多値論理及びそのハードウェア実現に関する国際会議であるInternational Symposium on Multiple-Valued Logic (ISMVL)2016に出席をし，アルゴリズムからシステムレベルに至る脳型コンピューティグに関する知見を得た． 上記の提案回路の検討中に，重複応募中の基盤研究（S)が採択となったため，本基盤研究（A)としての研究はその時点で終了となった．ただし，基盤研究（S)と本基盤研究（A)の課題として，共通に「脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術の開発」としていたため，本基盤研究（A)での研究進捗は，そのまま基盤研究（S)に引き継ぐ形となった．

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