-
An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) 354-359 2105/07/28
-
手術ナビゲーションのための超音波画像からの3次元再構成の高精度化に関する研究
赤川 琢人, 張山 昌論, 下田 貢
日本コンピュータ外科学会誌 26 (2) 130-130 2024/10
Publisher:
(一社)日本コンピュータ外科学会
ISSN：
1344-9486
eISSN：
1884-5770
-
手術ナビゲーションのための超音波画像からの3次元再構成の高精度化に関する研究
赤川 琢人, 張山 昌論, 下田 貢
日本コンピュータ外科学会誌 26 (2) 130-130 2024/10
Publisher:
(一社)日本コンピュータ外科学会
ISSN：
1344-9486
eISSN：
1884-5770
-
肝切除におけるナビゲーションの展開 術中ナビゲーションのための3Dプリンターを用いたプローブアタッチメントの作成と術中超音波画像の3D画像構築の試み
下田 貢, 張山 昌論, 鈴木 修司
日本外科系連合学会誌 49 (3) 270-270 2024/05
Publisher:
日本外科系連合学会
ISSN：
0385-7883
eISSN：
1882-9112
-
ベイジアンネットワークを用いた胆嚢亜全摘術施行へのリスク評価
下田 貢, 張山 昌論, 鈴木 修司
日本臨床外科学会雑誌 84 (増刊) S231-S231 2023/10
Publisher:
日本臨床外科学会
ISSN：
1345-2843
eISSN：
1882-5133
-
Optimal Estimation of Resected Regions Considering Hepatic Veins
Kurusu Hiromi, Hariyama Masanori, Shimoda Mitsugi
Proceedings of the Japan Joint Automatic Control Conference 66 91-93 2023
Publisher:
The Japan Joint Automatic Control Conference
DOI：
10.11511/jacc.66.0_91
-
急性胆嚢炎診療の進歩、安全に患者を救うためには 急性胆嚢炎は胆嚢亜全摘術施行へのリスクとなる
下田 貢, 張山 昌論, 鈴木 修司
日本外科感染症学会雑誌 19 (1) 143-143 2022/10
Publisher:
(一社)日本外科感染症学会
ISSN：
1349-5755
eISSN：
2434-0103
-
AIを用いた腹腔鏡下胆嚢摘出術困難症例に対するbailout surgeryの術式選択の可能性
下田 貢, 張山 昌論, 鈴木 修司
日本外科学会定期学術集会抄録集 122回 SF-5 2022/04
Publisher:
(一社)日本外科学会
-
FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services
Mitsuhiro Okada, Takayuki Suzuki, Naoya Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
IEEE Transactions on Cloud Computing 10 (2) 1373-1385 2022/04/01
Publisher:
Institute of Electrical and Electronics Engineers ({IEEE})
DOI：
10.1109/TCC.2020.2969655
-
Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
The Journal of Supercomputing 78 (6) 8733-8750 2022/04
Publisher:
Springer Science and Business Media {LLC}
DOI：
10.1007/s11227-021-04242-0
-
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano
2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022) 2022
DOI：
10.1109/MWSCAS54063.2022.9859281
-
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory
Hasitha Muthumala Waidyasooriya, Hiroki Oshiyama, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki
IEEE Access 1-1 2022
Publisher:
Institute of Electrical and Electronics Engineers ({IEEE})
DOI：
10.1109/ACCESS.2022.3183993
-
ナビゲーション手術の現状と今後 肝切除術における超音波3D画像構築とナビゲーションシステムへの応用
下田 貢, 張山 昌論, 鈴木 修司
日本臨床外科学会雑誌 82 (増刊) S96-S96 2021/10
Publisher:
日本臨床外科学会
ISSN：
1345-2843
eISSN：
1882-5133
-
Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
IEEE Transactions on Emerging Topics in Computing 9 (4) 2019-2029 2021/10/01
Publisher:
Institute of Electrical and Electronics Engineers ({IEEE})
DOI：
10.1109/TETC.2019.2957177
-
Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators
Peer-reviewed
Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
The Journal of Supercomputing 2021/05/18
Publisher:
Springer Science and Business Media {LLC}
DOI：
10.1007/s11227-021-03859-5
-
腹腔鏡下胆嚢摘出術困難症例に対するBailout surgery移行判断のAIモデリング
下田 貢, 張山 昌論, 鈴木 修司
日本外科学会定期学術集会抄録集 121回 SF-4 2021/04
Publisher:
(一社)日本外科学会
-
A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
IEEE ACCESS 8 67929-67939 2020
DOI：
10.1109/ACCESS.2020.2985699
ISSN：
2169-3536
-
Development of new software enabling automatic identification of the optimal anatomical liver resectable region, incorporating preoperative liver function
International-journal
Peer-reviewed
Mitsugi Shimoda, Masanori Hariyama, Yukio Oshiro, Shuji Suzuki
ONCOLOGY LETTERS 18 (6) 6639-6647 2019/12
DOI：
10.3892/ol.2019.11006
ISSN：
1792-1074
eISSN：
1792-1082
-
Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation
Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Proceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019 164-170 2019/11/01
Publisher:
Institute of Electrical and Electronics Engineers Inc.
DOI：
10.1109/CANDAR.2019.00028
-
A memory-bandwidth-efficient word2vec accelerator using OpenCL for FPGA
Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 103-108 2019/11/01
Publisher:
Institute of Electrical and Electronics Engineers Inc.
DOI：
10.1109/CANDARW.2019.00026
-
OpenCL-based design of an FPGA accelerator for quantum annealing simulation
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki
JOURNAL OF SUPERCOMPUTING 75 (8) 5019-5039 2019/08
DOI：
10.1007/s11227-019-02778-w
ISSN：
0920-8542
eISSN：
1573-0484
-
FPGA-based acceleration of word2vec using OpenCL
Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa
Proceedings - IEEE International Symposium on Circuits and Systems 2019- 2019
Publisher:
Institute of Electrical and Electronics Engineers Inc.
DOI：
10.1109/ISCAS.2019.8702700
ISSN：
0271-4310
-
Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
IEEE ACCESS 7 53188-53201 2019
DOI：
10.1109/ACCESS.2019.2910824
ISSN：
2169-3536
-
Benchmarks for FPGA-Targeted High-Level-Synthesis
Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama
2019 SEVENTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR 2019) 232-238 2019
DOI：
10.1109/CANDAR.2019.00038
ISSN：
2379-1888
-
Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL
Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama
ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems 335-340 2018/11/01
Publisher:
Institute of Electrical and Electronics Engineers Inc.
DOI：
10.1109/ISPACS.2018.8923263
-
An FPGA accelerator for PatchMatch multi-view stereo using OpenCL
Peer-reviewed
Shunsuke Tatsumi, Masanori Hariyama, Koichi Ito, Takafumi Aoki
Journal of Real-Time Image Processing 1-13 2018/02/15
Publisher:
Springer Verlag
DOI：
10.1007/s11554-017-0745-9
ISSN：
1861-8200
-
Implementation of an FPGA Accelerator for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure
Peer-reviewed
Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) 1-12 2018/01/24
-
A System for Estimating Optimal Resected Liver Regions Considering Practical Surgical Constraints.
Peer-reviewed
Yaya Watanabe, Masanori Hariyama, Mitsugi Shimoda
2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)(ISPACS) 415-420 2018
Publisher:
IEEE
DOI：
10.1109/ISPACS.2018.8923304
-
Architecture of an FPGA-based heterogeneous system for code-search problems
Peer-reviewed
Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 10776 146-155 2018
Publisher:
Springer Verlag
DOI：
10.1007/978-3-319-69953-0_9
ISSN：
1611-3349 0302-9743
eISSN：
1611-3349
-
Automatic optimization of OpenCL-based stencil codes for FPGAs
Peer-reviewed
Tsukasa Endo, Hasitha Muthumala Waidyasooriya, Masanori Hariyama
Studies in Computational Intelligence 721 75-89 2018
Publisher:
Springer Verlag
DOI：
10.1007/978-3-319-62048-0_6
ISSN：
1860-949X
-
Architecture of an FPGA accelerator for LDA-based inference
Peer-reviewed
Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki
Proceedings - 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017 357-362 2017/08/29
Publisher:
Institute of Electrical and Electronics Engineers Inc.
DOI：
10.1109/SNPD.2017.8022746
-
BEHAVIOR ANALYSIS OF CHILDREN USING A HIGH-ACCURACY GPS SYSTEM
Invited
M. Hariyama, N. Miyamoto, M. Koshiba, H. Watanabe, S. Ito, S. Shimazaki, T. Kubota, M. Senda, S. Taniguchi
12th International Neuroscience and Biological Psychiatry Regional ISBS Conference 2017/07/25
-
OpenCL-Based Implementation of an FPGA Accelerator for Molecular Dynamics Simulation
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
Information Engineering Express, International Institute of Applied Informatics 3 (2) 11-23 2017/07
-
OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 28 (5) 1390-1402 2017/05
DOI：
10.1109/TPDS.2016.2614981
ISSN：
1045-9219
eISSN：
1558-2183
-
An FPGA accelerator for molecular dynamics simulation using OpenCL
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara
International Journal of Networked and Distributed Computing 5 (1) 52-61 2017/01/01
Publisher:
Atlantis Press
DOI：
10.2991/ijndc.2017.5.1.6
ISSN：
2211-7946 2211-7938
-
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera
International Journal of Reconfigurable Computing 2017 2017
Publisher:
Hindawi Limited
DOI：
10.1155/2017/6817674
ISSN：
1687-7209 1687-7195
-
Evaluation of an openCL-based FPGA platform for particle filter
Peer-reviewed
Shunsuke Tatsumi, Masanori Hariyama, Norikazu Ikoma
Journal of Advanced Computational Intelligence and Intelligent Informatics 20 (5) 743-754 2016/09/01
Publisher:
Fuji Technology Press
DOI：
10.20965/jaciii.2016.p0743
ISSN：
1883-8014 1343-0130
-
Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 27 (5) 1358-1372 2016/05
DOI：
10.1109/TPDS.2015.2444376
ISSN：
1045-9219
eISSN：
1558-2183
-
Hardware-Oriented Succinct-Data-Structure for Text Processing Based on Block-Size-Constrained Compression
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama
International Journal of Computer Information Systems and Industrial Management Applications 8 1-11 2016/01
-
FPGA-Based Deep-Pipelined Architecture for FDTD Acceleration Using OpenCL
Peer-reviewed
Hasitha Muthumala, Waidyasooriya, Masanori Hariyama
2016 IEEE/ACIS 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS) 108-113 2016
DOI：
10.1109/ICIS.2016.7550742
-
Architecture of an FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL
Peer-reviewed
Hasitha Muthumala, Waidyasooriya, Masanori Hariyama, Kota Kasahara
2016 IEEE/ACIS 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS) 115-119 2016
DOI：
10.1109/ICIS.2016.7550743
-
FPGA Architecture for 3-D FDTD Acceleration Using OpenCL
Peer-reviewed
H. M. Waidyasooriya, M. Hariyama, Y. Ohtera
2016 PROGRESS IN ELECTROMAGNETICS RESEARCH SYMPOSIUM (PIERS) 4719-4719 2016
DOI：
10.1109/PIERS.2016.7735734
-
Multiscale, Multiphysics Computational Chemistry Methods Based on Artificial Intelligence Integrated Ultra-Accelerated Quantum Molecular Dynamics for the Application to Automotive Emission Control
Peer-reviewed
Akira Miyamoto, Kenji Inaba, Yukie Ishizawa, Manami Sato, Rei Komuro, Masashi Sato, Ryo Sato, Patrick Bonnaud, Ryuji Miura, Ai Suzuki, Naoto Miyamoto, Nozomu Hatakeyama, Masanori Hariyama
SAE International Journal of Engines 9 (4) 2434-2441 2016
Publisher:
SAE International
DOI：
10.4271/2016-32-0067
ISSN：
1946-3944 1946-3936
-
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators
Peer-reviewed
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E98A (12) 2658-2669 2015/12
DOI：
10.1587/transfun.E98.A.2658
ISSN：
1745-1337
eISSN：
1745-1337
-
Accurate Liver Extraction Using a Local-Thickness-Based Graph-Cut Approach
Peer-reviewed
Yasuhiro Kobayashi, Masanori Hariyama, Mitsugi Shimoda, Keiichi Kubota
Proc.International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV) 315-318 2015/07/29
-
Automatic Estimation of Optimal Resected Liver Regions Considering Practical Surgical Conditions
Peer-reviewed
Masanori Hariyama, Takeaki Suzuki, Keisuke Maeda, Mitsugi Shimoda, Keiichi Kubota
Proc.International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV) 356-360 2015/07/29
-
Evaluation of an FPGA-Based Shortest-Path-Search Accelerator
Peer-reviewed
Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) 613-617 2015/07/29
-
FPGA-Oriented Design of an FDTD Accelerator Based on Overlapped Tiling
Peer-reviewed
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) 72-77 2015/07/29
-
OpenCL-based Design of an FPGA Accelerator for Phase-Based Correspondence Matching
Peer-reviewed
Shunsuke Tatsumi, Masanori Hariyama, Mamoru Miura, Koichi Ito, Takafumi Aoki
Proc. International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) 613-617 2015/07/28
-
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path
Peer-reviewed
Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 23 (4) 619-630 2015/04
DOI：
10.1109/TVLSI.2014.2314685
ISSN：
1063-8210
eISSN：
1557-9999
-
Hardware-Oriented Succinct-Data-Structure based on Block-Size-Constrained Compression
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama
PROCEEDINGS OF THE 2015 SEVENTH INTERNATIONAL CONFERENCE OF SOFT COMPUTING AND PATTERN RECOGNITION (SOCPAR 2015) 136-140 2015
ISSN：
2381-7542
-
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama
Journal of Computational Engineering 2014 2014/12
DOI：
10.1155/2014/634269
-
An SIMD Architecture for Shortest-Path Search and Its FPGA Implementation
Peer-reviewed
Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) 53-56 2014/07/24
-
Liver Extraction from CT Images Based on Liver Structure Models
Peer-reviewed
Masanori Hariyama, Riichi Tanizawa, Mitsugi Shimoda, Keiichi Kubota, Yasuhiro Kobayashi
International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV) 170-173 2014/07/23
-
Design of an FPGA-Based FDTD Accelerator Using OpenCL
Peer-reviewed
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
International Conference on Parallel and Distributed Processing Techniques and Applications(PDPTA) 371-375 2014/07/23
-
Estimation of Resected Liver Regions Using a Tumor Domination Ratio
Peer-reviewed
Masanori Hariyama, Moe Okada, Mitsugi Shimoda, Keiichi Kubota
International Conference on Image Processing, Computer Vision, and Pattern Recognition(IPCV) 52-56 2014/07/22
-
An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture
Peer-reviewed
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
Proc. the 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) 111-114 2014/06/10
-
FPGA-Accelerator for DNA Sequence Alignment Based on an Efficient Data-Dependent Memory Access Scheme
Peer-reviewed
Hasitha Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Proc. the 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART) 127-130 2014/06/10
-
肝細胞癌手術にオンコロジカルな視点を考慮した自動肝切除領域抽出ソフトの使用経験
下田 貢, 清水 崇行, 白木 孝之, 張山 昌論, 窪田 敬一
日本肝胆膵外科学会・学術集会プログラム・抄録集 26回 660-660 2014/06
Publisher:
(一社)日本肝胆膵外科学会
-
DTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama
Journal of Computational Engineering 2014 2014
DOI：
10.1155/2014/634269
-
Efficient Data Transfer Scheme Using Word-Pair-Encoding-Based Compression for Large-Scale Text-Data Processing
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) 639-642 2014
DOI：
10.1109/APCCAS.2014.7032862
-
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Peer-reviewed
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E96D (8) 1632-1644 2013/08
DOI：
10.1587/transinf.E96.D.1632
ISSN：
0916-8532
-
Heterogeneous Multicore Platform with Accelerator Templates and Its Implementation on an FPGA with Hard-core CPUs
Peer-reviewed
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 47-50 2013/07
-
Reducing Floating-Point Error Based on Residue-Preservation and Its Evaluation on an FPGA
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Hirokazu Takahashi, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 55-58 2013/07
-
An Area-Efficient Asynchronous FPGA Architecture for Handshake-Component-Based Design
Peer-reviewed
Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 15-18 2013/07
-
肝胆膵外科手術への術前シミュレーションサージェリーの応用 門脈自動追跡ソフトの開発とAiRScouter WD-を用いた術中ナビゲーションシステムの構築
清水 崇行, 下田 貢, 張山 昌論, 窪田 敬一
日本肝胆膵外科学会・学術集会プログラム・抄録集 25回 223-223 2013/06
Publisher:
(一社)日本肝胆膵外科学会
-
A Low-Power FPGA Based on Self-Adaptive Multi-Voltage Control
Peer-reviewed
Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
2013 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) 166-169 2013
ISSN：
2163-9612
-
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures
Peer-reviewed
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING 20 (5-6) 595-623 2013
ISSN：
1542-3980
-
Evaluation of an FPGA-Based heterogeneous multicore platform with SIMD/MIMD custom accelerators
Peer-reviewed
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96-A (12) 2576-2586 2013
Publisher:
Institute of Electronics, Information and Communication, Engineers, IEICE
DOI：
10.1587/transfun.E96.A.2576
ISSN：
1745-1337 0916-8508
-
Implementation of a Custom Hardware-Accelerator for Short-read Mapping Using Burrows-Wheeler Alignment
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2013 35TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC) 651-654 2013
DOI：
10.1109/EMBC.2013.6609584
ISSN：
1557-170X
-
Platform and Mapping Methodology for Heterogeneous Multicore Processors
Peer-reviewed
Masanori HARIYAMA, Hasitha Muthumala WAIDYASOORIYA, Yasuhiro TAKEI, Michitaka KAMEYAMA
Interdisciplinary Information Sciences 18 (2) 175-184 2012/12
Publisher:
The Editorial Committee of the Interdisciplinary Information Sciences
DOI：
10.4036/iis.2012.175
ISSN：
1340-9050
-
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation
Peer-reviewed
Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Toru Nojiri, Kunio Uchiyama, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E95C (12) 1872-1882 2012/12
DOI：
10.1587/transele.E95.C.1872
ISSN：
0916-8524
eISSN：
1745-1353
-
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates
Peer-reviewed
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E95C (8) 1434-1443 2012/08
DOI：
10.1587/transele.E95.C.1434
ISSN：
1745-1353
-
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Peer-reviewed
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
The International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 133-136 2012/07
-
Area-Efficient Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs
Peer-reviewed
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
The International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 113-118 2012/07
-
Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2D-FDTD Computation
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
The International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 147-150 2012/07
-
Hybrid Single/Double Precision Floating-Point Computation on GPU Accelerators for 2-D FDTD
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA) 1001-1002 2012/07
-
An Asynchronous FPGA Based on Dual/Single-Rail Hybrid Architecture
Peer-reviewed
Zhengfan XIA, Shota ISHIHARA, Masanori HARIYAMA, Michitaka KAMEYAMA
The International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 139-142 2012/07
-
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, and Michitaka Kameyama
Peer-reviewed
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
IEEE International Symposium on Circuits and Systems(ISCAS) 3017-3020 2012/05/22
-
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E95D (2) 354-363 2012/02
DOI：
10.1587/transinf.E95.D.354
ISSN：
0916-8532
-
高精度血管抽出に基づく門脈支配領域推定
岡田 萌, 張山 昌論, 亀山 充隆, 下田 貢, 小林 康浩
電気関係学会東北支部連合大会講演論文集 2012 68-68 2012
Publisher:
電気関係学会東北支部連合大会実行委員会
DOI：
10.11528/tsjc.2012.0_68
-
FPGA Implementation of Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) 1339-1342 2012
DOI：
10.1109/ISCAS.2012.6271489
ISSN：
0271-4302
-
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture
Peer-reviewed
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E94C (10) 1669-1679 2011/10
DOI：
10.1587/transele.E94.C.1669
ISSN：
0916-8524
eISSN：
1745-1353
-
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 21 (10) 1453-1466 2011/10
DOI：
10.1109/TCSVT.2011.2162277
ISSN：
1051-8215
eISSN：
1558-2205
-
A low-power FPGA based on autonomous fine-grain power gating
Peer-reviewed
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (8) 1394-1406 2011/08
DOI：
10.1109/TVLSI.2010.2050500
ISSN：
1063-8210
-
An FPGA Based on Synchronous/Asynchroous Hybrid Architecture with Area-Efficient FIFO Interfaces
Peer-reviewed
Masanori Hariyama, Yoshiya Komatsu, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 331-334 2011/07/19
-
Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors
Peer-reviewed
Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) 282-288 2011/07/18
-
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E94A (1) 342-351 2011/01
DOI：
10.1587/transfun.E94.A.342
ISSN：
0916-8508
eISSN：
1745-1337
-
An Implementation of an Asychronous FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture
Peer-reviewed
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011 16TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 89-90 2011
DOI：
10.1109/ASPDAC.2011.5722311
-
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals
Peer-reviewed
Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING 17 (5-6) 553-580 2011
ISSN：
1542-3980
eISSN：
1542-3999
-
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E93A (12) 2570-2580 2010/12
DOI：
10.1587/transfun.E93.A.2570
ISSN：
0916-8508
eISSN：
1745-1337
-
Implementation of a Low-Power FPGA Based on Self-Adaptive Voltage Control
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
Student Organizing International Mini-Conference on Information Electronics Systems 57-58 2010/10/19
-
Accelerator-Centric Mapping Methodologies for Heterogeneous Multicore Processors
Invited
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Integrated Circuits and Devices in Vietnam(ICDV) 49-54 2010/08/16
-
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals
Peer-reviewed
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E93D (8) 2134-2144 2010/08
DOI：
10.1587/transinf.E93.D.2134
ISSN：
1745-1361
-
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture
Peer-reviewed
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E93C (8) 1338-1348 2010/08
DOI：
10.1587/transele.E93.C.1338
ISSN：
0916-8524
eISSN：
1745-1353
-
Synchronising logic gates for wave-pipelining design
Peer-reviewed
Z. Xia, S. Ishihara, M. Hariyama, M. Kameyama
ELECTRONICS LETTERS 46 (16) 1116-U36 2010/08
DOI：
10.1049/el.2010.1602
ISSN：
0013-5194
-
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 179-186 2010/07/12
-
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 281-282 2010/07/12
-
A Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture
Peer-reviewed
Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama
Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 271-274 2010/07/12
-
Evaluation of a self-adaptive voltage control scheme for low-power FPGAs
Peer-reviewed
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
Journal of Semiconductor Technology and Science 10 (3) 165-175 2010
Publisher:
Institute of Electronics Engineers of Korea
DOI：
10.5573/JSTS.2010.10.3.165
ISSN：
1598-1657
-
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 291-294 2009/07
-
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic
Peer-reviewed
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 271-274 2009/07
-
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation
Peer-reviewed
Masanori Hariyama, Keita Tanji, Michitaka Kameyama
International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 263-266 2009/07
-
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters
Peer-reviewed
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
International Conference on Engineering of Reconfigurable Systems and Algorithms(ERSA) 145-150 2009/07
-
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
Peer-reviewed
Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA
IEICE Transaction on Electron. E92-C (4) 539-549 2009/04
Publisher:
The Institute of Electronics, Information and Communication Engineers
DOI：
10.1587/transele.E92.C.539
ISSN：
0916-8524
-
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows
Peer-reviewed
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 17 (3) 403-416 2009/03
DOI：
10.1109/TVLSI.2008.2004547
ISSN：
1063-8210
-
A Low-Power FPGA Based on Autonomous Fine-Grain Power-Gating
Peer-reviewed
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 119-120 2009
DOI：
10.1109/ASPDAC.2009.4796461
-
Architecture of a Low-Power FPGA Based on Self-adaptive Voltage Control
Peer-reviewed
Shota Ishihara, Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009) 274-277 2009
DOI：
10.1109/SOCDC.2009.5423801
-
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A (12) 3596-3606 2008/12
DOI：
10.1093/ietfec/e91-a.12.3596
ISSN：
0916-8508
eISSN：
1745-1337
-
Memory Allocation for Multi-Resolution Image Processing
Peer-reviewed
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E91D (10) 2386-2397 2008/10
DOI：
10.1093/ietisy/e91-d.10.2386
ISSN：
1745-1361
-
Evaluation of a field-programmable VLSI based on an asynchronous bit-serial architecture
Peer-reviewed
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E91C (9) 1419-1426 2008/09
DOI：
10.1093/ietele/e91-c.9.1419
ISSN：
0916-8524
eISSN：
1745-1353
-
Non-volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals
Peer-reviewed
Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama
International Conference on Reconfigurable Systems and Algorithms(ERSA) 309-310 2008/07/14
-
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning
Peer-reviewed
Waidyasooriya, Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama
International Conference on Reconfigurable Systems and Algorithms(ERSA) 201-207 2008/07/14
-
Design of a trinocular-stereo-vision VLSI processor based on optimal scheduling
Peer-reviewed
Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E91C (4) 479-486 2008/04
DOI：
10.1093/ietele/e91-c.4.479
ISSN：
0916-8524
eISSN：
1745-1353
-
Multi-context FPGA using fine-grained interconnection blocks and its CAD environment
Peer-reviewed
Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E91C (4) 517-525 2008/04
DOI：
10.1093/ietele/e91-c.4.517
ISSN：
0916-8524
eISSN：
1745-1353
-
Image Processing VLSI Architecture Based on Data Compression
Peer-reviewed
Masanori Hariyama, Hisashi Yoshida, Michitaka Kameyama, Yasubiro Kobayashi
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 430-+ 2008
ISSN：
1548-3746
-
FPGA implementation of a vehicle detection algorithm using three-dimensional information
Peer-reviewed
Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama
2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8 3475-3479 2008
-
A Low-Power Field-Programmable VLSI Based on a Fine-Grained Power-Gating Scheme
Peer-reviewed
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 702-705 2008
ISSN：
1548-3746
-
FPGA implementation of a vehicle detection algorithm using three-dimensional information
Peer-reviewed
Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama
IPDPS Miami 2008 - Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium, Program and CD-ROM 2008
DOI：
10.1109/IPDPS.2008.4536535
-
Optimal Scheduling and Memory Allocation for Window-Type Image Processing
Peer-reviewed
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
IEICE Transaction J90-D (5) 1178-1193 2007/05
Publisher:
The Institute of Electronics, Information and Communication Engineers
ISSN：
1880-4535
-
Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture
Peer-reviewed
Waidyasoorlya Hasitha Muthumala, Masanorl Hariyama, Michitaka Kameyama
2007 IEEE DALLAS/CAS WORKSHOP ON SYSTEM-ON-CHIP (SOC): DESIGN, APPLICATIONS, INTEGRATION, AND SOFTWARE 59 (62) 59-62 2007
DOI：
10.1109/DCAS.2007.4433216
-
A field-programmable VLSI based on an asynchronous bit-serial architecture
Peer-reviewed
Masanori Hariyama, Shota Ishihara, Chang Chia Wei, Michitaka Karneyarna.
2007 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS 380-383 2007
DOI：
10.1109/ASSCC.2007.4425710
-
Minimizing energy consumption based on dual-supply-voltage assignment and interconnection simplification
Peer-reviewed
Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E89C (11) 1551-1558 2006/11
DOI：
10.1093/ietele/e89-c.11.1551
ISSN：
0916-8524
eISSN：
1745-1353
-
A multi-context FPGA using floating-gate-MOS functional pass-gates
Peer-reviewed
Masanori Hariyama, Sho Ogata, Michitaka Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E89C (11) 1655-1661 2006/11
DOI：
10.1093/ietele/e89-c.11.1655
ISSN：
0916-8524
eISSN：
1745-1353
-
Fine-Grained Architectures for Field-Programmable VLSIs
Invited
Masanori Hariyama, Michitaka Kameyama
International Workshop on Post-Binary ULSI Systems 1-5 2006/05/17
-
Optimal periodical memory allocation for logic-in-memory image processors
Peer-reviewed
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 193-+ 2006
DOI：
10.1109/ISVLSI.2006.69
-
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals
Peer-reviewed
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
ISMVL 2006: 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC 106-111 2006
DOI：
10.1109/IPDPS.2006.1639467
ISSN：
0195-623X
-
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals
Peer-reviewed
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
ISMVL 2006: 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC 106-111 2006
DOI：
10.1109/ISMVL.2006.40
ISSN：
0195-623X
-
Processor architecture for road extraction based on projective transformation
Peer-reviewed
Sunggae Lee, Masanori Hariyama, Michitaka Kameyama
2006 SICE-ICASE INTERNATIONAL JOINT CONFERENCE, VOLS 1-13 5808-+ 2006
-
Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment
Peer-reviewed
Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Michitaka Kameyama
2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 155-158 2006
DOI：
10.1109/ASSCC.2006.357874
-
1000 Frame/sec stereo matching VLSI processor with adaptive window-size control
Peer-reviewed
Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 123-126 2006
DOI：
10.1109/ASSCC.2006.357867
-
A multi-context FPGA using a Floating-Gate-MOS functional pass-gate and its CAD environment
Peer-reviewed
Masanori Hariyama, Michitaka Kameyama
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 1803-+ 2006
DOI：
10.1109/APCCAS.2006.342169
-
GA-based assignment of supply and threshold voltages and interconnection simplification for low power VLSI design
Peer-reviewed
Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama
2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS 1264-+ 2006
DOI：
10.1109/APCCAS.2006.342393
-
FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture
Peer-reviewed
M Hariyama, Y Kobayashi, H Sasaki, M Kameyama
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A (12) 3516-3522 2005/12
DOI：
10.1093/ietfec/e88-a.12.3516
ISSN：
0916-8508
eISSN：
1745-1337
-
Low-power field-programmable VLSI using multiple supply voltages
Peer-reviewed
W Chong, M Hariyama, M Kameyama
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E88A (12) 3298-3305 2005/12
DOI：
10.1093/ietfec/e88-a.12.3298
ISSN：
1745-1337
-
Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access
Peer-reviewed
M Hariyama, H Sasaki, M Kameyama
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E88D (7) 1486-1491 2005/07
DOI：
10.1093/ietisy/e88-d.7.1486
ISSN：
0916-8532
-
Genetic approach to minimizing energy consumption of VLSI processors using multiple supply voltages
Peer-reviewed
M Hariyama, T Aoyama, M Kameyama
IEEE TRANSACTIONS ON COMPUTERS 54 (6) 642-650 2005/06
DOI：
10.1109/TC.2005.100
ISSN：
0018-9340
-
FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture
Peer-reviewed
Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama, Yasuhiro Kobayashi
Midwest Symposium on Circuits and Systems 2005 1219-1222 2005
DOI：
10.1109/MWSCAS.2005.1594327
ISSN：
1548-3746
-
Minimizing energy consumption of VLSI processors based on dual-supply-voltage assignment and interconnection simplification
Peer-reviewed
Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
Midwest Symposium on Circuits and Systems 2005 1867-1870 2005
DOI：
10.1109/MWSCAS.2005.1594488
ISSN：
1548-3746
-
DSP-specific field-programmable VLSI and its CAD environment
Peer-reviewed
Masanori Hariyama, Sho Ogata, Michitaka Kameyama
Midwest Symposium on Circuits and Systems 2005 651-654 2005
DOI：
10.1109/MWSCAS.2005.1594185
ISSN：
1548-3746
-
Novel switch block architecture using non-volatile functional pass-gate for multi-context FPGAs
Peer-reviewed
M Hariyama, W Chong, S Ogata, M Kameyama
IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 46-50 2005
ISSN：
2159-3477
-
Design of a multi-context FPGA using a floating-gate-MOS functional pass-gate
Peer-reviewed
Masanori Hariyama, Sho Ogata, Michitaka Kameyama, Yasutoshi Morita
2005 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE, PROCEEDINGS OF TECHNICAL PAPERS 421-424 2005
DOI：
10.1109/ASSCC.2005.251755
-
Field-programmable VLSI based on a bit-serial fine-grain architecture
Peer-reviewed
M Hariyama, WS Chong, M Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E87C (11) 1897-1902 2004/11
ISSN：
1745-1353
-
Design of a Stereo Vision VLSI Processor Based on an Optimal Scheduling
Peer-reviewed
Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama
IEICE transaction on fundamentals of electronics, communications and computer sciences Vol.J87-A (5) 672-680 2004/05
Publisher:
The Institute of Electronics, Information and Communication Engineers
ISSN：
0913-5707
-
Recursive computation-based stereo matching and its implementation in VLSI
Peer-reviewed
K Miura, M Hariyama, M Kameyama
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 87 (12) 19-27 2004
ISSN：
8756-663X
-
Road extraction VLSI processor based on optimal allocation and its application to highly safe intelligent vehicles
Peer-reviewed
M Hariyama, T Kudoh, M Kameyama
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 87 (6) 49-57 2004
DOI：
10.1002/ecjb.20094
ISSN：
8756-663X
-
A field-programmable VLSI processor based on direct allocation of a control/data flow graph
Peer-reviewed
N Ohsawa, M Hariyama, M Kameyama
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 87 (7) 28-37 2004
DOI：
10.1002/ecjb.10076
ISSN：
8756-663X
-
Low-power field-programmable VLSI processor using dynamic circuits
Peer-reviewed
WS Chong, M Hariyama, M Kameyama
VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 243-248 2004
ISSN：
2159-3477
-
Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure
Peer-reviewed
N Ohsawa, O Sakamoto, M Hariyama, M Kameyama
VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS 258-259 2004
DOI：
10.1109/ISVLSI.2004.1339547
ISSN：
2159-3477
-
VLSI processor for reliable stereo matching based on window-parallel logic-in-memory architecture
Peer-reviewed
M Hariyama, M Kameyama
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS 166-169 2004
-
Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access
Peer-reviewed
M Hariyama, H Sasaki, M Kameyama
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS 245-247 2004
-
Design of a VLSI Processor Based on Hierarchically Parallel Memory Access\\\\ for Moving-Object-Trajectory Prediction
Peer-reviewed
Masanori Hariyama, Hideki Kazama, Michitaka Kameyama
IEICE Trans. J86C (8) 760-770 2003/08
Publisher:
The Institute of Electronics, Information and Communication Engineers
ISSN：
1345-2827
-
Recursive-Computation-Based Stereo Matching and Its VLSI Implementation
Peer-reviewed
Kiyoshi Miura, Masanori Hariyama, Michitaka Kameyama
IEICE Trans. J86-C (8) 752-759 2003/08
Publisher:
The Institute of Electronics, Information and Communication Engineers
ISSN：
1345-2827
-
High-Level Synthesis of a Logic-in-Memory VLSI Processor Based on a Genetic Algorithm
Peer-reviewed
Takao Kudoh, Masanori Hariyama, Michitaka Kameyama
Journal of Information Processing Society of Japan 44 (5) 1206-1215 2003/05
-
Periodical Memory Allocation Method for Window Operation and ItsApplication to a VLSI Image Processor
Peer-reviewed
Masanori Hariyama, Takao Kudoh, Michitaka Kameyama
IEICE Trans. J86-C (5) 524-533 2003/05
Publisher:
The Institute of Electronics, Information and Communication Engineers
ISSN：
1345-2827
-
Highly Reliable Stereo Matching Based on Adaptive Window-Size Selection and Its VLSI Implementation
Peer-reviewed
Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama
Trans. SICE 39 (3) 225-233 2003/03
Publisher:
DOI：
10.9746/sicetr1965.39.225
ISSN：
0453-4654
-
Chip design of a field programmable VLSI processor using memory-based cells
Peer-reviewed
N Ohsawa, O Sakamoto, M Hariyama, A Kameyama
SICE 2003 ANNUAL CONFERENCE, VOLS 1-3 1973-1977 2003
-
Stereo vision VLSI processor based on a recursive computation algorithm
Peer-reviewed
K Miura, M Hariyama, M Kameyama
SICE 2003 ANNUAL CONFERENCE, VOLS 1-3 1564-1567 2003
-
Field ProgrammableVLSI Processor Based on Direct Allocation of a Control/Data Flow Graph
Peer-reviewed
Naotaka OHSAWA, Masanori HARIYAMA, Michitaka KAMEYAMA
IEICE Trans. Electron J85-C (5) 384-392 2002/05
Publisher:
The Institute of Electronics, Information and Communication Engineers
ISSN：
1345-2827
-
Architecture of a field-programmable VLSI processor using memory-based cells
Peer-reviewed
N Ohsawa, M Hariyama, M Kameyama
SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5 1849-1852 2002
-
Optical flow extraction based on reuse of intermediate results and VLSI implementation
Peer-reviewed
M Hariyama, M Kameyama
SICE 2002: PROCEEDINGS OF THE 41ST SICE ANNUAL CONFERENCE, VOLS 1-5 1845-1848 2002
-
High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph
Peer-reviewed
N Ohsawa, M Hariyama, M Kameyama
ISVLSI 2000: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI - NEW PARADIGMS FOR VLSI SYSTEMS DESIGN 95-100 2002
DOI：
10.1109/ISVLSI.2002.1016881
ISSN：
2159-3477
-
Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size
Peer-reviewed
Masanori HARIYAMA, Michitaka KAMEYAMA
Interdisciplinary Information Sciences 7 (2) 289-297 2001/09
Publisher:
Tohoku University
DOI：
10.4036/iis.2001.289
ISSN：
1340-9050
-
Design Methodology for Human-Oriented Intelligent Integrated Systems
Peer-reviewed
Michitaka KAMEYAMA, Masanori HARIYAMA
Interdisciplinary Information Sciences 7 (2) 279-287 2001/09
Publisher:
Tohoku University
DOI：
10.4036/iis.2001.279
ISSN：
1340-9050
-
Design of a Collision Detection VLSI Processor for Highly Safe Intelligent Vehicles Based on a Hierarchical Obstacle Representation
Peer-reviewed
Masanori Hariyama, Michitaka Kameyama
Trans. IEE of Japan 121-C (6) 1016-1025 2001/06
Publisher:
ISSN：
0385-4221
-
Road Extraction VLSI Processor Based on an Optimal Allocation and Its Application to Highly Safe Intelligent Vehicles
Peer-reviewed
Masanori Hariyama, Takao Kudoh, Michitaka Kameyama
IEICE Trans. Information and Systems J84-D-I (6) 531-539 2001/06
Publisher:
The Institute of Electronics, Information and Communication Engineers
ISSN：
0915-1915
-
Highly-parallel stereo vision VLSI processor based on arm optimal parallel memory access scheme
Peer-reviewed
M Hariyama, S Lee, M Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E84C (3) 382-389 2001/03
ISSN：
1745-1353
-
Implementation of an Ultra-High-Speed Path Planning VLSI Processor
Peer-reviewed
Masanori Hariyama, Fumitake Yamaguchi, Michitaka Kameyama
Trans. SICE 37 (3) 235-241 2001/03
Publisher:
DOI：
10.9746/sicetr1965.37.235
ISSN：
0453-4654
-
Highly-parallel stereo vision VLSI processor based on an optimal parallel memory access scheme
M. Hariyama, S. Lee, M. Kameyama
IEICE Transactions on Electronics E84-C (3) 382-389 2001
Publisher:
Institute of Electronics, Information and Communication, Engineers, IEICE
ISSN：
0916-8524
-
Prospects of Intelligent Integrated Systems for Real-World Applications
Peer-reviewed
Michitaka Kameyama, Masanori Hariyama
The Society of Instrument and Control Engineers 40 (12) 841-847 2001
Publisher:
DOI：
10.11499/sicejl1962.40.841
ISSN：
0453-4662
-
VLSI processor for reliable stereo matching based on adaptive window-size selection
Peer-reviewed
M Hariyama, T Takeuchi, M Kameyama
2001 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND AUTOMATION, VOLS I-IV, PROCEEDINGS 1168-1173 2001
DOI：
10.1109/ROBOT.2001.932769
ISSN：
1050-4729
-
An FPGA-oriented motion-stereo processor with a simple interconnection network for parallel memory access
Peer-reviewed
S Lee, M Hariyama, M Kameyama
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E83D (12) 2122-2130 2000/12
ISSN：
1745-1361
-
VLSI Processor for Hierarchical Template Matching and Its Application to a Ball-Catching Robot System
Peer-reviewed
Masanori Hariyama, Hideki Kazama, Michitaka Kameyama
Proc. IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2 613-618 2000/11
-
VLSI-Oriented Algorithm for Reliable Stereo Matching
Peer-reviewed
Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama
Proc. IEEE International Symposium on Intelligent Signal Processing and Communication Systems 2 625-630 2000/11
-
Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture
Peer-reviewed
Masanori Hariyama, Michitaka Kameyama
Journal of Robotics and Mechatronics 12 (5) 521-526 2000/10
-
Path Planning Based on Distance Transformation and Its VLSI Implementation
Peer-reviewed
Masanori Hariyama, Michitaka Kameyama
Journal of Robotics and Mechatronics 12 (5) 527-533 2000/10
-
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction
Peer-reviewed
Hideki Kazama, Masanori Hariyama, Michitaka Kameyama
Journal of Robotics and Mechatronics 12 (5) 534-540 2000/10
-
Design of a Motion Stereo VLSI Processor Based on a Transfer Bottleneck-Free Sensor/Memory Architecture
Peer-reviewed
Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama
Trans. IEEE of Japan 120-E (5) 237-244 2000/05
Publisher:
The Institute of Electrical Engineers of Japan
DOI：
10.1541/ieejsmas.120.237
ISSN：
1341-8939
-
Architecture of a high-performance stereo vision VLSI processor
Peer-reviewed
M Hariyama, S Lee, M Kameyama
ADVANCED ROBOTICS 14 (5) 329-332 2000
ISSN：
0169-1864
-
Reliable stereo matching for highly-safe intelligent vehicles and its VLSI implementation
Peer-reviewed
M Hariyama, T Takeuchi, M Kameyama
PROCEEDINGS OF THE IEEE INTELLIGENT VEHICLES SYMPOSIUM 2000 128-133 2000
-
Collision detection VLSI processor for intelligent vehicles using a hierarchically-content-addressable memory
Peer-reviewed
M Hariyama, K Sasaki, M Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E82C (9) 1722-1729 1999/09
ISSN：
1745-1353
-
Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory
Peer-reviewed
Masanori Hariyama, Michitaka Kameyama
Interdisciplinary Information Sciences 5 (2) 109-115 1999
Publisher:
Tohoku University
DOI：
10.4036/iis.1999.109
ISSN：
1340-9050
-
Innovation of Intelligent Integrated System Architecture
Peer-reviewed
Michitaka Kameyama, Takahiro Hanyu, Masanori Hariyama
International Symposium on Future of Intellcetual Integrated Electronics 231-247 1999
-
Optimal Design of a Parallel VLSI Processor Based on Minimization of Area-Time Products and Its Application
Peer-reviewed
Masanori Hariyama, Michitaka Kameyama
Proc. the Workshop on Synthesis and System Integration of Mixed Technologyies 179-185 1998
-
Design of a collision detection VLSI processor based on minimization of area-time products
Peer-reviewed
M Hariyama, M Kameyama
1998 IEEE INTERNATIONAL CONFERENCE ON ROBOTICS AND AUTOMATION, VOLS 1-4 3691-3696 1998
ISSN：
1050-4729
-
A three-dimensional instrumentation VLSI processor based on a concurrent memory-access scheme
Peer-reviewed
S Lee, M Hariyama, M Kameyama
IEICE TRANSACTIONS ON ELECTRONICS E80C (11) 1491-1498 1997/11
ISSN：
0916-8524
eISSN：
1745-1353
-
Collision detection VLSI processor for intelligent vehicles based on ROM-type content-addressable memory
Peer-reviewed
M Hariyama, M Kameyama
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 80 (5) 62-69 1997/05
ISSN：
8756-663X
-
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects
Peer-reviewed
Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
Systems and Computers in Japan 28 (2) 54-61 1997
Publisher:
John Wiley and Sons Inc.
DOI：
10.1002/(SICI)1520-684X(199702)28:2<54::AID-SCJ6>3.0.CO;2-Q
ISSN：
0882-1666
-
Collision detection VLSI processor for intelligent vehicles based on a hierarchical obstacle representation
Peer-reviewed
M Hariyama, M Kameyama
IEEE CONFERENCE ON INTELLIGENT TRANSPORTATION SYSTEMS 830-834 1997
-
Design of a VLSI processor chip for three-dimensional instrumentation
Peer-reviewed
SW Lee, M Hariyama, M Kameyama
SICE '97 - PROCEEDINGS OF THE 36TH SICE ANNUAL CONFERENCE, INTERNATIONAL SESSION PAPERS 951-954 1997
-
読出し専用型連想メモリに基づく高安全自動車用衝突チェックVLSIプロセッサ
Peer-reviewed
張山 昌論, 亀山 充隆
電子情報通信学会論文誌 J79-C-II (11) 698-705 1996/11
-
３次元物体直方体表現用ロボットビジョンVLSIプロセッサ
Peer-reviewed
張山 昌論, 荒海 雄一, 亀山 充隆
電子情報通信学会論文誌 J79-D (5) 245-252 1996/05
-
Collision detection VLSI processor for intelligent vehicles based on efficient coordinate transformation scheme
Peer-reviewed
M Hariyama, M Kameyama
PROCEEDINGS OF THE 1996 IEEE IECON - 22ND INTERNATIONAL CONFERENCE ON INDUSTRIAL ELECTRONICS, CONTROL, AND INSTRUMENTATION, VOLS 1-3 755-760 1996
ISSN：
1553-572X
-
High-performance VLSI architecture for three-dimensional instrumentation based on a new concurrent memory-access scheme
Peer-reviewed
S Lee, M Hariyama, M Kameyama
APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96 500-503 1996
-
A Collision Detection Multiprocessor for Intelligent Vehicles Using a High-Density CAM
Peer-reviewed
M. Hariyama, T. Hanyu, M. Kameyama
IEEE Intelligent Vehicles Symposium 143-148 1994/10
-
DESIGN OF A CAM-BASED COLLISION DETECTION VLSI PROCESSOR FOR ROBOTICS
Peer-reviewed
M HARIYAMA, M KAMEYAMA
IEICE TRANSACTIONS ON ELECTRONICS E77C (7) 1108-1115 1994/07
ISSN：
0916-8524
eISSN：
1745-1353
-
Rule-Based Highly-Safe Intelligent Vehicle Using a New Content-Addressable Memory
Peer-reviewed
M. Hariyama, T. Hanyu, M. Kameyama
IEEE Proc. of the Intelligent Vehicles Symposium 143-148 1994
-
A COLLISION DETECTION PROCESSOR FOR INTELLIGENT VEHICLES
Peer-reviewed
M HARIYAMA, M KAMEYAMA
IEICE TRANSACTIONS ON ELECTRONICS E76C (12) 1804-1811 1993/12
ISSN：
0916-8524
eISSN：
1745-1353
-
A PARALLEL COLLISION DETECTION VLSI PROCESSOR FOR ROBOTICS USING A CONTENT-ADDRESSABLE MEMORY
Peer-reviewed
M HARIYAMA, M KAMEYAMA
PROCEEDINGS OF THE IECON 93 - INTERNATIONAL CONFERENCE ON INDUSTRIAL ELECTRONICS, CONTROL, AND INSTRUMENTATION, VOLS 1-3 1512-1516 1993
