Details of the Researcher

PHOTO

Masayuki Sato
Section
Graduate School of Information Sciences
Job title
Associate Professor
Degree

  • 博士（情報科学）（東北大学）

  • 修士（情報科学）（東北大学）

Committee Memberships 9

  • 電子情報通信学会 エレクトロニクスソサイエティ英文論文誌編集委員会　編集委員

    2024/06 - Present

  • 情報処理学会東北支部　会計幹事

    2021 - Present

  • CANDAR WANC Workshop Committee

    2019 - Present

  • CANDAR　Main Symposium Committee Member (Track 2)

    2017 - Present

  • 電子情報通信学会　情報・システムソサイエティ英文論文誌編集委員会

    2020/06 - 2024/05

  • 電子情報通信学会集積回路研究専門委員会　専門委員

    2017/06 - 2023/05

  • PDCAT　Program Committee

    2022 - 2023

  • 電子情報通信学会　論文特集号 編集委員

    2021 - 2021

  • 電子情報通信学会　論文特集号 編集委員

    2019 - 2019

Show all ︎Show first 5

Professional Memberships 4

  • ACM

  • 電子情報通信学会

  • 情報処理学会

  • IEEE

Research Interests 1

  • Computer Architecture

Research Areas 2

  • Informatics / Information networks /

  • Informatics / Computer systems /

Awards 9

  1. Outstanding Paper Award

    2024/11　CANDAR 2024　Adaptive Parallelization based on Frame-level and Tile-level Parallelisms for VVC Encoding

  2. Best Paper Award

    2022/12　PDCAT 2022　A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders

  3. Best Poster Award

    2022/04　COOL Chips 25　A Shared Cache Architecture for VVC Coding

  4. 研究奨励賞

    2021/12　石田實記念財団

  5. Best Paper Award

    2020/11　CANDAR　Combinatorial Clustering based on an Externally-defined One-hot Constraint

  6. 野口研究奨励賞

    2020/06　情報処理学会東北支部

  7. Best Poster Winner HPC-in-Asia

    2019/06　ISC High Performance　A Skewed Multi-bank Cache for Vector Processors

  8. Student Session Award (Encouragement Prize)

    2017/08　IEEE　Early Evaluation of a Heterogeneous Memory Architecture on a Vector Supercomputer

  9. Best Poster Award

    2012/04　COOLChips XV　A Bypass Mechanism for Way-Adaptable Caches

Show all ︎Show 5

Papers 91

  1. A Graph-based Molecular Structure Identification Method via Feature Extraction for Three-dimensional Electron Diffraction Data Peer-reviewed

    Yusuke Fukasawa, Kazuhiko Komatsu, Masayuki Sato, Saori Maki-Yonekura, Hirofumi Kurokawa, Koji Yonekura, Hiroaki Kobayashi

    2024 Twelfth International Symposium on Computing and Networking Workshops (CANDARW)　325-329　2024/11/26

    Publisher: IEEE

    DOI： 10.1109/candarw64572.2024.00060 　

  2. Adaptive Parallelization based on Frame-level and Tile-level Parallelisms for VVC Encoding Peer-reviewed

    Karin Onouchi, Masayuki Sato, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi

    2024 Twelfth International Symposium on Computing and Networking (CANDAR)　87-95　2024/11/26

    Publisher: IEEE

    DOI： 10.1109/candar64496.2024.00018 　

  3. 画像特徴量を用いたブロック分割によるVVCイントラエンコーダの高速化

    内山力太, 小野内花倫, 丹羽直也, 佐藤雅之, 岩崎裕江, 小林広明

    列/分散/協調処理に関するサマー・ワークショップ(SWoPP2024)　2024/08

  4. Prediction of Steam Turbine Blade Erosion Using CFD Simulation Data and Hierarchical Machine Learning Peer-reviewed

    Issei Fukamizu, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    Journal of Engineering for Gas Turbines and Power　1-10　2024/06/25

    Publisher: ASME International

    DOI： 10.1115/1.4065815 　

    ISSN： 0742-4795

    eISSN： 1528-8919

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    Abstract The information of the degree of blade erosion is vital for the efficient operation of steam turbines. However, it is nearly impossible to directly measure the degree of blade erosion during operation. Moreover, collecting sufficient data of eroded cases for predictive analysis is challenging. Therefore, this paper proposes a blade erosion prediction method using numerical simulation and machine learning. Pressure data of several blade erosion cases are collected from the numerical turbine simulation. The machine learning approach involves training on collected simulation data to predict the degree of erosion for the firststage stator (1S) and the first-stage rotor blade (1R) from internal pressure data. The proposed erosion prediction model employs a two-step hierarchical approach. First, the proposed model predicts the 1S erosion degree using the k-NN (k-Nearest Neighbor) regression. Second, the proposed model estimates the 1R erosion degree with Linear Regression models. These models are tailored for each of the 1S erosion degrees, utilizing pressure data processed through Fast Fourier Transform (FFT). The evaluation shows that the proposed method achieves the prediction of the 1S erosion with a Mean Absolute Error (MAE) of 0.000693 mm, and the 1R erosion with an MAE of 0.458 mm. The evaluation results indicate that the proposed method can accurately capture the degree of turbine blade erosion from internal pressure data. As a result, the proposed method suggests that the erosion prediction method can be effectively used to determine the optimal timing for Maintenance and Repair Operations (MRO).

  5. イジングマシンを用いた救助経路の最適化に関する一検討

    長南 和希, 小松 一彦, 佐藤 雅之, 小林 広明

    情報処理学会 第86回全国大会　2024/03

  6. 機械学習モデルを用いた断層パラメータ予測に関する一検討

    JEONG SANGUK, 小松 一彦, 佐藤 雅之, 小林 広明

    情報処理学会 第86回全国大会　2024/03

  7. VVCの高速化のためのフレーム差分画像を用いたブロック分割に関する一検討

    原田 零生, 近藤 嘉昭, 佐藤 雅之, 岩崎 裕江, 小松 一彦, 小林 広明

    情報処理学会 第86回全国大会　2024/03

  8. 巡回セールスマン問題による並列ベクトルアニーリングの評価

    小野田 誠, 小松 一彦, 伴内 光太郎, 百瀬 真太郎, 佐藤 雅之, 小林 広明

    第193回ハイパフォーマンスコンピューティング研究発表会　2024/03

  9. A Constraint Partition Method for Combinatorial Optimization Problems Peer-reviewed

    Onoda Makoto, Kazuhiko Komatsu, Masahito Kumagai, Masayuki Sato, Hiroaki Kobayashi

    In Proceedings of 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)　600　(607)　2023/12

    DOI： 10.1109/MCSoC60832.2023.00093 　

  10. Appropriate Graph-Algorithm Selection for Edge Devices Using Machine Learning Peer-reviewed

    Yusuke Fukasawa, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    In Proceedings of 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)　544　(551)　2023/12

    DOI： 10.1109/MCSoC60832.2023.00086 　

  11. Multi-scale Loss based Electron Microscopic Image Pair Matching Method Peer-reviewed

    Chunting Duan, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    In Proceedings of 22nd IEEE International Conference on Machine Learning and Applications　1957-1964　2023/12

    DOI： 10.1109/ICMLA58977.2023.00295 　

  12. Performance Evaluation of Tsunami Evacuation Route Planning on Multiple Annealing Machines

    Yihui Liu, Kazuhiko Komatsu, Masahito Kumagai, Masayuki Sato, Hiroaki Kobayashi

    Proceedings of the 20th ACM International Conference on Computing Frontiers　2023/05/09

    Publisher: ACM

    DOI： 10.1145/3587135.3592193 　

  13. Ising-Based Kernel Clustering Peer-reviewed

    Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    Algorithms　16　(4)　214-214　2023/04/19

    Publisher: MDPI AG

    DOI： 10.3390/a16040214 　

    eISSN： 1999-4893

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    Combinatorial clustering based on the Ising model is drawing attention as a high-quality clustering method. However, conventional Ising-based clustering methods using the Euclidean distance cannot handle irregular data. To overcome this problem, this paper proposes an Ising-based kernel clustering method. The kernel clustering method is designed based on two critical ideas. One is to perform clustering of irregular data by mapping the data onto a high-dimensional feature space by using a kernel trick. The other is the utilization of matrix–matrix calculations in the numerical libraries to accelerate preprocess for annealing. While the conventional Ising-based clustering is not designed to accept the transformed data by the kernel trick, this paper extends the availability of Ising-based clustering to process a distance matrix defined in high-dimensional data space. The proposed method can handle the Gram matrix determined by the kernel method as a high-dimensional distance matrix to handle irregular data. By comparing the proposed Ising-based kernel clustering method with the conventional Euclidean distance-based combinatorial clustering, it is clarified that the quality of the clustering results of the proposed method for irregular data is significantly better than that of the conventional method. Furthermore, the preprocess for annealing by the proposed method using numerical libraries is by a factor of up to 12.4 million × from the conventional naive python’s implementation. Comparisons between Ising-based kernel clustering and kernel K-means reveal that the proposed method has the potential to obtain higher-quality clustering results than the kernel K-means as a representative of the state-of-the-art kernel clustering methods.

  14. A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders Peer-reviewed

    Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi

    Parallel and Distributed Computing, Applications and Technologies　288-300　2023/04/08

    Publisher: Springer Nature Switzerland

    DOI： 10.1007/978-3-031-29927-8_23 　

    ISSN： 0302-9743

    eISSN： 1611-3349

  15. Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation Peer-reviewed

    Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

    Proceedings of 2022 IEEE/ACM 12th Workshop on Irregular Applications: Architectures and Algorithms (IA3)　1-8　2022/11

    DOI： 10.1109/IA356718.2022.00007 　

  16. A hierarchical wavefront method for LU-SGS Peer-reviewed

    Kazuhiko Komatsu, Yuta Hougi, Masayuki Sato, Hiroaki Kobayashi

    Computers & Fluids　245　105572-105572　2022/06

    Publisher: Elsevier BV

    DOI： 10.1016/j.compfluid.2022.105572 　

    ISSN： 0045-7930

  17. An Efficient Reference Image Sharing Method for the Image-division Parallel Video Encoding Architecture Peer-reviewed

    Nakamura Ken, Omori Yuya, Kobayashi Daisuke, Nitta Koyo, Sano Kimikazu, Sato Masayuki, Iwasaki Hiroe, Kobayashi Hiroaki

    IEICE Transactions on Electronics　advpub　2022

    Publisher: The Institute of Electronics, Information and Communication Engineers

    DOI： 10.1587/transele.2022lhp0002 　

    ISSN： 0916-8524

    eISSN： 1745-1353

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    This paper proposes an efficient reference image sharing method for the image-division parallel video encoding architecture. This method efficiently reduces the amount of data transfer by using pre-transfer with area prediction and on-demand transfer with a transfer management table. Experimental results show that the data transfer can be reduced to 19.8-35.3% of the conventional method on average without major degradation of coding performance. This makes it possible to reduce the required bandwidth of the inter-chip transfer interface by saving the amount of data transfer.

  18. A Metadata Prefetching Mechanism for Hybrid Memory Architectures Peer-reviewed

    Shunsuke TSUKADA, Hikaru TAKAYASHIKI, Masayuki SATO, Kazuhiko KOMATSU, Hiroaki KOBAYASHI

    IEICE Transactions on Electronics　E105.C　(6)　232-243　2022

    Publisher: Institute of Electronics, Information and Communications Engineers (IEICE)

    DOI： 10.1587/transele.2021lhp0004 　

    ISSN： 0916-8524

    eISSN： 1745-1353

  19. Detection of Machinery Failure Signs From Big Time-Series Data Obtained by Flow Simulation of Intermediate-Pressure Steam Turbines Peer-reviewed

    Kazuhiko Komatsu, Hironori Miyazawa, Cheng Yiran, Masayuki Sato, Takashi Furusawa, Satoru Yamamoto, Hiroaki Kobayashi

    Journal of Engineering for Gas Turbines and Power　144　(1)　2022/01/01

    Publisher: ASME International

    DOI： 10.1115/1.4052142 　

    ISSN： 0742-4795

    eISSN： 1528-8919

  20. A dynamic parameter tuning method for SpMM parallel execution Peer-reviewed

    Bin Qi, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    Concurrency and Computation: Practice and Experience　2021/12/09

    Publisher: Wiley

    DOI： 10.1002/cpe.6755 　

    ISSN： 1532-0626

    eISSN： 1532-0634

  21. Ising-Based Combinatorial Clustering Using the Kernel Method Peer-reviewed

    Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)　2021/12

    Publisher: IEEE

    DOI： 10.1109/mcsoc51149.2021.00037 　

  22. Optimizations of a Linear Matrix Solver in a Composite Simulation for a Vector Computer Peer-reviewed

    He Zhilin, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    Proceedings of the 12th International Symposium on Parallel Architectures, Algorithms and Programming (PAAP)　2021/12

  23. An Externally-Constrained Ising Clustering Method for Material Informatics Peer-reviewed

    Kazuhiko Komatsu, Masahito Kumagai, Ji Qi, Masayuki Sato, Hiroaki Kobayashi

    2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)　2021/11

    Publisher: IEEE

    DOI： 10.1109/candarw53999.2021.00040 　

  24. Register Flush-free Runahead Execution for Modern Vector Processors Peer-reviewed

    Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

    2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)　2021/10

    Publisher: IEEE

    DOI： 10.1109/sbac-pad53543.2021.00023 　

  25. Performance and Power Analysis of a Vector Computing System Peer-reviewed

    Komatsu, Kazuhiko, Akito Onodera, Erich Focht, Soya Fujimoto, Yoko Isobe, Shintaro Momose, Masayuki Sato, Hiroaki Kobayashi

    Supercomputing Frontiers and Innovations　8　(2)　2021/06

    Publisher: FSAEIHE South Ural State University (National Research University)

    DOI： 10.14529/jsfi210205 　

    ISSN： 2313-8734

  26. Optimizing Load Balance in a Parallel CFD Code for a Large-scale Turbine Simulation on a Vector Supercomputer Peer-reviewed

    Osamu Watanabe, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    Supercomputing Frontiers and Innovations　8　(2)　2021/06

    Publisher: FSAEIHE South Ural State University (National Research University)

    DOI： 10.14529/jsfi210207 　

    ISSN： 2313-8734

  27. A Processor Selection Method based on Execution Time Estimation for Machine Learning Programs Peer-reviewed

    Kou Murakami, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)　2021/06

    Publisher: IEEE

    DOI： 10.1109/ipdpsw52791.2021.00116 　

  28. A Metadata Prefetching Mechanism for Hybrid Memory Architectures Peer-reviewed

    Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

    2021 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)　2021/04/14

    Publisher: IEEE

    DOI： 10.1109/coolchips52128.2021.9410321 　

  29. Efficient Mixed-Precision Tall-and-Skinny Matrix-Matrix Multiplication for GPUs Peer-reviewed

    Hao Tang, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    International Journal of Networking and Computing　11　(2)　267-282　2021

    Publisher: IJNC Editorial Committee

    DOI： 10.15803/ijnc.11.2_267 　

    ISSN： 2185-2839

    eISSN： 2185-2847

  30. An External Definition of the One-Hot Constraint and Fast QUBO Generation for High-Performance Combinatorial Clustering Peer-reviewed

    Masahito Kumagai, Kazuhiko Komatsu, Fumiyo Takano, Takuya Araki, Masayuki Sato, Hiroaki Kobayashi

    International Journal of Networking and Computing　11　(2)　463-491　2021

    Publisher: IJNC Editorial Committee

    DOI： 10.15803/ijnc.11.2_463 　

    ISSN： 2185-2839

    eISSN： 2185-2847

  31. Optimization of the Himeno Benchmark for SX-Aurora TSUBASA Peer-reviewed

    Akito Onodera, Kazuhiko Komatsu, Soya Fujimoto, Yoko Isobe, Masayuki Sato, Hiroaki Kobayashi

    Benchmarking, Measuring, and Optimizing　127-143　2021

    Publisher: Springer International Publishing

    DOI： 10.1007/978-3-030-71058-3_8 　

    ISSN： 0302-9743

    eISSN： 1611-3349

  32. A Deep Reinforcement Learning Based Feature Selector Peer-reviewed

    Yiran Cheng, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    Parallel Architectures, Algorithms and Programming　378-389　2021

    Publisher: Springer Singapore

    DOI： 10.1007/978-981-16-0010-4_33 　

    ISSN： 1865-0929

    eISSN： 1865-0937

  33. A Dynamic Parameter Tuning Method for High Performance SpMM Peer-reviewed

    Bin Qi, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    Parallel and Distributed Computing, Applications and Technologies　318-329　2021

    Publisher: Springer International Publishing

    DOI： 10.1007/978-3-030-69244-5_28 　

    ISSN： 0302-9743

    eISSN： 1611-3349

  34. An Efficient Skinny Matrix-Matrix Multiplication Method by Folding Input Matrices into Tensor Core Operations Peer-reviewed

    Hao Tang, Kazuhiko Komatsu, Masayuki Sato, Hiroaki Kobayashi

    2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW)　2020/11

    Publisher: IEEE

    DOI： 10.1109/candarw51189.2020.00041 　

  35. Combinatorial Clustering Based on an Externally-Defined One-Hot Constraint Peer-reviewed

    Masahito Kumagai, Kazuhiko Komatsu, Fumiyo Takano, Takuya Araki, Masayuki Sato, Hiroaki Kobayashi

    2020 Eighth International Symposium on Computing and Networking (CANDAR)　2020/11

    Publisher: IEEE

    DOI： 10.1109/candar51075.2020.00015 　

  36. Importance of Selecting Data Layouts in the Tsunami Simulation Code Peer-reviewed

    Takumi Kishitani, Kazuhiko Komatsu, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi

    2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)　2020/05

    Publisher: IEEE

    DOI： 10.1109/ipdpsw50202.2020.00140 　

  37. Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture Peer-reviewed

    Masayuki Sato, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi

    2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)　2020/04

    Publisher: IEEE

    DOI： 10.1109/coolchips49199.2020.9097643 　

  38. An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems Peer-reviewed

    Supercomputing Frontiers and Innovations　6　(4)　2019/12

    Publisher: FSAEIHE South Ural State University (National Research University)

    DOI： 10.14529/jsfi190401 　

    ISSN： 2313-8734

  39. A Skewed Multi-banked Cache for Many-core Vector Processors Peer-reviewed

    Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

    Supercomputing Frontiers and Innovations　6　(3)　86-101　2019/09

    Publisher: FSAEIHE South Ural State University (National Research University)

    DOI： 10.14529/jsfi190305 　

    ISSN： 2313-8734

  40. A layer-adaptable cache hierarchy by a multiple-layer bypass mechanism

    Ryusuke Egawa, Ryoma Saito, Masayuki Sato, Hiroaki Kobayashi

    PervasiveHealth: Pervasive Computing Technologies for Healthcare　2019/06/06

    Publisher: ICST

    DOI： 10.1145/3337801.3337820 　

    ISSN： 2153-1633

  41. A Hardware Prefetching Mechanism for Vector Gather Instructions. Peer-reviewed

    Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

    IEEE/ACM 9th Workshop on Irregular Applications: Architectures and Algorithms (IA3)　59-66　2019

    Publisher: IEEE

    DOI： 10.1109/IA349570.2019.00015 　

  42. An Appropriate Computing System and Its System Parameters Selection Based on Bottleneck Prediction of Applications. Peer-reviewed

    Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato, Hiroaki Kobayashi

    In Proceedings of the Fourteenth International Workshop on Automatic Performance Tuning　768-777　2019

    Publisher: IEEE

    DOI： 10.1109/IPDPSW.2019.00127 　

  43. Perceptron-based Cache Bypassing for Way-Adaptable Caches Peer-reviewed

    Masayuki Sato, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi

    2019 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS (COOL CHIPS 22)　1-3　2019

    DOI： 10.1109/CoolChips.2019.8721331 　

    ISSN： 2473-4683

  44. Optimizing Memory Layout of Hyperplane Ordering for Vector Supercomputer SX-Aurora TSUBASA Peer-reviewed

    Osamu Watanabe, Yuta Hougi, Kazuhiko Komatsu, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi

    PROCEEDINGS OF MCHPC'19: 2019 IEEE/ACM WORKSHOP ON MEMORY CENTRIC HIGH PERFORMANCE COMPUTING (MCHPC)　25-32　2019

    DOI： 10.1109/MCHPC49590.2019.00011 　

  45. Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA. Peer-reviewed

    Akihiro Musa, Takashi Abe, Takumi Kishitani, Takuya Inoue, Masayuki Sato, Kazuhiko Komatsu, Yoichi Murashima, Shunichi Koshimura, Hiroaki Kobayashi

    Computational Science - ICCS 2019 - 19th International Conference, Faro, Portugal, June 12-14, 2019, Proceedings, Part II　363-376　2019

    Publisher: Springer

    DOI： 10.1007/978-3-030-22741-8_26 　

  46. An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches Peer-reviewed

    Sato, M., Shoji, Y., Sakai, Z., Egawa, R., Kobayashi, H.

    IEEE Transactions on Multi-Scale Computing Systems　4　(4)　593-604　2018/10/01

    Publisher: Institute of Electrical and Electronics Engineers ({IEEE})

    DOI： 10.1109/TMSCS.2018.2827955 　

  47. メニーコアプロセッサのためのパラメータチューニング時間削減手法

    岸谷 拓海, 小松 一彦, 撫佐 昭裕, 佐藤 雅之, 小林 広明

    並列／分散／協調処理に関する『熊本』サマー・ワークショップ　2018/07

  48. マルチベクトルコアプロセッサの共有キャッシュ構成に関する一検討,

    高屋敷 光, 佐藤 雅之, 小松 一彦, 江川 隆輔, 小林 広明

    並列／分散／協調処理に関する『熊本』サマー・ワークショップ　2018/07

  49. An energy-aware set-level refreshing mechanism for eDRAM last-level caches Peer-reviewed

    Masayuki Sato, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi

    21st IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL Chips 2018 - Proceedings　1-3　2018/06/05

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/CoolChips.2018.8373082 　

  50. Performance Evaluation of a Real-Time Tsunami Inundation Forecast System on Modern Supercomputers Peer-reviewed

    Akihiro Musa, Takumi Kishitani, Takuya Inoue, Hiroaki Hokari, Masayuki Sato, Kazuhiko Komatsu, Yoichi Murashima, Shunichi Koshimura, Hiroaki Kobayashi

    15th Annual Meeting Asia Oceania Geoscience Society　2018/06

    DOI： 10.20965/jdr.2018.p0234 　

  51. Early Evaluation of a New Vector Processor SX-Aurora TSUBASA Peer-reviewed

    Kazuhiko Komatsu, Shintaro Momose, Yoko Isobe, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi

    Poster Proceedings of International Supercomputing Conference　2018/06

  52. Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor Peer-reviewed

    Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi

    2018 IEEE 12TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANY-CORE SYSTEMS-ON-CHIP (MCSOC 2018)　117-124　2018

    DOI： 10.1109/MCSoC2018.2018.00030 　

  53. Performance Evaluation of a Vector Supercomputer SX-Aurora TSUBASA Peer-reviewed

    Kazuhiko Komatsu, Shintaro Momose, Yoko Isobe, Osamu Watanabe, Akihiro Musa, Mitsuo Yokokawa, Toshikazu Aoyama, Masayuki Sato, Hiroaki Kobayashi

    PROCEEDINGS OF THE INTERNATIONAL CONFERENCE FOR HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE, AND ANALYSIS (SC'18)　2018

  54. A Multiple-layer Bypass Mechanism for Energy-Efficient Computing Peer-reviewed

    Ryusuke Egawa, Masayuki Sato, Ryoma Saito, Hiroaki Kobayashi

    In Proceedings of 26th Workshop on Sustained Simulation Performance　2017/10

  55. Early Evaluation of a Heterogeneous Memory Architecture on a Vector Supercomputer

    Ryosuke Sato, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi

    Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers　2017　20-20　2017/08

    Publisher: Organizing Committee of Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, Japan

    DOI： 10.11528/tsjc.2017.0_20 　

  56. A power-aware LLC control mechanism for the 3D-stacked memory system Peer-reviewed

    Ryusuke Egawa, Wataru Uno, Masayuki Sato, Hiroaki Kobayashi, Jubee Tada

    2016 IEEE International 3D Systems Integration Conference, 3DIC 2016　2017/07/05

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/3DIC.2016.7970034 　

  57. An Adaptive Demotion Policy for High-Associativity Caches Peer-reviewed

    Jubee Tada, Masayuki Sato, Ryusuke Egawa

    ACM International Conference Proceeding Series　2017/06/07

    Publisher: Association for Computing Machinery

    DOI： 10.1145/3120895.3120906 　

  58. An Adjacent-Line-Merging Writeback Scheme for STT-RAM Last-Level Caches Peer-reviewed

    Masayuki Sato, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi

    2017 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS (COOL CHIPS)　2017

    DOI： 10.1109/CoolChips.2017.7946380 　

    ISSN： 2473-4683

  59. An Application-adaptive Data Allocation Method for Multi-channel Memory Peer-reviewed

    Takuya Toyoshima, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi

    2017 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS (COOL CHIPS)　2017

    DOI： 10.1109/CoolChips.2017.7946381 　

    ISSN： 2473-4683

  60. 高バンド幅メモリのための省電力データ配置手法に関する研究

    豊嶋 拓也, 佐藤 雅之, 江川 隆輔, 小林 広明

    東北支部大会連合大会予稿集　2016　39-39　2016/08

    Publisher:

    DOI： 10.11528/tsjc.2016.0_39 　

  61. A Power-Performance Tradeoff of HBM by Limiting Access Channels Peer-reviewed

    Takuya Toyoshima, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    Proceedings of IEEE Symposium on Low-Power and High-Speed Chips　2016/04

  62. アプリケーション適応型キャッシュリサイズのためのバイパス機構 Peer-reviewed

    佐藤 雅之, 高井 拓実, 江川 隆輔, 滝沢 寛之, 小林 広明

    電子情報通信学会論文誌　J99-D　(3)　2016/03

  63. A Cache Partitioning Mechanism to Protect Shared Data for CMPs Peer-reviewed

    Masayuki Sato, Shin Nishimura, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    2016 IEEE SYMPOSIUM IN LOW-POWER AND HIGH-SPEED CHIPS (COOL CHIPS XIX)　2016

    DOI： 10.1109/CoolChips.2016.7503674 　

    ISSN： 2473-4683

  64. 三次元積層時代における高電力効率メモリ階層設計

    宇野 渉, 佐藤 雅之, 江川 隆輔, 小林 広明

    信学技報　115　(271)　19-24　2015/10

    Publisher:

    ISSN： 0913-5685

  65. マルチコアプロセッサのためのスレッド間共有データを考慮したキャッシュ機構

    西村 秦, 佐藤 雅之, 江川 隆輔, 小林 広明

    研究報告計算機アーキテクチャ（ARC）　2015-ARC-216　(38)　1-8　2015/08

  66. FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms Peer-reviewed

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    IEICE TRANSACTIONS ON ELECTRONICS　E98C　(7)　550-558　2015/07

    DOI： 10.1587/transele.E98.C.550 　

    ISSN： 1745-1353

  67. A Data Management Policy for Energy-Efficient Cache Mechanisms

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    Sustained Simulation Performance 2015　61-75　2015

    DOI： 10.1007/978-3-319-20340-9_6 　

  68. An Energy-Efficient Dynamic Memory Address Mapping Mechanism Peer-reviewed

    Masayuki Sato, Chengguang Han, Kazuhiko Komatsu, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    2015 IEEE SYMPOSIUM ON LOW-POWER AND HIGH-SPEED CHIPS　1-3　2015

    DOI： 10.1109/CoolChips.2015.7158660 　

  69. MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications Peer-reviewed

    Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E97D　(11)　2835-2843　2014/11

    DOI： 10.1587/transinf.2014EDP7227 　

    ISSN： 1745-1361

  70. High-Performance and Low-Power Memory Hierarchy toward Next-Generation Extreme Computing

    Masayuki Sato

    ATIP Workshop: Japanese Research Toward Next-Generation Extreme Computing　2014/11

  71. ベクトル型メディアプロセッサの低消費電力化に関する研究

    宇野 渉, 高 也, 佐藤 雅之, 江川 隆輔, 滝沢 寛之, 小林 広明

    電気関係学会東北支部連合大会予稿集　2014/08

  72. キャッシュメモリにおけるスレッド間共有データの管理に関する研究

    西村 秦, 佐藤 雅之, 江川 隆輔, 滝沢 寛之, 小林 広明

    電気関係学会東北支部連合大会予稿集　2014/08

  73. An Energy Optimization Method for Vector Processing Mechanisms Peer-reviewed

    Ye Gao, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    2014 IEEE COOL CHIPS XVII　1-3　2014

    DOI： 10.1109/CoolChips.2014.6842957 　

    ISSN： 2473-4683

  74. On-Chip Checkpointing with 3D-Stacked Memories Peer-reviewed

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    2014 INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC)　2014

    DOI： 10.1109/3DIC.2014.7152173 　

    ISSN： 2164-0157

  75. A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts Peer-reviewed

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E96D　(9)　2047-2054　2013/09

    DOI： 10.1587/transinf.E96.D.2047 　

    ISSN： 1745-1361

  76. ブロックバイパス機構によるキャッシュのエネルギ効率化に関する研究

    高井 拓実, 佐藤 雅之, 江川 隆輔, 滝沢 寛之, 小林 広明

    並列/分散/協調処理に関する「北九州」サマー・ワークショップ (SWoPP2013)　1-9　2013/07

  77. Checkpoint-Restart for Heterogeneous Computing Systems Invited

    滝沢寛之, 佐藤雅之, 江川隆輔, 小林広明

    Reliability Engineering Association of Japan　35　(8)　515　2013

    DOI： 10.11348/reajshinrai.35.8_515 　

  78. A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms Peer-reviewed

    Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    2013 IEEE COOL CHIPS XVI (COOL CHIPS)　1-3　2013

    DOI： 10.1109/CoolChips.2013.6547923 　

    ISSN： 2473-4683

  79. Vertically Integrated Processor and Memory Module Design for Vector Supercomputers Peer-reviewed

    Ryusuke Egawa, Masayuki Sato, Jubee Tada, Hiroaki Kobayashi

    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC)　1-6　2013

    DOI： 10.1109/3DIC.2013.6702377 　

    ISSN： 2164-0157

  80. ウェイ適応型キャッシュの高エネルギ効率化のためのデッドブロック早期追い出しポリシ Peer-reviewed

    東方 雄亮, 佐藤 雅之, 江川 隆輔, 滝沢 寛之, 小林 広明

    先進的計算基盤シンポジウムSACSIS2012　2012　4-5　2012/05

  81. A Bypass Mechanism for Way-Adaptable Caches Peer-reviewed

    Takumi Takai, Yusuke Tobo, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    Poster Proceedings of COOLChips XV　1　2012/04

  82. A capacity-efficient insertion policy for dynamic cache resizing mechanisms Peer-reviewed

    Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    CF '12 - Proceedings of the ACM Computing Frontiers Conference　265-267　2012

    DOI： 10.1145/2212908.2212949 　

  83. ウェイ適応型キャッシュのための低消費エネルギ指向挿入ポリシ Peer-reviewed

    東方 雄亮, 佐藤 雅之, 江川 隆輔, 滝沢 寛之, 小林 広明

    先進的計算基盤シンポジウムSACSIS2011　2011　213-214　2011/05

  84. Power-aware insertion policy for the way-adaptable caches Peer-reviewed

    Yusuke Tobo, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    IEEE COOL Chips XIV　2011/04

  85. A Power-Aware Insertion Policy for the Way-Adaptable Cache Mechanism Peer-reviewed

    Yusuke Tobo, Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    Poster Proceedings of COOLChips XIV　1　2011/04

  86. A Majority-Based Control Scheme for Way-Adaptable Caches Peer-reviewed

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    FACING THE MULTICORE-CHALLENGE: ASPECTS OF NEW PARADIGMS AND TECHNOLOGIES IN PARALLEL COMPUTING　6310　16-+　2010

    DOI： 10.1007/978-3-642-16233-6_5 　

    ISSN： 0302-9743

    eISSN： 1611-3349

  87. A Voting-Based Working Set Assessment Scheme for Dynamic Cache Resizing Mechanisms Peer-reviewed

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN　98-105　2010

    DOI： 10.1109/ICCD.2010.5647599 　

    ISSN： 1063-6404

  88. Working Sets based Thread Scheduling with Cache Partitioning Peer-reviewed

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    Poster Abstracts of The Eighteenth International Conference on Parallel Architecture and Compilation Techniques　12　2009/09

  89. ワーキングセット評価に基づくスレッドスケジューリング

    佐藤 雅之, 小寺 功, 江川 隆輔, 滝沢 寛之, 小林 広明

    並列/分散/協調処理に関する「仙台」サマー・ワークショップ (SWoPP仙台2009)　1-10　2009/08

  90. A Cache-Aware Thread Scheduling Policy for Multi-Core Processors Peer-reviewed

    Masayuki Sato, Isao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks　109-114　2009/02

  91. SMTプロセッサの実行時性能予測のためのハードウェアリソース競合解析 Peer-reviewed

    佐藤 雅之, 船矢 祐介, 小寺 功, 滝沢 寛之, 小林 広明

    第6回情報科学技術フォーラム(FIT2007)情報科学技術レターズ　67-70　2007/09

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Misc. 1

  1. リアルタイム津波浸水被害推計シミュレーションの性能評価

    撫佐 昭裕, 岸谷 拓海, 阿部 孝志, 佐藤 佳彦, 田野 邊睦, 鈴木 崇之, 村嶋 陽一, 佐藤 雅之, 小松 一彦, 伊達 進, 越村 俊一, 小林 広明

    SENAC : 東北大学大型計算機センター広報　53　(2)　10-18　2020/04

    Publisher: 東北大学サイバーサイエンスセンター

    ISSN： 0286-7419

Presentations 4

  1. MICRO 2024における研究動向 Invited

    佐藤 雅之

    第66回AIチップ設計拠点フォーラム　2024/12/27

  2. Analysis of Memory Systems of Clustered Architecture Invited

    Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

    36th Workshop on Sustained Simulation Performance　2023/12

  3. A Multiple-layer Bypass Mechanism for Energy Efficient Computing Invited

    Ryusuke Egawa, Masayuki Sato, Ryoma Saito, Hiroaki Kobayashi

    26th Workshop on Sustained Simulation Performance　2017/10

  4. Energy-efficient Memory Hierarchy toward Future Computing Systems Invited

    Masayuki Sato, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

    21st Workshop on Sustained Simulation Performance　2015/02

Industrial Property Rights 4

  1. 映像符号化装置用キャッシュメモリ

    大森 優也, 佐藤 雅之, 江川 隆輔, 小林 広明, 中村 健, 小林 大祐, 岩崎 裕江

    特許7425446

    Property Type: Patent

  2. 映像符号化装置用キャッシュメモリ

    大森 優也, 江川 隆輔, 佐藤 雅之, 小林 広明, 中村 健, 小林 大祐, 岩崎 裕江

    特許7406206

    Property Type: Patent

  3. 映像符号化装置用キャッシュメモリ

    大森 優也, 江川 隆輔, 佐藤 雅之, 小林 広明, 中村 健, 小林 大祐, 岩崎 裕江

    特許7416380

    Property Type: Patent

  4. 多階層キャッシュメ モリの制御方法，及び多階層キャッシュメモリの制御プログラム

    大森 優也, 大西 隆之, 岩崎 裕江, 清水 淳, 江川 隆 輔, 佐藤 雅之, 小林 広明

    特許7142289

    Property Type: Patent

Research Projects 9

  1. 量子・古典ハイブリッド計算によるソフトマテリアル研究開発デジタルツインの創成

    小林 広明, 撫佐 昭裕, 阿部 圭晃, 佐藤 雅之, 小松 一彦, 菊川 豪太

    Offer Organization: 日本学術振興会

    System: 科学研究費助成事業

    Category: 基盤研究(B)

    Institution: 東北大学

    2024/04/01 - 2028/03/31

  2. 大規模量子コンピューティングによる新計算原理計算基盤の創生

    小松 一彦, 小林 広明, 佐藤 雅之, 百瀬 真太郎

    Offer Organization: 日本学術振興会

    System: 科学研究費助成事業 基盤研究(B)

    Category: 基盤研究(B)

    Institution: 東北大学

    2023/04 - 2028/03

  3. Real-time video coding technology using the latest coding VVC/H.266 and its applications

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research

    Category: Grant-in-Aid for Scientific Research (B)

    Institution: Tokyo University of Agriculture and Technology

    2022/04/01 - 2025/03/31

  4. Quantum-Annealing Assisted Innovative Material Informatics Infrastructure

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)

    Category: Grant-in-Aid for Scientific Research (A)

    Institution: Tohoku University

    2019/04/01 - 2023/03/31

  5. 複合型メインメモリのための次世代型メモリ管理方式の創出

    佐藤 雅之

    Offer Organization: 日本学術振興会

    System: 科学研究費助成事業 若手研究

    Category: 若手研究

    Institution: 東北大学

    2019/04/01 - 2023/03/31

    More details Close

    次世代のメモリシステムとして，高バンド幅積層メモリモジュールと大容量外部メモリモジュールを併用した複合型メインメモリが注目されている．一方で，複合型メインメモリでは，2つのモジュールに分けて保存されるデータをアプリケーションの実行状況に合わせてどう管理するかが性能向上や低消費電力化への課題となる．このことから，複合型メインメモリが将来主流になることを見据え，高効率なデータ管理方式を実現することを目的とし，研究を遂行してきた． 本年度は特にアーキテクチャレベルによる高性能・低消費電力なメモリ管理機構に取り組んだ．特に，複合型メインメモリのための低オーバーヘッドメモリ管理戦略に関する管理方式の具体的な手法について検討を行った．本複合型メインメモリでは広いメモリ空間を管理するためのメタデータ保持コストを抑制しつつ，実行時の性能・電力オーバーヘッドを削減する必要がある．そこで，昨年度から継続していたメタデータに対するアクセスパターンの分析を詳細化した．その結果，少なくないアプリケーションにおいて，現在のアクセスと次のアクセスのメモリ空間上での相対的な位置関係が規則的である性質を明らかにした．さらに，近い将来にアクセスされるメタデータを事前にメモリコントローラ内のメタデータキャッシュにプリフェッチする機構の設計を行った．本機構は，メモリ空間上のある位置にアクセスが発生した場合，上記の性質に基づき次のアクセスの相対的な位置を予測し，その位置に関するメタデータをメタデータキャッシュにプリフェッチする．本機構によりメモリコントローラ内でのメタデータ保持コストを削減しつつ，メモリアクセスレイテンシを削減することが可能である．

  6. Design Space Exploration of Future Microprocessors using the post CMOS devices

    EGAWA Ryusuke, Kobayashi Hiroaki, Takizawa Hiroyuki, Tada Jubee, Sato Masayuki, Uno Wataru, Toyoshima Takuya, Sakai Zentaro, Ogasawara Daisuke

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research

    Category: Grant-in-Aid for Challenging Exploratory Research

    Institution: Tohoku University

    2015/04/01 - 2018/03/31

    More details Close

    In this research, for realizing a high energy efficiency microprocessor using novel device technologies in the post-Moore's era, expected to be practical around 2025, we have worked on circuits and memory subsystems designs. Regarding the circuit design, we worked on the design method of wave-pipelined circuits using CNFET. For the memory subsystem, we focus on a die stacking and STT-RAM technologies. We have examined the cache-bypass mechanism, the energy efficient data allocation method for the multi-bank memory, and the power-aware controlling mechanism for STT-RAM last-level caches.

  7. High-performance and Low-Power Memory Management for the Era of Many-Channel Memories Competitive

    Sato Masayuki, Kobayashi Hiroaki, Egawa Ryusuke, Toyoshima Takuya

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Research Activity Start-up

    Category: Grant-in-Aid for Research Activity Start-up

    Institution: Tohoku University

    2016 - 2018

    More details Close

    This project proposes the high-performance and low-power management mechanism for many-channel memories, which is realized by the address-mapping schemes that limit the number of accessed channels, and the memory controller that can switch the address-mapping schemes. The proposed address-mapping schemes change where the channel address is taken from bits of the physical address. These schemes successfully limit the number of channels accessed by executing applications, and the performance/power trade-off can be selected by switching these schemes. The proposed memory controller can dynamically switch the address-mapping schemes. It also realizes the migration of the application data to maintain the consistency of the data placement when switching the address-mapping schemes. The evaluation results show that the memory controller can be realized by the reasonable costs of hardware and data migration.

  8. A Green Microarchitecure in 5.5D-Design Era

    EGAWA RYUSUKE, Kobayashi Hiroaki, Takizawa Hiroyuki, Sato Masayuki, Uno Wataru, Nishimura Shin, Hosokawa Mikio, Toyoshima Takuya

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    Category: Grant-in-Aid for Scientific Research (B)

    Institution: Tohoku University

    2014/04/01 - 2017/03/31

    More details Close

    To clarify the design space of future microprocessors after the end of moor’s law, this research project focuses on vertical integration technologies such as 2.5D and 3D technologies using a through silicon via (TSV). Since the TSVs have a high potential of shortening the latency and reducing the power consumption in/of microprocessors and computing systems, these technologies are expected to overcome the limits of technology scaling. In this research, we explore the design space of the future microprocessors by aggressively using TSVs in various stacking granularities. The evaluation results show that appropriate usage of TSVs with considering a trade-off among performance, power, and cost can drastically improve the energy efficiency of the microprocessors and computer systems.

  9. Study on Hardware-Software Collaborative Scheduling for Highly Efficient Multithreading

    KOBAYASHI Hiroaki, NAKAMURA Tadao, SUZUKI Kenichi, TAKIZAWA Hiroyuki, EGAWA Ryusuke, SATO Yukinori, KOTERA Isao, FUNAYA Yusuke, SATO Masayuki

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    Category: Grant-in-Aid for Scientific Research (B)

    Institution: Tohoku University

    2006 - 2009

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Teaching Experience 9

  1. アーキテクチャ学

  2. Fundamentals of Information Sciences II　Tohoku University

  3. 情報処理演習　東北大学

  4. 機械知能・航空実験II　東北大学

  5. Fundamentals of Information Sciences I　Tohoku University

  6. 機械知能・航空実験I　東北大学

  7. 基礎ゼミ　東北大学

  8. 創造工学研修　東北大学

  9. 基礎ゼミ　東北大学

Show all Show first 5