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40 nm 1T-1MTJ 128 Mb STT-MRAM With Novel Averaged Reference Voltage Generator Based on Detailed Analysis of Scaled-Down Memory Cell Array Design
Hiroki Koike, Takaho Tanigawa, Toshinari Watanabe, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Toru Yoshiduka, Yitao Ma, Hiroaki Honjo, Koichi Nishioka, Sadahiko Miura, Hirofumi Inoue, Shoji Ikeda, Tetsuo Endoh
IEEE TRANSACTIONS ON MAGNETICS 57 (3) 2021/03
DOI：
10.1109/TMAG.2020.3038110
ISSN：
0018-9464
eISSN：
1941-0069
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Review of STT-MRAM circuit design strategies, and a 40-nm 1T-1MTJ 128Mb STT-MRAM design practice
Hiroki KOIKE, Takaho TANIGAWA, Toshinari WATANABE, Takashi NASUNO, Yasuo NOGUCHI, Mitsuo YASUHIRA, Toru YOSHIDUKA, Yitao MA, Hiroaki HONJO, Koichi NISHIOKA, Sadahiko MIURA, Hirofumi INOUE, Shoji IKEDA, Tetsuo ENDOH
2020 IEEE 31st Magnetic Recording Conference (TMRC) 2020/08/17
Publisher:
IEEE
DOI：
10.1109/tmrc49521.2020.9366711
-
First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400℃ thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology
Peer-reviewed
H. Honjo, T. V. A. Nguyen, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, S. Miura, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, A. Tamakoshi, M. Natsui, Y. Ma, H. Koike, Y. Takahashi, K. Furuya, H. Shen, S. Fukami, H. Sato, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
International Electron Device Meeting 2019-December 2019/12
DOI：
10.1109/IEDM19573.2019.8993443
ISSN：
0163-1918
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12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Digest of Technical Papers - IEEE International Solid-State Circuits Conference 2019-February 202-204 2019/03/06
DOI：
10.1109/ISSCC.2019.8662431
ISSN：
0193-6530
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A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
Peer-reviewed
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
J. Solid-State Circuits 54 (11) 2991-3004 2019
DOI：
10.1109/JSSC.2019.2930910
ISSN：
0018-9200
eISSN：
1558-173X
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A Fully Nonvolatile Microcontroller Unit with Embedded STT-MRAM and FPGA-Based Accelerator for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology
Peer-reviewed
M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, T. Hanyu
IEEE Journal of Solid State Circuits 54 (11) 2991-3004 2019
DOI：
10.1109/JSSC.2019.2930910
ISSN：
0018-9200
eISSN：
1558-173X
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14ns write speed 128Mb density Embedded STT-MRAM with endurance>10^10 and 10yrs retention @85°C using novel low damage MTJ integration process
Peer-reviewed
H. Sato, H. Honjo, T. Watanabe, M. Niwa, H. Koike, S. Miura, T. Saito, H. Inoue, T. Nasuno, T. Tanigawa, Y. Noguchi, T. Yoshiduka, M. Yasuhira, S. Ikeda, S.- Y. Kang, T. Kubo, K. Yamashita, Y. Yagi, R. Tamura, T. Endoh
International Electron Devise Meeting 2018-December 27.2.1-27.2.4 2018/12
DOI：
10.1109/IEDM.2018.8614606
ISSN：
0163-1918
-
1T-1MTJ Type Embedded STT-MRAM with Advanced Low-Damage and Short-Failure-Free RIE Technology down to 32 nmφ MTJ Patterning
Peer-reviewed
Hideo Sato, Toshinari Watanabe, Hiroki Koike, Takashi Saito, Sadahiko Miura, Hiroaki Honjo, Hirofumi Inoue, Shoji Ikeda, Yasuo Noguchi, Takaho Tanigawa, Mitsuo Yasuhira, Hideo Ohno, Song Yun Kang, Takuya Kubo, Koichi Takatsuki, Koji Yamashita, Yasushi Yagi, Ryo Tamura, Takuro Nishimura, Koh Murata, Tetsuo Endoh
2018 IEEE International Memory Workshop (IMW) 1-4 2018/05
Publisher:
IEEE
DOI：
10.1109/imw.2018.8388774
-
Impact of Tungsten Sputtering Condition on Magnetic and Transport Properties of Double-MgO Magnetic Tunneling Junction With CoFeB/W/CoFeB Free Layer
Peer-reviewed
H. Honjo, S. Ikeda, H. Sato, K. Nishioka, T. Watanabe, S. Miura, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, H. Koike, H. Inoue, M. Muraguchi, M. Niwa, H. Ohno, T. Endoh
IEEE TRANSACTIONS ON MAGNETICS 53 (11) 2017/11
DOI：
10.1109/TMAG.2017.2701838
ISSN：
0018-9464
eISSN：
1941-0069
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Origin of variation of shift field via annealing at 400 degrees C in a perpendicular-anisotropy magnetic tunnel junction with [Co/Pt]-multilayers based synthetic ferrimagnetic reference layer
Peer-reviewed
H. Honjo, S. Ikeda, H. Sato, T. Watanebe, S. Miura, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, H. Koike, M. Muraguchi, M. Niwa, K. Ito, H. Ohno, T. Endoh
AIP ADVANCES 7 (5) 2017/05
DOI：
10.1063/1.4973946
ISSN：
2158-3226
-
Beyond MRAM: Nonvolatile Logic-in-Memory VLSI
Peer-reviewed
Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, Hideo Ohno
Introduction to Magnetic Random-Access Memory 199-229 2016/11/26
Publisher:
wiley
DOI：
10.1002/9781119079415.ch7
-
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing
Invited
Peer-reviewed
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
PROCEEDINGS OF THE IEEE 104 (10) 1844-1863 2016/10
DOI：
10.1109/JPROC.2016.2574939
ISSN：
0018-9219
eISSN：
1558-2256
-
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design
Peer-reviewed
M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, T. Hanyu
Proceedings - IEEE International Symposium on Circuits and Systems 2016- 1878-1881 2016/07/29
Publisher:
Institute of Electrical and Electronics Engineers Inc.
DOI：
10.1109/ISCAS.2016.7538938
ISSN：
0271-4310
-
Improvement of Thermal Tolerance of CoFeB-MgO Perpendicular-Anisotropy Magnetic Tunnel Junctions by Controlling Boron Composition
Peer-reviewed
H. Honjo, S. Ikeda, H. Sato, S. Sato, T. Watanabe, S. Miura, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, H. Koike, M. Muraguchi, M. Niwa, K. Ito, H. Ohno, T. Endoh
IEEE TRANSACTIONS ON MAGNETICS 52 (7) 2016/07
DOI：
10.1109/TMAG.2016.2518203
ISSN：
0018-9464
eISSN：
1941-0069
-
An Overview of Nonvolatile Emerging Memories-Spintronics for Working Memories
Invited
Peer-reviewed
Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 6 (2) 109-119 2016/06
DOI：
10.1109/JETCAS.2016.2547704
ISSN：
2156-3357
-
Optimum boron concentration difference between single and double CoFeB/MgO interface perpendicular MTJs with high thermal tolerance and its mechanism
Peer-reviewed
H. Honjo, H. Sato, S. Ikeda, S. Sato, T. Watanebe, S. Miura, T. Nasuno, Y. Noguchi, M.Yasuhira, T.Tanigawa, H.Koike, M.Muraguchi, M.Niwa, K.Ito, H.Ohno, T.Endoh
13th Joint MMM-Intermag Conference FB-06 2016/01/14
-
Demonstration of yield improvement for on-via MTJ using a 2-Mbit 1T-1MTJ STT-MRAM test chip
Peer-reviewed
Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Toshinari Watanabe, Hideo Sato, Soshi Sato, Takashi Nasuno, Yasuo Noguchi, Mitsuo Yasuhira, Takaho Tanigawa, Masakazu Muraguchi, Masaaki Niwa, Kenchi Ito, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh
2016 IEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW) 2016
DOI：
10.1109/imw.2016.7495264
ISSN：
2330-7978
-
10 nm perpendicular anisotropy CoFeB-MgO magnetic tunnel junction with over 400oC high thermal tolerance by boron diffusion control
Peer-reviewed
H. Honjo, H. Sato, S. Ikeda, S. Sato, T. Watanebe, S. Miura, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, H. Koike, M. Muraguchi, M. Niwa, K. Ito, H. Ohno, T. Endoh
2015 Symposia on VLSI technology 2015-August T160-T161 2015/06/18
DOI：
10.1109/VLSIT.2015.7223661
ISSN：
0743-1562
-
1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance
Peer-reviewed
H. Koike, S. Miura, H. Honjo, T. Watanabe, H. Sato, S. Sato, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, M. Muraguchi, M. Niwa, K. Ito, S. Ikeda, H. Ohno, T. Endoh
2015 IEEE International Memory Workshop 1-4 2015/05/17
DOI：
10.1109/IMW.2015.7150264
-
Properties of perpendicular-anisotropy magnetic tunnel junctions fabricated over the bottom
Peer-reviewed
S. Miura, H. Honjo, K. Kinoshita, K. Tokutome, H. Koike, S. Ikeda, T. Endoh, H. Ohno
Japanese Journal of Applied Physics 54 (4) 04DM06-1-04DM06-4 2015/03/11
DOI：
10.7567/JJAP.54.04DM06
ISSN：
0021-4922
eISSN：
1347-4065
-
Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation
Peer-reviewed
Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
Japanese Journal of Appllied Physics 54 (4) 2015
DOI：
10.7567/JJAP.54.04DE08
ISSN：
0021-4922
eISSN：
1347-4065
-
A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instraction Achieving Ultra-low Power Operation
Peer-reviewed
H. Koike, T. Ohsawa, S. Miura, H. Honjo, K, Kinoshita, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
International Conference on Solid State Dvices and Materails (SSDM) A-7-1 2014/09/09
-
Properties of Perpendicular-Anisotrapy Magnetic Tunnel Junctions Fabricated over the Cu Via
Peer-reviewed
S. Miura, H. Honjo, K. Kinoshita, K. Tokutome, H, Koike, S. Ikeda, T. Endoh, H. Ohno
International Conference on Solid State Dvices and Materails (SSDM) A-6-3 2014/09/09
-
1.5ns/2.1nsのランダム読出／書込サイクル時間を達成した不揮発性混載メモリ用1Mb STT-MRAM －6T2MTJセルにバックグラウンド書き込み（BGW）方式を適用
Invited
Peer-reviewed
大澤隆, 小池洋紀, 三浦貞彦, 木下啓藏, 本庄弘明, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎
信学技報 114 (13) 33-38 2014/04/17
-
MTJベース不揮発フリップフロップを用いた3μsec-Entry/Exit 遅延時間のマイクロプロセッサ
Invited
Peer-reviewed
小池洋紀, 崎村昇, 根橋竜介, 辻幸秀, 森岡あゆ香, 三浦貞彦, 本庄弘明, 杉林直彦, 大澤隆, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎
信学技報 114 (13) 85-90 2014/04/17
-
Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell
Peer-reviewed
Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
JAPANESE JOURNAL OF APPLIED PHYSICS 53 (4) 2014/04
DOI：
10.7567/JJAP.53.04ED13
ISSN：
0021-4922
eISSN：
1347-4065
-
A 1Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell with 32b Fine-Grained Power Gating Scheme
Peer-reviewed
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno
IEEE Journal of Solid State Circuits 48 (6) 1511-1520 2014
DOI：
10.1109/JSSC.2013.2253412
ISSN：
0018-9200
-
MTJ Resistance Distribution of 1-kbit 1T-1MTJ STT-MRAM Cell Arrays Fabricated on a 300-mm Wafer
Peer-reviewed
Hiroki Koike, Takashi Ohsawa, Katsuya Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
The 58th Annual Magnetism and Magnetic Materials Conference (MMM2013) DC-01 324-324 2013/11/04
-
Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell
Peer-reviewed
Hiroki Koike, Takashi Ohsawa, Sadahiro Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh
2013 International Conference on Solid State Devices and Materials (SSDM) M-7-3 1094-1095 2013/09/24
-
IEEE Journal of Solid-State Circuits
Peer-reviewed
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme 48 (6) 1511-1520 2013/06/22
-
A 1Mb STT-MRAM with Zero Array Standby Power and 1.5ns Quick Wake-up by 8b Fine-Grained Power Gating
Peer-reviewed
Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh
5th IEEE International Memory Workshop (IMW) 80-83 2013/05/26
DOI：
10.1109/IMW.2013.6582103
-
A fine-grained power gating architecture for MTJ-based embedded memories
Peer-reviewed
Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
The 3nd CSIS International Symposium on Spintronics-based VLSIs 2013/01/31
-
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop
H. Koike, T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, S. Miura, H. Honjo, T. Sugibayashi
Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 317-320 2013
DOI：
10.1109/ASSCC.2013.6691046
-
Restructuring of Memory Hierarchy in Computing System with Spintronics-Based Technologies
Invited
Peer-reviewed
Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno
2012 Symposia on VLSI Technology and Circuits T1003 89-90 2012/06/11
DOI：
10.1109/VLSIT.2012.6242475
-
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique with 1.0ns/200ps Wake-up/Power-off Times
Peer-reviewed
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
2012 Symposium on VLSI Circuits, Digest of Technical Papers J-C6.3 46-47 2012/06
DOI：
10.1109/VLSIC.2012.6243782
-
High-Speed Simulator including Accurate MTJ Models for Spintronics Integrated Circuit Design
Peer-reviewed
Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh
2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) 1971-1974 2012
DOI：
10.1109/ISCAS.2012.6271663
ISSN：
0271-4302
-
A new sensing scheme with high signal margin suitable for Spin-Transfer Torque RAM
Peer-reviewed
Hiroki Koike, Tetsuo Endoh
International Symposium on VLSI Technology, Systems, and Applications, Proceedings 56-57 2011
DOI：
10.1109/VTSA.2011.5872230
-
A 600MHz MTJ-based nonvolatile latch making use of incubation time in MTJ switching
T. Endoh, S. Togashi, F. Iga, Y. Yoshida, T. Ohsawa, H. Koike, S. Fukami, S. Ikeda, N. Kasai, N. Sakimura, T. Hanyu, H. Ohno
Technical Digest - International Electron Devices Meeting, IEDM 2011
DOI：
10.1109/IEDM.2011.6131487
ISSN：
0163-1918
-
Characteristics of 0.25.MU.m Ferroelectric Nonvolatile Memory with a Pb(Zr, Ti)O3 Capacitor on a Metal/via-Stacked Plug.
Amanuma Kazushi, Kobayashi Sota, Tatsumi Toru, Maejima Yukihiko, Hada Hiromitsu, Yamada Junichi, Miwa Tohru, Koike Hiroki, Toyoshima Hideo, Kunio Takemitsu
Japanese Journal of Applied Physics 39 (4) 2098-2101 2000
Publisher:
The Japan Society of Applied Physics
DOI：
10.1143/JJAP.39.2098
ISSN：
0021-4922
