Details of the Researcher

PHOTO

Hasitha Muthumala Waidyasooriya
Section
Graduate School of Information Sciences
Job title
Associate Professor

Research Areas 1

  • Informatics / Computer systems /

Awards 5

  1. 石田實記念財団研究奨励賞

    2024/11　石田實記念財団

  2. エレクトロニクスシミュレーション研究会優秀論文発表賞

    2017/03　エレクトロニクスシミュレーション研究会

  3. トーキン財団奨励賞

    2017/03　トーキン科学技術振興財団

  4. 電子情報通信学会東北支部学生員奨励賞

    2006/03　電子情報通信学会

  5. なし

    2006/03　Tohoku University

Papers 64

  1. Multi-FPGA Acceleration of Simulated Quantum Annealing for Route Optimization in Commercial AGV Operating Systems

    Thinh Nguyen Quang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Jumpei Suzuki, Ziyi Chen, Hasitha Muthumala Waidyasooriya, Nishio Kosei, Masanori Hariyama, Masaru Hitomi, Kenta Sawamura, Tomohisa Okada, Masayuki Ohzeki

    IEEE Access　2026

    DOI： 10.1109/ACCESS.2026.3717906 　

  2. Quantum annealing-based route optimization for commercial AGV operating systems in large-scale logistics warehouses

    Thinh Nguyen Quang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Masahiro Miki, Jumpei Suzuki, Ziyi Chen, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaru Hitomi, Kenta Sawamura, Masayuki Ohzeki

    SCIENTIFIC REPORTS　15　(1)　2025/12/02

    DOI： 10.1038/s41598-025-28481-w 　

    ISSN： 2045-2322

  3. Exploring Spatial and Temporal Parallelism for Vision Transformer Acceleration.

    Hasitha Muthumala Waidyasooriya, Tomohiro Matsui, Daisuke Tanaka, Masanori Hariyama

    MCSoC　70-75　2025

    DOI： 10.1109/MCSoC67473.2025.00022 　

  4. Fpga-Based Highly Parallel Architecture for Multi-Robot Path Planning.

    Kosei Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    MCSoC　64-69　2025

    DOI： 10.1109/MCSoC67473.2025.00021 　

  5. Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration Peer-reviewed

    Thinh Nguyen Quang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki

    30TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2025　1188-1194　2025/01

    DOI： 10.1145/3658617.3697700 　

    ISSN： 2153-6961

  6. Performance evaluation of Word2vec accelerators exploiting spatial and temporal parallelism on DDR/HBM-based FPGAs

    Waidyasooriya, H.M., Hariyama, M.

    Journal of Supercomputing　80　(12)　17192-17211　2024

    DOI： 10.1007/s11227-024-06120-x 　

    ISSN： 1573-0484 0920-8542

    eISSN： 1573-0484

  7. FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services

    Okada, M., Suzuki, T., Nishio, N., Waidyasooriya, H.M., Hariyama, M.

    IEEE Transactions on Cloud Computing　10　(2)　1373-1385　2022/04/01

    DOI： 10.1109/TCC.2020.2969655 　

    ISSN： 2168-7161

  8. Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU

    Waidyasooriya, H.M., Hariyama, M.

    Journal of Supercomputing　78　(6)　8733-8750　2022/04

    DOI： 10.1007/s11227-021-04242-0 　

    ISSN： 1573-0484 0920-8542

    eISSN： 1573-0484

  9. Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism.

    Hasitha Muthumala Waidyasooriya, Shutaro Ishihara, Masanori Hariyama

    Parallel and Distributed Computing, Applications and Technologies - 23rd International Conference(PDCAT)　69-77　2022

    Publisher: Springer

    DOI： 10.1007/978-3-031-29927-8_6 　

  10. FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model.

    Hasitha Muthumala Waidyasooriya, Yuta Ohma, Masanori Hariyama

    15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC)　195-199　2022

    Publisher: IEEE

    DOI： 10.1109/MCSoC57363.2022.00039 　

  11. Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC plus

    Kosiro Obata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022)　2022

    DOI： 10.1109/MWSCAS54063.2022.9859514 　

  12. OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano

    2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022)　2022

    DOI： 10.1109/MWSCAS54063.2022.9859281 　

  13. A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory

    Waidyasooriya, H.M., Oshiyama, H., Kurebayashi, Y., Hariyama, M., Ohzeki, M.

    IEEE Access　10　1-1　2022

    DOI： 10.1109/ACCESS.2022.3183993 　

    ISSN： 2169-3536

  14. Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators Peer-reviewed

    Liu, C.-Y., Waidyasooriya, H.M., Hariyama, M.

    Journal of Supercomputing　78　(1)　1-17　2022/01

    DOI： 10.1007/s11227-021-03859-5 　

    ISSN： 1573-0484 0920-8542

    eISSN： 1573-0484

  15. Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing

    Waidyasooriya, H.M., Hariyama, M.

    IEEE Transactions on Emerging Topics in Computing　9　(4)　2019-2029　2021/10/01

    DOI： 10.1109/TETC.2019.2957177 　

    ISSN： 2168-6750

  16. A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    IEEE ACCESS　8　67929-67939　2020

    DOI： 10.1109/ACCESS.2020.2985699 　

    ISSN： 2169-3536

  17. Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation

    Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    Proceedings - 2019 7th International Symposium on Computing and Networking, CANDAR 2019　164-170　2019/11/01

    DOI： 10.1109/CANDAR.2019.00028 　

    ISSN： 2379-1888

  18. A memory-bandwidth-efficient word2vec accelerator using OpenCL for FPGA

    Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa

    Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019　103-108　2019/11/01

    DOI： 10.1109/CANDARW.2019.00026 　

  19. OpenCL-based design of an FPGA accelerator for quantum annealing simulation

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki

    JOURNAL OF SUPERCOMPUTING　75　(8)　5019-5039　2019/08

    DOI： 10.1007/s11227-019-02778-w 　

    ISSN： 0920-8542

    eISSN： 1573-0484

  20. Prospects of FPGA-Based Custom Supercomputing,FPGA を用いたカスタムスーパーコンピューティングの展望

    Hariyama, M., Waidyasooriya, H., M

    Kyokai Joho Imeji Zasshi/Journal of the Institute of Image Information and Television Engineers　73　(1)　2019

    DOI： 10.3169/ITEJ.73.40 　

    ISSN： 1342-6907

  21. FPGA-based acceleration of word2vec using OpenCL

    Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa

    Proceedings - IEEE International Symposium on Circuits and Systems　2019-　2019

    DOI： 10.1109/ISCAS.2019.8702700 　

    ISSN： 0271-4310

  22. Benchmarks for FPGA-Targeted High-Level-Synthesis

    Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama

    2019 SEVENTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR 2019)　232-238　2019

    DOI： 10.1109/CANDAR.2019.00038 　

    ISSN： 2379-1888

  23. Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    IEEE ACCESS　7　53188-53201　2019

    DOI： 10.1109/ACCESS.2019.2910824 　

    ISSN： 2169-3536

  24. Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL

    Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama

    ISPACS 2018 - 2018 International Symposium on Intelligent Signal Processing and Communication Systems　335-340　2018/11/01

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/ISPACS.2018.8923263 　

  25. Automatic optimization of OpenCL-based stencil codes for FPGAs Peer-reviewed

    Tsukasa Endo, Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    Studies in Computational Intelligence　721　75-89　2018

    Publisher: Springer Verlag

    DOI： 10.1007/978-3-319-62048-0_6 　

    ISSN： 1860-949X

  26. Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems Peer-reviewed

    Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)　10776　146-155　2018

    DOI： 10.1007/978-3-319-69953-0_9 　

    ISSN： 1611-3349 0302-9743

    eISSN： 1611-3349

  27. Architecture of an FPGA accelerator for LDA-based inference Peer-reviewed

    Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki

    Proceedings - 18th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, SNPD 2017　357-362　2017/08/29

    DOI： 10.1109/SNPD.2017.8022746 　

  28. OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama

    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS　28　(5)　1390-1402　2017/05

    DOI： 10.1109/TPDS.2016.2614981 　

    ISSN： 1045-9219

    eISSN： 1558-2183

  29. An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara

    INTERNATIONAL JOURNAL OF NETWORKED AND DISTRIBUTED COMPUTING　5　(1)　52-61　2017/01

    DOI： 10.2991/ijndc.2017.5.1.6 　

    ISSN： 2211-7938

    eISSN： 2211-7946

  30. OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera

    International Journal of Reconfigurable Computing　2017　Article ID 6817674　2017

    Publisher: Hindawi Limited

    DOI： 10.1155/2017/6817674 　

    ISSN： 1687-7209 1687-7195

  31. OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera

    INTERNATIONAL JOURNAL OF RECONFIGURABLE COMPUTING　2017　6817674:1-6817674:11　2017

    DOI： 10.1155/2017/6817674 　

    ISSN： 1687-7195

    eISSN： 1687-7209

  32. An FPGA accelerator for molecular dynamics simulation using OpenCL Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara

    International Journal of Networked and Distributed Computing　5　(1)　52-61　2017/01/01

    Publisher: Atlantis Press

    DOI： 10.2991/ijndc.2017.5.1.6 　

    ISSN： 2211-7946 2211-7938

  33. FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    2016 IEEE/ACIS 15th International Conference on Computer and Information Science, ICIS 2016 - Proceedings　109-114　2016/08/23

    Publisher: Institute of Electrical and Electronics Engineers Inc.

    DOI： 10.1109/ICIS.2016.7550742 　

  34. FPGA architecture for 3-D FDTD acceleration using open CL Peer-reviewed

    H. M. Waidyasooriya, M. Hariyama, Y. Ohtera

    Progress in Electromagnetic Research Symposium (PIERS)　4719-4719　2016/08/11

    DOI： 10.1109/PIERS.2016.7735734 　

  35. Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    IEEE Transactions on Parallel and Distributed Systems　27　(5)　1358-1372　2016/05/01

    Publisher: Institute of Electrical {\&} Electronics Engineers ({IEEE})

    DOI： 10.1109/TPDS.2015.2444376 　

    ISSN： 1045-9219

  36. Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama

    IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS　27　(5)　1358-1372　2016/05

    DOI： 10.1109/TPDS.2015.2444376 　

    ISSN： 1045-9219

    eISSN： 1558-2183

  37. Hardware-oriented succinct-data-structure for text processing based on block-size-constrained compression Peer-reviewed

    Waidyasooriya, H.M., Ono, D., Hariyama, M.

    International Journal of Computer Information Systems and Industrial Management Applications　8　(11)　1-11　2016/01/01

    ISSN： 2150-7988

  38. Architecture of an FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL Peer-reviewed

    Hasitha Muthumala, Waidyasooriya, Masanori Hariyama, Kota Kasahara

    2016 IEEE/ACIS 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS)　115-119　2016

    DOI： 10.1109/ICIS.2016.7550743 　

  39. Architecture of an FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL Peer-reviewed

    Hasitha Muthumala, Waidyasooriya, Masanori Hariyama, Kota Kasahara

    2016 IEEE/ACIS 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS)　115-119　2016

    DOI： 10.1109/ICIS.2016.7550743 　

  40. FPGA-Based Deep-Pipelined Architecture for FDTD Acceleration Using OpenCL Peer-reviewed

    Hasitha Muthumala, Waidyasooriya, Masanori Hariyama

    2016 IEEE/ACIS 15TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION SCIENCE (ICIS)　108-113　2016

    DOI： 10.1109/ICIS.2016.7550742 　

  41. Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators Peer-reviewed

    Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E98A　(12)　2658-2669　2015/12

    DOI： 10.1587/transfun.E98.A.2658 　

    ISSN： 0916-8508

    eISSN： 1745-1337

  42. Hardware-Oriented Succinct-Data-Structure based on Block-Size-Constrained Compression Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama

    PROCEEDINGS OF THE 2015 SEVENTH INTERNATIONAL CONFERENCE OF SOFT COMPUTING AND PATTERN RECOGNITION (SOCPAR 2015)　136-140　2015

    DOI： 10.1109/SOCPAR.2015.7492797 　

    ISSN： 2381-7542

  43. Hardware-Oriented Succinct-Data-Structure based on Block-Size-Constrained Compression Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama

    PROCEEDINGS OF THE 2015 SEVENTH INTERNATIONAL CONFERENCE OF SOFT COMPUTING AND PATTERN RECOGNITION (SOCPAR 2015)　136-140　2015

    DOI： 10.1109/SOCPAR.2015.7492797 　

    ISSN： 2381-7542

  44. Efficient Data Transfer Scheme Using Word-Pair-Encoding-Based Compression for Large-Scale Text-Data Processing Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama

    2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)　639-642　2014

    DOI： 10.1109/APCCAS.2014.7032862 　

  45. FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama,Array,Array

    J. Computational Engineering　2014　634269:1-634269:8　2014

  46. Implementation of a Custom Hardware-Accelerator for Short-read Mapping Using Burrows-Wheeler Alignment Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    2013 35TH ANNUAL INTERNATIONAL CONFERENCE OF THE IEEE ENGINEERING IN MEDICINE AND BIOLOGY SOCIETY (EMBC)　651-654　2013

    DOI： 10.1109/EMBC.2013.6609584 　

    ISSN： 1557-170X

  47. Evaluation of an FPGA-Based heterogeneous multicore platform with SIMD/MIMD custom accelerators Peer-reviewed

    Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences　E96-A　(12)　2576-2586　2013

    Publisher: Institute of Electronics, Information and Communication, Engineers, IEICE

    DOI： 10.1587/transfun.E96.A.2576 　

    ISSN： 1745-1337 0916-8508

  48. Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation Peer-reviewed

    Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Toru Nojiri, Kunio Uchiyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON ELECTRONICS　E95C　(12)　1872-1882　2012/12

    DOI： 10.1587/transele.E95.C.1872 　

    ISSN： 0916-8524

    eISSN： 1745-1353

  49. Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E95D　(2)　354-363　2012/02

    DOI： 10.1587/transinf.E95.D.354 　

    ISSN： 1745-1361

  50. Platform and Mapping Methodology for Heterogeneous Multicore Processors Peer-reviewed

    Masanori HARIYAMA, Hasitha Muthumala WAIDYASOORIYA, Yasuhiro TAKEI, Michitaka Kameyama

    Interdisciplinary Information Sciences　18　(2)　175-184　2012

    Publisher: The Editorial Committee of the Interdisciplinary Information Sciences

    DOI： 10.4036/iis.2012.175 　

    ISSN： 1340-9050

    More details Close

    Heterogeneous multi-core processors are attracted by various type of applications from low-power media applications to high-performance computing due to their capability of drawing strengths of different cores to improve the overall performance. However, the data transfer bottlenecks between different cores becomes a serious problem. This paper presents two key methodologies to solve the data transfer bottoleneck: memory allocation considering a addressing function constraint and task allocation based on algorithm transformation. Moreover, in order to help to explore accelerator architecture suitable for applications, this paper presents a platform based on FPGAs where circuity is reconfigured by users after fabrication.

  51. FPGA Implementation of Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama

    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)　1339-1342　2012

    DOI： 10.1109/ISCAS.2012.6271489 　

    ISSN： 0271-4302

  52. Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama

    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY　21　(10)　1453-1466　2011/10

    DOI： 10.1109/TCSVT.2011.2162277 　

    ISSN： 1051-8215

    eISSN： 1558-2205

  53. Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E94A　(1)　342-351　2011/01

    DOI： 10.1587/transfun.E94.A.342 　

    ISSN： 0916-8508

    eISSN： 1745-1337

  54. Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E93A　(12)　2570-2580　2010/12

    DOI： 10.1587/transfun.E93.A.2570 　

    ISSN： 0916-8508

    eISSN： 1745-1337

  55. Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama

    Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA　281-284　2010

    Publisher: CSREA Press

  56. Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA　179-186　2010

    Publisher: CSREA Press

  57. Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON ELECTRONICS　E92C　(4)　539-549　2009/04

    DOI： 10.1587/transele.E92.C.539 　

    ISSN： 1745-1353

    eISSN： 1745-1353

  58. Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, July 13-16, 2009, Las Vegas Nevada, USA　291-294　2009

    Publisher: CSREA Press

  59. Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E91A　(12)　3596-3606　2008/12

    DOI： 10.1093/ietfec/e91-a.12.3596 　

    ISSN： 0916-8508

    eISSN： 1745-1337

  60. Multi-context FPGA using fine-grained interconnection blocks and its CAD environment Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama

    IEICE TRANSACTIONS ON ELECTRONICS　E91C　(4)　517-525　2008/04

    DOI： 10.1093/ietele/e91-c.4.517 　

    ISSN： 1745-1353

    eISSN： 1745-1353

  61. Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2008, Las Vegas, Nevada, USA, July 14-17, 2008　201-207　2008

    Publisher: CSREA Press

  62. Design of a multi-context FPVLSI based on an asynchronous bit-serial architecture Peer-reviewed

    Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama

    2007 IEEE Dallas/CAS Workshop on System-on-Chip (SoC): Design, Applications, Integration, and Software, DCAS-07　59-62　2007

    DOI： 10.1109/DCAS.2007.4433216 　

  63. Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment Peer-reviewed

    Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Michitaka Kameyama

    2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006　155-158　2006

    DOI： 10.1109/ASSCC.2006.357874 　

  64. GA-based assignment of supply and threshold voltages and interconnection simplification for low power VLSI design Peer-reviewed

    Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama

    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS　1264-+　2006

Show all ︎Show first 5

Misc. 25

  1. Design and Parallel Performance Evaluation of a Multi-FPGA SQA Accelerator for Route Optimization in Large-Scale AGV Systems

    NGUYEN QUANG Thinh, NGUYEN QUANG Thinh, 松山公丞, 清水啓介, 菅野裕己, 栗本英治, WAIDYASOORIYA Hasitha Muthumala, 西尾昂世, 張山昌論, 人見将, 澤村建太, 大関真之

    電子情報通信学会技術研究報告(Web)　125　(184(RECONF2025 50-67))　2025

    ISSN： 2432-6380

  2. Studies for Quantum-Classic Hybrid Systems Employing Logics and Algorithms in Digital Communications

    越川翔太, 保坂有杜, 西川翔太, 小西良明, 篠崎基矢, 大塚朋廣, WAIDYASOORIYA Hasitha Muthumala, 張山昌論, 吉田剛

    電子情報通信学会技術研究報告(Web)　123　(329(CS2023 93-103))　2024

    ISSN： 2432-6380

  3. Design of FPGA-based computing systems with openCL

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kunio Uchiyama

    Design of FPGA-Based Computing Systems with OpenCL　1-126　2017/10/24

    Publisher: Springer International Publishing

    DOI： 10.1007/978-3-319-68161-0 　

  4. 離散最適化問題のためのFPGAベースk-out-of-n生成器の構成

    平舘侑樹, WAIDYASOORIYA Hasitha Muthumala, 張山昌論

    信号処理シンポジウム講演論文集(CD-ROM)　32nd　2017

  5. LDAベース推論のためのFPGAアクセラレータ設計

    小野泰輔, WAIDYASOORIYA Hasitha Muthumala, 張山昌論, 石垣司

    信号処理シンポジウム講演論文集(CD-ROM)　32nd　2017

  6. OpenCLを用いたステンシル計算用FPGAアクセラレータの最適設計

    遠藤司, WAIDYASOORIYA Hasitha Muthumala, 張山昌論

    信号処理シンポジウム講演論文集(CD-ROM)　32nd　2017

  7. OpenCLを用いたステンシル計算向けFPGAプラットフォーム

    WAIDYASOORIYA Hasitha Muthumala, 立見駿介, 張山昌論

    情報処理学会研究報告(Web)　2016　(HPC-154)　2016

  8. Design of an FPGA-based Accelerator for Moleculer Dynamics Using OpenCL

    WAIDYASOORIYA Hasitha Muthumala, 張山昌論, 笠原浩太

    電子情報通信学会技術研究報告　116　(53(RECONF2016 1-23))　2016

    ISSN： 0913-5685

  9. Design of an FPGA Platform for Stencil Computation Using OpenCL

    WAIDYASOORIYA Hasitha Muthumala, 張山昌論

    電子情報通信学会技術研究報告　116　(53(RECONF2016 1-23))　2016

    ISSN： 0913-5685

  10. OpenCLを用いたFDTD計算用FPGAプラットフォームの開発

    WAIDYASOORIYA Hasitha Muthumala, 張山昌論, 大寺康夫

    電子情報通信学会大会講演論文集(CD-ROM)　2016　2016

    ISSN： 1349-144X

  11. An FPGA Architecture for Text Search Using a Wavelet-Tree-Based Succinct-Data-Structure Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama

    International Conference on Parallel and Distributed Processing Techniques and Applications　354-359　2015

  12. FPGA-Oriented Design of an FDTD Accelerator Based on Overlapped Tiling

    Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    International Conference on Parallel and Distributed Processing Techniques and Applications　72-77　2015

  13. Highly-Parallel FPGA Accelerator for DNA Sequence Alignment Using the Burrows-Wheeler Algorithm

    WAIDYASOORIYA Hasitha Muthumala, HARIYAMA Masanori, KAMEYAMA Michitaka

    IEICE technical report　114　(75)　17-20　2014/06/11

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    The mapping of millions of short DNA fragments to a large genome is a very important aspect of the modern bioinformatics. However, software-based DNA sequence mapping takes many days to complete. This paper proposes an FPGA-based hardware accelerator to increase the mapping speed. Proposed accelerator maps over hundred short DNA fragments simultaneously. We apply a data encoding scheme that reduces the genome data size to just 4%, and propose a hardware decoder to decode the data in single clock cycle. We also design customized data paths to increase the speed for random data access. According to the experimental results, the speed-up of the proposed architecture is 15 times compared to its equivalent software application.

  14. FPGA-Accelerator for DNA Sequence Alignment Based on an Efficient Data-Dependent Memory Access Scheme Peer-reviewed

    Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    Proceedings of the 5th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies　127-130　2014

  15. Design of an FPGA-Based FDTD Accelerator Using Open CL

    Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    International Conference on Parallel and Distributed Processing Techniques and Applications　371-375　2014

  16. Heterogeneous Multicore Platform with Accelerator Templates and Its Implementation on an FPGA with Hard-core CPUs

    Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms　47-50　2013

  17. Reducing Floating-Point Error Based on Residue-Preservation and Its Evaluation on an FPGA

    Hasitha Muthumala Waidyasooriya, Hirokazu Takahashi, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama

    Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms　55-58　2013

  18. Platform and Mapping Methodology for Heterogeneous Multicore Processors

    HARIYAMA Masanori, WAIDYASOORIYA Hasitha Muthumala, TAKEI Yasuhiro, KAMEYAMA Michitaka

    Interdisciplinary Information Sciences　18　(2)　175-184　2012/12/10

    Publisher: Graduate School of Information Sciences, Tohoku University

    ISSN： 1347-6157

  19. Low-Power Heterogeneous Platform for High Performance Computing and Its Application to 2D-FDTD Computation

    Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama

    Proceedings of International Conference on Engineering of Reconfigurable Systems and Algorithms　147-150　2012

  20. Hybrid Single/Double Precision Floating-Point Computation on GPU Accelerators for 2-D FDTD

    Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama

    International Conference on Parallel and Distributed Processing Techniques and Applications　CD ROM　2012

  21. FPGA Platform for Heterogeneous Multicore Processors with MIMD-ALU-array-type Dynamically Reconfigurable Accelerators

    TAKEI Yasuhiro, WAIDYASOORIYA Hasitha Muthumala, HARIYAMA Masanori, KAMEYAMA Michitaka

    Technical report of IEICE. ICD　111　(258)　73-76　2011/10/17

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    Heterogeneous multi-core architectures with CPUs and accelerators attract many attentions since they can achieve energy-efficient computing for various areas such as media processing and high-performance computing. It is important to explore the suitable architecture for each application since the suitable architectures are different from application to application. This paper reports an FPGA implementation of a heterogeneous multicore architecture with a MIMD-2D-type accelerator where independently-controlled ALUs are aligned in a 2-dimensional array.

  22. Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor

    HIRAMATSU Yoshitaka, WAIDYASOORIYA Hasitha Muthumala, HARIYAMA Masanori, NOJIRI Tohru, UCHIYAMA Kunio

    IEICE technical report　110　(380)　57-62　2011/01/13

    Publisher: The Institute of Electronics, Information and Communication Engineers

    ISSN： 0913-5685

    More details Close

    The large data-transfer time among different cores and data-supply time to arithmetic unit is a big problem in heterogeneous multi-core processors. To reduce the data-supply time, an efficient method based on complex memory allocation was proposed. However, the data-transfer-modules cannot be used to accelerate the data transfer since the method does not use linear or stride data transfers. This paper presents a method by alignment in the data transfer and arithmetic processing respectively so that we can accelerate the data transfers exploiting data-transfer-units together with complex memory allocation. We use block matching to evaluate our technique. The proposed method reduces the data-transfer time by 42% compared to the method that use only complex memory allocation.

  23. Data-Transfer-Aware Memory Allocation for Dynamically Reconfigurable Accelerators in Heterogeneous Multicore Processors

    Yosuke Ohbayashi, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama

    Proc. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)　282-288　2011

  24. FPGA向きヘテロジニアスマルチコアプロセッサ--SIMD形アクセラレータコアとその評価—FPGA-oriented heterogeneous multi-core processor: SIMD-accelerator core its evaluation—集積回路

    張山 昌論, Hasitha Muthumala Waidyasooriya, 松田 岳久

    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報　109　(405)　105-108　2010/01

    Publisher: 東京 : 電子情報通信学会

    ISSN： 0913-5685

  25. C-033 Optimal Memory Allocation for Heterogeneous Multicore Architecture for Multimedia Applications

    Matsuda Takehisa, Waidyasooriya Hasitha Muthumala, Hariyama Masanori, Kameyama Michitaka

    8　(1)　511-512　2009/08/20

    Publisher: Forum on Information Technology

Show all ︎Show first 5

Industrial Property Rights 3

  1. 符号化装置、符号化方法及びプログラム

    小林 大祐, 大森 優也, 中村 健, 岩崎 裕江, 張山 昌論, ウィッデヤスーリヤ ハシタ ムトゥマラ

    特許第7406208号

    Property Type: Patent

  2. 入出力制御方法、入出力制御プログラム、及び入出力制御装置

    小林 大祐, 大森 優也, 中村 健, ウィッデヤスーリヤ ハシタ ムトゥマラ, 張山 昌論, 岩崎 裕江

    Property Type: Patent

  3. 符号化装置、符号化方法及びプログラム

    小林 大祐, 大森 優也, 中村 健, 岩崎 裕江, 張山 昌論, ウィッデヤスーリヤ ハシタ ムトゥマラ

    Property Type: Patent

Research Projects 6

  1. High-efficiency Heterogeneous Custom Accelerator Foundation for Transformer

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research

    Category: Grant-in-Aid for Scientific Research (B)

    Institution: Tohoku University

    2024/04/01 - 2028/03/31

  2. Custom Accelerators for Quantum-Annealing-Assisted Material Informatics

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research

    Category: Grant-in-Aid for Scientific Research (B)

    Institution: Tohoku University

    2020/04/01 - 2024/03/31

  3. High Speed FPGA Simulator for Large Scale Quantum Annealing Simulations

    Waidyasooriya Hasitha

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research

    Category: Grant-in-Aid for Scientific Research (C)

    Institution: Tohoku University

    2019/04/01 - 2023/03/31

    More details Close

    (1) Large scale quantum annealing simulation: The connections among spins (coefficients) increases exponentially with the number of spins. This increases the required memory capacity and prevents large-scale simulation. This research proposes a method to generate the coefficients efficiently, without storing the pre-generated coefficients in the memory. As a result, large memory requirement has been eliminated, and we were able to run simulations with over 200,000 spins using a single FPGA. (2) Acceleration: Quantum Monte-Carlo method used for the simulations is very difficult to parallelize. We proposed a method to execute the computations among multiple Trotter slices in parallel while maintaining the data dependancy. As a result, we achieved over 290 times speed-up compared to CPU serial implementation. (3) High accuracy: Since we protect the data dependency in parallel computation, the accuracy is very high. Compared to D-Wave using MQLib benchmark suit, the accuracy is over 99%.

  4. Developing a Smart Storage based on a Succinct Data Structure that Processes Compressed Data

    Waidyasooriya Hasitha

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research

    Category: Grant-in-Aid for Young Scientists (B)

    Institution: Tohoku University

    2015/04/01 - 2017/03/31

    More details Close

    Big-data are used in many text processing applications. As a result, data access often becomes a bottleneck. This research is focused on data access reduction using a succinct data structure and its processor architecture. The data amount is reduced to 27% using wavelet tree based succinct data structure. In addition, memory access is reduced to 73%. A smart storage and its processor architecture is designed based on the proposed succinct data structure to reduce the data access. Using this storage, accelerators are designed for genome data alignment and text data search processes. The designed system that contains accelerators and storage is implemented using an FPGA. A speed-up of over 21 times is achieved compared to the conventional CPU-based implementation.

  5. Development of Heterogeneous-Computing Platform with Custom Accelerators for Embedded HPC Applications

    Hariyama Masanori, Waidyasooriya Hasitha Muthumala

    Offer Organization: Japan Society for the Promotion of Science

    System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

    Category: Grant-in-Aid for Scientific Research (B)

    Institution: Tohoku University

    2012/04/01 - 2016/03/31

    More details Close

    This research is aiming at design technologies for a heterogeneous computing platform consisting of CPU cores, GPUs, and FPGAs. FPGAs allows us to build the application-specific accelerators since it's datapath can be reconfigured by programming after fabrication. One major difficulty in designing the heterogeneous computing platform is to find task allocation maximizing the performance and to design the FPGA datapath as easily as possible. In order to solve this problem, we develop high-level synthesis technologies for the heterogeneous computing platform.

  6. カスタムアクセラレータを有する高性能計算ヘテロジニアスプラットフォーム

    亀山 充隆, HASITHAMUTHUMALA Waidyasooriya

    Offer Organization: 日本学術振興会

    System: 科学研究費助成事業 特別研究員奨励費

    Category: 特別研究員奨励費

    Institution: 東北大学

    2011 - 2013

    More details Close

    本研究プロジェクトでは, 高性能・低消費電力な高性能演算"Green HPC (High Performance Computing)"の実現のため, CPU, GPU(グラフィック処理ユニット)そして"FPGAカスタムアクセラレータ"からなるヘテロジニアスな構成を想定し, それにユーザープログラムを自動マッピングするソフトウェア群の開発を目的である. 本年度では, 構築したGreen HPCプラットフォームの性能を以下の具体的なアプリケーションにより評価した. 雷磁界解析におけるFDTD (Finite-Difference Time-Domain)シミュレーション FDTDシミュレーションでは倍精度浮動小数点演算を使わなければならない場合が多く, 1つのデータを64ビットを使い表すためデータ量が大きくなりデータ転送はボトルネックになる. 本研究では, 高い演算精度が必要な電磁界の変動が激しい領域と低い演算精度でも十分な変動が少ない領域に分解した. それぞれの領域を順番に倍精度浮動小数点と32ビット固定小数点に分けて計算できる手法を提案した. 提案の浮動小数点・固定小数点ハイブリッド演算手法をFPGAで実装した結果GPUと同等な性能をその10%以下の消費電力で達成可能であることを発表した. ビッグデータを扱うDNA塩基配列位置推定処理 ゲノムを構成するDNA分子の塩基配列はA, T, C, Gの4種類の要素で構成されている. 塩基配列の要素が30億以上の膨大な数であり, そのデータアクセスがボトルネックになるため, 通常のCPUを接続したPCクラスターベースのスーパーコンピュータでの処理時間が数日～1週間程度かかる. 本研究では, ホスト側でデータを圧縮して転送を行い, FPGAの中でハードウェアによりワンステップで伸張できるような圧縮手法を提案した. 圧縮データアクセスとFPGA上にカスタムデータパスを設計することにより, CPUのランダムアクセス速度の20倍から50倍程度のメモリアクセス速度を達成した.

Show all Show first 5