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Takahiro Hanyu

Section

Research Institute of Electrical Communication

Job title

Professor

Degree

工学博士（東北大学）

researchmap

https://researchmap.jp/read0168375

J-GLOBAL ID

200901015971474624

Professional Memberships 4

The Japan Society of Applied Physics

2009/03 - Present
Information Processing Society of Japan

1986/08 - Present
The Institute of Electronics, Information and Communication Engineers

1984/08 - Present
米国電気電子工学会(The Institute of Electrical and Electronics Engineers)

Research Interests 3

Device-model-based electronics
New Paradigm VLSI
Nonvolatile Logic-in-Memory Architecture

Research Areas 3

Informatics / Computational science / die-hard computing
Informatics / Soft computing / non-volatile logic
Informatics / Computer systems / Intelligent Integrated Systrems

Awards 17

Next-Generation Division Award

2024/10　CEATEC AWARD2024　Design Technique for CMOS/spintronics-hybrid AI semiconductor
Outstanding Contributed Paper Award

2024/05　IEEE Computer Society Technical Committee of MVL(Multiple-Valued Logic)　Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware
Excellent Young Researcher Presentation Award

2018/05　Technical Committee on Integrated Circuits and Devices (ICD), IEICE
The Commendation for Science and Technology

2015/04　MEXT　"Study of Nonvolatile Logic-in-Memory Integrated Circuits"
Best Paper Award Finalist

2014/05　IEEE ASYNC 2014　"A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure"
Paper Award

2012/09　SSDM 2012　"High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction"
Best Paper Award

2010/07　IEEE ISVLSI 2010　"Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model"
Excellent Paper Award

2010/05　The Institute of Electronics, Information and Communication Engineers　"Design of a Lookup Table Circuit Based on TMR Logic and Its Application to an Immediate Wake-Upable FPGA"
Ichimura Academic Award

2010/04　"Development of Nonvolatile Logic-in-Memory Integrated Circuits"
Excellent Paper Award (JJAP Paper Award)

2009/09　The Japan Society of Applied Physics　"Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices"
University LSI Design Contest Special Feature Award

2007/01　ASP-DAC 2007　"Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic"
優秀ポスター賞

2002/11　2002年システムLSIワークショップ　"Design of Low-Power Logic-in-Memory VLSI Using Ferroelectric Devices"
審査員特別賞

2002/06　2002年度(第９回)ＬＳＩデザイン・オブ・ザ・イヤー　強誘電体デバイスを用いたシステムLSI構築技術
坂井記念特別賞

2000/05　（社）情報処理学会　"Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate MOS Pass-Transistor Logic"
Distinctive Contribution Award

1988/05　IEEE ISMVL　"Quaternary Gate Array for Pattern Matching and its Application to Knowledge Information Processing System"
丹羽記念賞

1988/02　丹羽記念会　"Design and Implementation of an nMOS Image Processor Based on Quaternary Logic"
Award for Excellence

1986/05　IEEE ISMVL　"Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing"

Show all ︎Show 5

Papers 542

Design of an FPGA-based emulator for rapidly prototyping a nonvolatile system-on-a-chip Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

Japanese Journal of Applied Physics　64　(4)　04SP06-04SP06　2025/04/01
Publisher: IOP Publishing
DOI： 10.35848/1347-4065/adba6d 　

ISSN： 0021-4922

eISSN： 1347-4065

More details Close

Abstract This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.
Design of an Intermittent-Computing-Oriented Nonvolatile Register With a Switching-Probability-Aware Store-and-Verify Scheme Peer-reviewed

Masanori Natsui, Takahiro Hanyu

IEEE Access　13　38104-38114　2025/03/07
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/access.2025.3546590 　

eISSN： 2169-3536
GPU-accelerated simulated annealing based on p-bits with real-world device-variability modeling

Naoya Onizawa, Takahiro Hanyu

Scientific Reports　15　(1)　2025/02/19
Publisher: Springer Science and Business Media LLC
DOI： 10.1038/s41598-025-90520-3 　

eISSN： 2045-2322
Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware Peer-reviewed

Ken ASANO, Masanori NATSUI, Takahiro HANYU

IEICE Transactions on Information and Systems　E107.D　(8)　958-965　2024/08/01
Publisher: Institute of Electronics, Information and Communications Engineers (IEICE)
DOI： 10.1587/transinf.2023lop0007 　

ISSN： 0916-8532

eISSN： 1745-1361
Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems

Naoya Onizawa, Takahiro Hanyu

Scientific Reports　14　(1)　2024/01/16
Publisher: Springer Science and Business Media LLC
DOI： 10.1038/s41598-024-51639-x 　

eISSN： 2045-2322

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Abstract This article critically investigates the limitations of the simulated annealing algorithm using probabilistic bits (pSA) in solving large-scale combinatorial optimization problems. The study begins with an in-depth analysis of the pSA process, focusing on the issues resulting from unexpected oscillations among p-bits. These oscillations hinder the energy reduction of the Ising model and thus obstruct the successful execution of pSA in complex tasks. Through detailed simulations, we unravel the root cause of this energy stagnation, identifying the feedback mechanism inherent to the pSA operation as the primary contributor to these disruptive oscillations. To address this challenge, we propose two novel algorithms, time average pSA (TApSA) and stalled pSA (SpSA). These algorithms are designed based on partial deactivation of p-bits and are thoroughly tested using Python simulations on maximum cut benchmarks that are typical combinatorial optimization problems. On the 16 benchmarks from 800 to 5000 nodes, the proposed methods improve the normalized cut value from 0.8 to 98.4% on average in comparison with the conventional pSA.
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems

Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

IEEE Access　12　102050-102060　2024
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/access.2024.3431540 　

eISSN： 2169-3536
Stochastic Implementation of Simulated Quantum Annealing on PYNQ

Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2023 International Conference on Field Programmable Technology (ICFPT)　2023/12/12
Publisher: IEEE
DOI： 10.1109/icfpt59805.2023.00042 　
Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network

Ken Asano, Masanori Natsui, Takahiro Hanyu

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)　2023/12/04
Publisher: IEEE
DOI： 10.1109/icecs58634.2023.10382768 　
Improving Stochastic Quantum-Like Annealing Based on Rerandomization

Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)　2023/12/04
Publisher: IEEE
DOI： 10.1109/icecs58634.2023.10382735 　
Challenge of Energy-Efficient Edge-AI Accelerator Architecture Using Nonvolatile Logic Peer-reviewed

Natsui Masanori, Takako Yasuhiro, Tamakoshi Akira, Hanyu Takahiro

2023 International Symposium on Nonlinear Theory and Its Applications (NOLTA2023)　263-264　2023/09

DOI： 10.34385/proc.76.B2L-36 　
Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing

Kaede Sakai, Masanori Natsui, Takahiro Hanyu

2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)　2023/08/06
Publisher: IEEE
DOI： 10.1109/mwscas57524.2023.10405935 　
Design of a nonvolatile-register-embedded RISC-V CPU with software-controlled data-retention and hardware-acceleration functions

Masanori Natsui, Keisuke Sakamoto, Takahiro Hanyu

Memories - Materials, Devices, Circuits and Systems　4　100035-100035　2023/07
Publisher: Elsevier BV
DOI： 10.1016/j.memori.2023.100035 　

ISSN： 2773-0646
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing

Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu

IEEE Open Journal of Signal Processing　1-11　2023
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/ojsp.2023.3329756 　

eISSN： 2644-1322
Self-Adaptive Gate Control for Efficient Escape from Local Minimum Energy on Invertible Logic

Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access　11　1-1　2023
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/access.2023.3272867 　

eISSN： 2169-3536
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE Journal on Emerging and Selected Topics in Circuits and Systems　13　(1)　1-1　2023
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/jetcas.2023.3243260 　

ISSN： 2156-3357

eISSN： 2156-3365
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing

Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)　2022/10/24
Publisher: IEEE
DOI： 10.1109/icecs202256217.2022.9971124 　
Dynamic activation of power-gating-switch configuration for highly reliable nonvolatile large-scale integrated circuits

Fangcen Zhong, Masanori Natsui, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　61　(SC)　2022/05

DOI： 10.35848/1347-4065/ac461a 　

ISSN： 0021-4922

eISSN： 1347-4065
CMOS Invertible Logic: Bidirectional operation based on the probabilistic device model and stochastic computing

Naoya Onizawa, Takahiro Hanyu

IEEE Nanotechnology Magazine　16　(1)　33-46　2022/02
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/mnano.2021.3126094 　

ISSN： 1932-4510

eISSN： 1942-7808
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing

Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

IEEE Transactions on Neural Networks and Learning Systems　1-7　2022
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tnnls.2022.3159713 　

ISSN： 2162-237X

eISSN： 2162-2388
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

2021 IEEE Workshop on Signal Processing Systems (SiPS)　2021/10
Publisher: IEEE
DOI： 10.1109/sips52927.2021.00047 　
Design automation of invertible logic circuit from a standard hdl description

Makoto Kato, Naoya Onizawa, Takahiro Hanyu

Journal of Applied Logics　8　(5)　1311-1333　2021/06/01
Publisher: College Publications
ISSN： 2631-9829 2631-9810
Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu

Japanese Journal of Applied Physics　60　2021/05/01
Publisher: IOP Publishing Ltd
DOI： 10.35848/1347-4065/abe682 　

ISSN： 1347-4065 0021-4922
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians

Naoya Onizawa, Takahiro Hanyu

2021 IEEE International Symposium on Circuits and Systems (ISCAS)　2021/05
Publisher: IEEE
DOI： 10.1109/iscas51556.2021.9401278 　
Design of a highly reliable nonvolatile flip-flop incorporating a common-mode write error detection capability

Masanori Natsui, Gensei Yamagishi, Takahiro Hanyu

Japanese Journal of Applied Physics　60　(SB)　SBBB02-SBBB02　2021/05/01
Publisher: IOP Publishing
DOI： 10.35848/1347-4065/abdcb0 　

ISSN： 0021-4922

eISSN： 1347-4065
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under Field-Assistance-Free Condition

Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

IEEE Journal of Solid-State Circuits　56　(4)　1116-1128　2021/04

DOI： 10.1109/JSSC.2020.3039800 　

ISSN： 0018-9200

eISSN： 1558-173X
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

IEEE Open Journal of Circuits and Systems　2　782-791　2021
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/ojcas.2021.3116584 　

eISSN： 2644-1225
Sparse Random Signals for Fast Convergence on Invertible Logic

Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access　9　62890-62898　2021
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/access.2021.3072048 　

eISSN： 2169-3536
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu

IEEE Transactions on Circuits and Systems I: Regular Papers　68　(1)　67-76　2021/01
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tcsi.2020.3030104 　

ISSN： 1549-8328

eISSN： 1558-0806
Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA

Daisuke Suzuki, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　2020-　194-199　2020/11/01
Publisher: IEEE Computer Society
DOI： 10.1109/ISMVL49045.2020.000-6 　

ISSN： 0195-623X
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)

Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems　28　(11)　2370-2382　2020/11
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tvlsi.2020.3011522 　

ISSN： 1063-8210

eISSN： 1557-9999
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter

Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems　28　(10)　2171-2181　2020/10
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tvlsi.2020.3005413 　

ISSN： 1063-8210

eISSN： 1557-9999
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage Peer-reviewed

M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, Y. Ma, H. Shen, S. Fukami, H. Sato, S. Ikeda, H. Ohno, T. Endoh, T. Hanyu

VLSI Symposium　2020-June　2020/06

DOI： 10.1109/VLSICircuits18222.2020.9162774 　
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices Peer-reviewed

A. Tamakoshi, N. Onizawa, H. Yamagata, H. Fujita, T. Hanyu

Proc. 18th IEEE International New Circuits and Systems Conference (NEWCAS)　2020/06
Impact of MTJ-based nonvolatile circuit techniques for energy-efficient binary neural network hardware Peer-reviewed

Masanori Natsui, Tomoki Chiba, Takahiro Hanyu

Japanese Journal of Applied Physics　59　(5)　050602-050602　2020/05/01
Publisher: IOP Publishing
DOI： 10.35848/1347-4065/ab82ae 　

ISSN： 0021-4922

eISSN： 1347-4065
Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Daisuke Suzuki, Takahiro Hanyu

Japanese Journal of Applied Physics　59　2020/04/01
Publisher: Institute of Physics Publishing
DOI： 10.35848/1347-4065/ab70ac 　

ISSN： 1347-4065 0021-4922
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE Access　8　188004-188014　2020
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/access.2020.3029576 　

eISSN： 2169-3536
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning International-journal International-coauthorship Peer-reviewed

N. Onizawa, S. C. Smithson, B. H. Meyer, W. J. Gross, T. Hanyu

IEEE Trans. on Circuits and Syst. I Reg. Papers　67　(5)　1541-1550　2020
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/TCSI.2019.2960383 　

ISSN： 1549-8328

eISSN： 1558-0806
Design of an MTJ-based Nonvolatile Multi-context Ternary Content-Addressable Memory Peer-reviewed

N. Onizawa, R. Arakawa, T. Hanyu

Journal of Applied Logics　7　(1)　89-105　2020/01
Fast Hardware-based Learning Algorithm for Binarized Perceptron Using CMOS Invertible Logic Peer-reviewed

N. Onizawa, D. Shin, T. Hanyu

Journal of Applied Logics　7　(1)　41-58　2020/01
First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400℃ thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology Peer-reviewed

H. Honjo, T. V. A. Nguyen, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, S. Miura, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, A. Tamakoshi, M. Natsui, Y. Ma, H. Koike, Y. Takahashi, K. Furuya, H. Shen, S. Fukami, H. Sato, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

International Electron Device Meeting　2019-December　2019/12

DOI： 10.1109/IEDM19573.2019.8993443 　

ISSN： 0163-1918
Multi-Context TCAM-Based Selective Computing Architecture for a Low-Power NN International-journal Peer-reviewed

R. Arakawa, N. Onizawa, T. Hanyu

Proc. 26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS) 2019　117-118　2019/11

DOI： 10.1109/ICECS46596.2019.8964869 　
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic International-journal Peer-reviewed

D. Shin, N. Onizawa, T. Hanyu

Proc. 26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS) 2019,　115-116　2019/11

DOI： 10.1109/ICECS46596.2019.8965097 　
A Design Framework for Invertible Logic Peer-reviewed

N. Onizawa, K. NIshino, S. C. Smithson, B. H. Meyer, W. J. Gross, H. Yamagata, H. Fujita, T. Hanyu

Proc. 53rd Asilomar Conference on Signals, Systems, and Computers　2019/11
Publisher: IEEE
DOI： 10.1109/ieeeconf44664.2019.9048700 　
Stochastic-Computing Based Branware LSI Towards an Intelligence Edge Invited Peer-reviewed

N. ONizawa, W. J. Gross, T. Hanyu

Proc. 26th IEEE International Conference on Electrocnis, Circuits & Systems (ICECS) 2019,　2019/11
MTJ-Based Nonvolatile Logic-in-Memory Circuit with Feedback-Type Equal-Resistance Sensing Mechanism for Ternary Neural Network Hardware

Masanori Natsui, Takahiro Hanyu

2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019　2019/10/14
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/S3S46989.2019.9320674 　
Design of an Energy-Efficient Controller for Realizing a Data-Shift-Minimized Nonvolatile FPGA Peer-reviewed

SUZUKI Daisuke, TAKAHIRO Hanyu

International Conference on Solid-State Devices and Materials　525-526　2019/09
Efficient CMOS Invertible Logic Using Stochastic Computing Peer-reviewed

S. Smithson, N. Onizawa, B. H. Meyer, W. J. Gross, T. Hanyu

IEEE Trans. on Circuits and Syst. I Reg. Papers　66　(6)　2263-2274　2019/06

DOI： 10.1109/TCSI.2018.2889732 　
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks

Tomoki Chiba, Masanori Natsui, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　2019-　91-96　2019/05/01
Publisher: IEEE Computer Society
DOI： 10.1109/ISMVL.2019.00024 　

ISSN： 0195-623X
Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure Peer-reviewed

SUZUKI Daisuke, TAKAHIRO Hanyu

Japanese Journal of Applied Physics　58　(SB)　SBBB10~1-SBBB10~7　2019/04
12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Digest of Technical Papers - IEEE International Solid-State Circuits Conference　2019-February　202-204　2019/03/06

DOI： 10.1109/ISSCC.2019.8662431 　

ISSN： 0193-6530
Brain-inspired computing

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

Stochastic Computing: Techniques and Applications　185-199　2019/02/18
Publisher: Springer International Publishing
DOI： 10.1007/978-3-030-03730-7_10 　
Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware

Masanori Natsui, Tomoki Chiba, Takahiro Hanyu

Japanese Journal of Applied Physics　58　2019
Publisher: Institute of Physics Publishing
DOI： 10.7567/1347-4065/aafb4d 　

ISSN： 1347-4065 0021-4922
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. Peer-reviewed

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

J. Solid-State Circuits　54　(11)　2991-3004　2019

DOI： 10.1109/JSSC.2019.2930910 　

ISSN： 0018-9200

eISSN： 1558-173X
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices Peer-reviewed

Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu

Microelectronics Journal　83　39-49　2019/01

DOI： 10.1016/j.mejo.2018.10.013 　
A Fully Nonvolatile Microcontroller Unit with Embedded STT-MRAM and FPGA-Based Accelerator for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Peer-reviewed

M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, T. Hanyu

IEEE Journal of Solid State Circuits　54　(11)　2991-3004　2019

DOI： 10.1109/JSSC.2019.2930910 　

ISSN： 0018-9200

eISSN： 1558-173X
Design of MTJ-Based nonvolatile logic gates for quantized neural networks

Masanori Natsui, Tomoki Chiba, Takahiro Hanyu

Microelectronics Journal　82　13-21　2018/12/01
Publisher: Elsevier Ltd
DOI： 10.1016/j.mejo.2018.10.005 　

ISSN： 0026-2692
Recent Trends in MTJ-Based Nonvolatile FPGA

Daisuke Suzuki, Takahiro Hanyu

CSRN-Osaka Annual Workshop　2018/12
Study of Stochastic Invertible Multiplier Designs Peer-reviewed

K. Nishino, S. Smituhson, N. Onizawa, B. H. Myer, W. J. Gross, H. Yamagata, H. Fujita, T. Hanyu

Proc. IEEE International Conference on Electronics, Circuits & Systems (ICECS) 2018　649-650　2018/12
MTJ-Based Asynchronous Circuits for Re-Initialization Free Computing against Power Failures Peer-reviewed

N. Onizawa, M. Imai, T. Yoneda, T. Hanyu

Microelectronics Journal　82　46-61　2018/12

DOI： 10.1016/j.mejo.2018.10.012 　
Networked Power-Gated MRAMs for Memory-Based Computing Peer-reviewed

J.-P. Diguet, N. Onizawa, M. Rizk, M. J. Sepulveda, A. Baghdadi, T. Hanyu

IEEE Trans. on Very Large Scale Integration (VLSI) Systems,　26　(12)　2696-2708　2018/12

DOI： 10.1109/TVLSI.2018.2856458 　
Application of Stochastic Computing in Brainware Invited Peer-reviewed

W. J. Gross, N. Onizawa, K. Matsumiya, T. Hanyu

Nonlinear Theory and Its Applications, IEICE,　E9-N　(4)　406-422　2018/10

DOI： 10.1587/nolta.9.406 　
A High-Read-Margin MTJ-Based Fracturable Lookup Table Circuit Using a Series-NMOS-Resistance-Reduced Logic-in-Memory Structure Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

Extended Abstracts of 2018 International Conference on Solid State Devices and Materials (SSDM2018)　117-118　2018/09
書込み回数最小化に基づく省エネルギー不揮発Lookup Table回路の構成

岡貴弘, 鈴木大輔, 羽生貴弘

平成30年度電気関係学会東北支部連合大会講演論文集　1E16　2018/09
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation with Dynamic Voltage-Frequency-Length Scaling Peer-reviewed

Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)　8　(3)　444-453　2018/09

DOI： 10.1109/JETCAS.2018.2844329 　
Systematic intrusion detection technique for an in-vehicle network based on time-series feature extraction

Hiroki Suda, Masanori Natsui, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　2018-　56-61　2018/07/19
Publisher: IEEE Computer Society
DOI： 10.1109/ISMVL.2018.00018 　

ISSN： 0195-623X
低電力・高性能な不揮発MCU実現に向けた要素回路IPの開発

Daisuke Suzuki, Takahiro Hanyu

ImPACT佐橋プログラム公開成果報告会　128-129　2018/06
低電力・高性能な不揮発MCU実現に向けた自律制御型パワーゲーティング技術

Daisuke Suzuki, Takahiro Hanyu

ImPACT佐橋プログラム公開成果報告会　126-127　2018/06
MTJ-based nonvolatile logic LSI for ultra low-power and highly dependable computing Peer-reviewed

Masanori Natsui, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

China Semiconductor Technology International Conference 2018, CSTIC 2018　1-4　2018/05/29
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/CSTIC.2018.8369189 　
MTJ ベース多機能不揮発Lookup Table 回路の設計

鈴木大輔, 岡貴弘, 羽生貴弘

信学技報, RECONF2018-12　59-64　2018/05
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter Peer-reviewed

S. Mukaida, N. Onizawa, T. Hanyu

48th International Symposium on Multiple-Valued Logic (ISMVL)　156-161　2018/05
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure Peer-reviewed

Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

Proceedings of IEEE International Symposium on Circuits and Systems　2018/05

DOI： 10.1109/ISCAS.2018.8351186 　
Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

Japanese Journal of Applied Physics　57　(4)　2018/04/01
Publisher: Japan Society of Applied Physics
DOI： 10.7567/JJAP.57.04FE09 　

ISSN： 1347-4065 0021-4922
Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit Peer-reviewed

Masanori Natsui, Takahiro Hanyu

Japanese Journal of Applied Physics　57　(4)　2018/04/01
Publisher: Japan Society of Applied Physics
DOI： 10.7567/JJAP.57.04FN03 　

ISSN： 1347-4065 0021-4922
Design of stochastic asymmetric compensation filters for auditory signal processing Peer-reviewed

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu

2017 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2017 - Proceedings　2018-　1315-1319　2018/03/07
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/GlobalSIP.2017.8309174 　
MTJ素子を用いた高度演算機能を有する不揮発LUT回路の構成

鈴木大輔, 羽生貴弘

2018年電子情報通信学会総合大会講演論文集　58-58　2018/03
Minimum Power Supply Asynchronous Circuits for Re-initialization Free Computing Peer-reviewed

M. Imai, N. Onizawa, T. Hanyu, T. Yoneda

21st Workshop on Synthesis And System Integration of Mixed Information Technologies　283-288　2018/03
Energy-Efficient MTJ-Based Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

Kick-off Symposium for World Leading Research Centers -Materials Science and Spintronics-　135-135　2018/02
Design of a Multi-Functional MTJ-Based FPGA for an Ultra-Low-Power IoT Applications

Daisuke Suzuki, Takahiro Hanyu

Kick-off Symposium for World Leading Research Centers -Materials Science and Spintronics-　136-136　2018/02
MTJ-Based Nonvolatile FPGA for Brainware LSI Platform

Daisuke Suzuki, Takahiro Hanyu

Abstracts of The 5th International Symposium on Brainware LSI　3-3　2018/02
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

Proceedings of 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018)　291-291　2018/02
不揮発FPGAを用いた脳型情報処理アクセラレータの構成

鈴木大輔, 羽生貴弘

信学会第２種研究会「多値論理とその応用」予稿集　45-50　2018/01
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception Peer-reviewed

K. Boga, F. Leduc-Primeaur, N. Onizawa, K. Matsumiya, T. Hanyu, W. J. Gross

Journal of Signal Processing Systems (JSPS)　90　(5)　709-725　2018

DOI： 10.1007/s11265-016-1197-3 　
An Area/Power-Aware 32-channel compressive gammachirp filterbank chip based on hybrid stochastic/binary computation Peer-reviewed

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu

Nonlinear Theory and Its Applications, IEICE　E9-N　(4)　406-422　2018

DOI： 10.1587/nolta.9.423 　
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures Peer-reviewed

Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda

Proceedings - International Symposium on Asynchronous Circuits and Systems　2017-　118-125　2017/11/03
Publisher: IEEE Computer Society
DOI： 10.1109/ASYNC.2017.11 　

ISSN： 1522-8681
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation Peer-reviewed

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　25　(10)　2724-2735　2017/10

DOI： 10.1109/TVLSI.2017.2687404 　

ISSN： 1063-8210

eISSN： 1557-9999
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing Peer-reviewed

Arash Ardakani, Francois Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　25　(10)　2688-2699　2017/10

DOI： 10.1109/TVLSI.2017.2654298 　

ISSN： 1063-8210

eISSN： 1557-9999
Energy-Efficient High-Performance Nonvolatile VLSI Processor with a Temporary-Data Reuse Technique Peer-reviewed

M. Natsui, T. Hanyu

2017 International Conference on Solid State Devices and Materials (SSDM2017)　977-978　2017/09
Design of an MTJ-Oriented Nonvolatile Lookup Table Circuit with Write-Operation Minimizing Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

2017 International Conference on Solid State Devices and Materials (SSDM2017)　195-196　2017/09
Accuracy/Energy-Flexible Stochastic Configurable 2D Gabor Filter with Instant-on Capability Peer-reviewed

N. Onizawa, K. Matsumiya, W. J. Gross, T. Hanyu

43rd European Solid-State Circuit Conference (ESSCIRC)　43-46　2017/09

DOI： 10.1109/ESSCIRC.2017.8094521 　
NoC-MRAM architecture for memory-based computing: Database-search case study Peer-reviewed

M. Rizk, J-Ph. Diguet, N. Onizawa, A. Baghdadi, M. J. Sepulveda, Y. Akgul, V. Gripon, T. Hanyu

Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017　309-312　2017/08/11
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/NEWCAS.2017.8010167 　
Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications Peer-reviewed

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　56　(8)　0802B7-1-0802B7-7　2017/08

DOI： 10.7567/JJAP.56.0802B7 　

ISSN： 0021-4922

eISSN： 1347-4065
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E100D　(8)　1618-1624　2017/08

DOI： 10.1587/transinf.2016LOP0015 　

ISSN： 1745-1361
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation Peer-reviewed

Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E100D　(8)　1592-1602　2017/08

DOI： 10.1587/transinf.2016LOP0011 　

ISSN： 1745-1361
Evaluation of Stochastic Cascaded IIR Filters Peer-reviewed

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　224-229　2017/06/30
Publisher: IEEE Computer Society
DOI： 10.1109/ISMVL.2017.25 　

ISSN： 0195-623X
Challenge of Spintronics-Based Nonvolatile VLSI Processor with a Sudden Power-Outage Resilient In-Processor Checkpointing Invited

Takahiro Hanyu

2017 Spintronics Workshop on LSI　3　2017/06
Origin of variation of shift field via annealing at 400 degrees C in a perpendicular-anisotropy magnetic tunnel junction with [Co/Pt]-multilayers based synthetic ferrimagnetic reference layer Peer-reviewed

H. Honjo, S. Ikeda, H. Sato, T. Watanebe, S. Miura, T. Nasuno, Y. Noguchi, M. Yasuhira, T. Tanigawa, H. Koike, M. Muraguchi, M. Niwa, K. Ito, H. Ohno, T. Endoh

AIP ADVANCES　7　(5)　055913-1-055913-5　2017/05

DOI： 10.1063/1.4973946 　

ISSN： 2158-3226
Challenge of MOS/MTJ-Hybrid Nonvolatile VLSI Processor for IoE Applications Invited

Takahiro Hanyu

Emerging Technologies of Communications, Microsystems, Optoelectronics and Sensors 2017 (ETCMOS 2017)　2017/05
MTJ-Based Nonvolatile FPGA; the Present and the Future Technology Trends Invited

Daisuke Suzuki, Takahiro Hanyu

26th International Workshop on Post-Binary ULSI Systems　2　2017/05
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors Peer-reviewed

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING　5　(2)　151-163　2017/04

DOI： 10.1109/TETC.2016.2604083 　

ISSN： 2168-6750
Design of a variation-resilient single-ended non-volatile six-input lookup table circuit with a redundant-magnetic tunnel junction-based active load for smart Internet-of-things applications Peer-reviewed

D. Suzuki, M. Natsui, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

Electronics Letters　53　(7)　456-458　2017/03/30
Publisher: Institution of Engineering and Technology
DOI： 10.1049/el.2016.4233 　

ISSN： 0013-5194
Soft/write-error-resilient CMOS/magnetic tunnel junction nonvolatile flip-flop based on majority-decision shared writing

Onizawa Naoya, Hanyu Takahiro

Jpn. J. Appl. Phys.　56　(4)　04CF12　2017/03/21
Publisher: Institute of Physics
DOI： 10.7567/JJAP.56.04CF12 　

ISSN： 0021-4922

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A soft/write-error-resilient nonvolatile flip-flop (NVFF) using three-terminal magnetic tunnel junctions (MTJs) is presented. The proposed NVFF exploits a redundant structure with a majority bit implicitly stored, which is tolerant to soft errors including both single-event transients (SETs) and single-event upsets (SEUs). For write-error resilience, all the bits of the redundant MTJs are written using the majority bit with a shared write-current path, exhibiting 1-bit soft-error correction and 1-bit write-error masking. In addition, the shared writing scheme reduces the number of write-current paths to one-third of that with a redundant NVFF with 1-bit soft/write-error masking. Using 65 nm CMOS/MTJ technologies, the proposed NVFF achieves a few orders-of-magnitude reduction in the failure in time (FIT), a 31% reduction in the transistor count, and a 65% reduction in the write energy in comparison with the redundant NVFF.
Design of a variation-resilient single-ended non-volatile six-input lookup table circuit with a redundant-magnetic tunnel junction-based active load for smart Internet-of-things applications Peer-reviewed

D. Suzuki, M. Natsui, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

ELECTRONICS LETTERS　53　(7)　2017/03

DOI： 10.1049/el.2016.4233 　

ISSN： 0013-5194

eISSN： 1350-911X
A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching Peer-reviewed

Yitao Ma, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Japanease Journal of Applied Physics　56　(4S)　04CF08　2017/03
Publisher: Japan Society of Applied Physics
DOI： 10.7567/jjap.56.04cf08 　

ISSN： 0021-4922

eISSN： 1347-4065
A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing Peer-reviewed

Naoya Onizawa, Takahiro Hanyu

Japanese Journal of Applied Physics　56　(4S)　04CF12-1-04CF12-6　2017/03
Fabrication of an MTJ-Based Nonvolatile Logic-in-Memory LSI with Content-Aware Write Error Masking Scheme Achieving 92% Storage Capacity and 79% Power Reduction Peer-reviewed

Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Japanese Journal of Applied Physics　56　(4S)　04CN01-1-04CN01-5　2017/03
Design of a Low-Power Nonvolatile Flip-Flop Using 3-Terminal Magnetic-Tunnel-Junction-Based Self-Terminated Mechanism Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

Japanese Journal of Applied Physics　56　(4S)　04CN06-1-04CN06-5　2017/03
Publisher: Institute of Physics
DOI： 10.7567/JJAP.56.04CN06 　

ISSN： 0021-4922

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A nonvolatile flip-flop (NV-FF) using a three-terminal magnetic tunnel junction (3T-MTJ)-based self-terminated mechanism is proposed for a low-power logic LSI while maintaining almost the same performance as a conventional CMOS-based logic LSI. The use of a self-terminated mechanism, which continuously monitors the change in MTJ resistance, makes it possible not only to minimize the write energy consumption for the 3T-MTJ device but also to ensure a reliable write. Moreover, since the write current path is separated from the read current path in the 3T-MTJ device, the sensing circuit and the write driver are individually optimized, which makes it possible to minimize the performance overhead due to additional components. As a result, the write energy of the proposed NV-FF is reduced by 69% with a small performance overhead compared with that of a conventional NV-FF using a worst-case-oriented writing scheme.
Challenge of Spintronics-Device-Based Non-volatile Logic-in-Memory Architecture for Internet-of-Things Applications Invited

T. Hanyu

BIT's 3rd Annual World Congress of Smart Materials-2017　262　2017/03
Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

Natsui Masanori, Tamakoshi Akira, Endoh Tetsuo, Ohno Hideo, Hanyu Takahiro

Jpn. J. Appl. Phys.　56　(4)　04CN01　2017/02/16
Publisher: Institute of Physics
DOI： 10.7567/JJAP.56.04CN01 　

ISSN： 0021-4922

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A magnetic-tunnel-junction (MTJ)-based video coding hardware with an MTJ-write-error-rate relaxation scheme as well as a nonvolatile storage capacity reduction technique is designed and fabricated in a 90 nm MOS and 75 nm perpendicular MTJ process. The proposed MTJ-oriented dynamic error masking scheme suppresses the effect of write operation errors on the operation result of LSI, which results in the increase in an acceptable MTJ write error rate up to 7.8 times with less than 6% area overhead, while achieving 79% power reduction compared with that of the static-random-access-memory-based one.
脳型計算に基づく車載ネットワークの不正侵入検出法

須田拓樹, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2017　60-60　2017
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2017.0_60 　
Three-Terminal MTJ-Based Nonvolatile Logic Circuits with Self-Terminated Writing Mechanism for Ultra-Low-Power VLSI Processor Invited Peer-reviewed

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui

PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)　548-553　2017

DOI： 10.23919/DATE.2017.7927048 　

ISSN： 1530-1591
Beyond MRAM: Nonvolatile Logic-in-Memory VLSI Peer-reviewed

Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, Hideo Ohno

Introduction to Magnetic Random-Access Memory　199-229　2016/11/26
Publisher: wiley
DOI： 10.1002/9781119079415.ch7 　
A Self-Terminated One-Phase Write Driver for Complementary-MTJ Based Memory Cells Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

61th Annual Conference on Magnetism & Magnetic Materials (MMM),　554　2016/11
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing Peer-reviewed

Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno

PROCEEDINGS OF THE IEEE　104　(10)　1844-1863　2016/10

DOI： 10.1109/JPROC.2016.2574939 　

ISSN： 0018-9219

eISSN： 1558-2256
Highly Reliable MTJ-Based Nonvolatile Logicin-Memory LSI with Content-Aware Write Error Masking Scheme Peer-reviewed

M.Natsui, A.Tamakoshi, T.Endoh, H.Ohno, T.Hanyu

International Conference on Solid State Devices and Materials (SSDM)　B-2-03　77-78　2016/09/26
A Compact and Ultra-Low-Power STT-MRAMBased Associative Memory for Nearest Neighbor Search with Full Adaptivity of Template Data Format Employing Current-Mode Similarity Evaluation and Time-Domain Minimum Searching Peer-reviewed

Y.Ma, S.Miura, H.Honjo, S.Ikeda, T.Hanyu, H.Ohno, T.Endoh

International Conference on Solid State Devices and Materials (SSDM)　B-2-06　83-84　2016/09/26
Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips Peer-reviewed

Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu

IEEE TRANSACTIONS ON NANOTECHNOLOGY　15　(5)　705-714　2016/09

DOI： 10.1109/TNANO.2015.2511151 　

ISSN： 1536-125X

eISSN： 1941-0085
Highly Reliable MTJ-Based Motion-Vector Prediction Unit with Dynamic Write Error Masking Scheme Peer-reviewed

Masanori Natsui, Akira Tamakoshi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proc. of 2016 International Conference on Solid State Devices and Materials　77-78　2016/09
A Soft/Write-Error Resilient CMOS/MTJ Nonvolatile Flip-Flop Based on Majority-Decision Shared Writing Peer-reviewed

Naoya Onizawa, Takahiro Hanyu

Proc. of 2016 International Conference on Solid State Devices and Materials　79-80　2016/09
A Self-Terminated Energy-Efficient Nonvolatile Flip-Flop Using 3-terminal Magnetic Tunnel Junction Device Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

Proc. of 2016 International Conference on Solid State Devices and Materials　911-912　2016/09
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design Peer-reviewed

M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, T. Hanyu

Proceedings - IEEE International Symposium on Circuits and Systems　2016-　1878-1881　2016/07/29
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/ISCAS.2016.7538938 　

ISSN： 0271-4310
An Overview of Nonvolatile Emerging Memories-Spintronics for Working Memories Peer-reviewed

Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS　6　(2)　109-119　2016/06

DOI： 10.1109/JETCAS.2016.2547704 　

ISSN： 2156-3357
Power-Gated Single-Track Asynchronous Circuits Using Three-Terminal MTJ-Based Nonvolatile Devices for Energy Harvesting Systems Peer-reviewed

T. Yoneda, N. Onizawa, M. Imai, T. Hanyu

22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) Fresh Idea Track　9-10　2016/05
A 600-mu W ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme Peer-reviewed

Yitao Ma, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

JAPANESE JOURNAL OF APPLIED PHYSICS　55　(4)　04EF15-1-04EF15-11　2016/04

DOI： 10.7567/JJAP.55.04EF15 　

ISSN： 0021-4922

eISSN： 1347-4065
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks Peer-reviewed

Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS　6　(1)　13-24　2016/03

DOI： 10.1109/JETCAS.2016.2528721 　

ISSN： 2156-3357
スピントロニクスのデバイス応用 Invited Peer-reviewed

遠藤哲郎, 小池洋紀, 池田正二, 羽生貴弘, 大野英男

電子情報通信学会論文誌 C　J99-C　(1)　1-9　2016/01/14
Approximate Computingに基づく脳型LSIの高精度・省電力・省面積実装技術の一考察

加藤健太郎, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2016　40-40　2016
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2016.0_40 　
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory Peer-reviewed

N. Onizawa, N. Sakimura, R. Nebashi, T. Sugibayashi, T. Hanyu

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　26　(1-2)　125-140　2016

ISSN： 1542-3980

eISSN： 1542-3999
Gammatone Filter Based on Stochastic Computation Peer-reviewed

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu

2016 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING PROCEEDINGS　1036-1040　2016

DOI： 10.1109/ICASSP.2016.7471833 　

ISSN： 1520-6149
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

2016 IEEE 46TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2016)　5-10　2016

DOI： 10.1109/ISMVL.2016.50 　

ISSN： 0195-623X
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission Peer-reviewed

Naoto Sugaya, Masanori Natsui, Takahiro Hanyu

2016 IEEE 46TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2016)　72-77　2016

DOI： 10.1109/ISMVL.2016.42 　

ISSN： 0195-623X
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation Peer-reviewed

Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

2016 IEEE 46TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2016)　223-228　2016

DOI： 10.1109/ISMVL.2016.40 　

ISSN： 0195-623X
Stochastic Behavior-Considered VLSI CAD Environment for MTJ/MOS-Hybrid Microprocessor Design Peer-reviewed

M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, T. Hanyu

2016 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)　1878-1881　2016

DOI： 10.1109/ISCAS.2016.7538938 　

ISSN： 0271-4302
Redundant STT-MTJ-Based Nonvolatile Flip-Flops for Low Write-Error-Rate Operations Peer-reviewed

Naoya Onizawa, Takahiro Hanyu

2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　1-4　2016

DOI： 10.1109/NEWCAS.2016.7604792 　

ISSN： 2472-467X
A Study of a Top-Down Error Correction Technique Using Recurrent-Neural-Network-Based Learning Peer-reviewed

Masanori Natsui, Naoto Sugaya, Takahiro Hanyu

2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　2016

DOI： 10.1109/NEWCAS.2016.7604786 　

ISSN： 2472-467X
A Low-Power MTJ-Based Nonvolatile FPGA Using Self-Terminated Logic-In-Memory Structure Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

2016 26TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL)　1-4　2016

DOI： 10.1109/FPL.2016.7577345 　

ISSN： 1946-1488
VLSI Implementation of Deep Neural Networks Using Integral Stochastic Computing Peer-reviewed

Arash Ardakani, Fracois Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

2016 9TH INTERNATIONAL SYMPOSIUM ON TURBO CODES AND ITERATIVE INFORMATION PROCESSING (ISTC)　216-220　2016

DOI： 10.1109/ISTC.2016.7593108 　

ISSN： 2165-4700
MTJ素子を活用した高性能・高信頼VLSI設計技術 Invited Peer-reviewed

夏井雅典, 鈴木大輔, 池田正二, 遠藤哲郎, 大野英男, 羽生貴弘

応用物理学会スピントロニクス研究会・日本磁気学会スピンエレクトロニクス専門研究会・日本磁気学会ナノマグネティックス専門研究会共同主催研究会　2015/11/12
Spintronics-Based Logic-in-Memory Architecture Towards Dark Silicon Era Invited

T. Hanyu

International Workshop: Spintronics VLSI　9　2015/11
Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing Peer-reviewed

Takahiro Hanyu, Masanori Natsui, Daisuke Suzuki, Akira Mochizuki, Naoya Onizawa, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S),　1-3　2015/10/05

DOI： 10.1109/S3S.2015.7333502 　
A 600-μW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing Magnetic Tunnel Junction (MTJ) Based Nonvolatile Memories with Novel Intelligent Power-Gating (IPG) Scheme Peer-reviewed

Y. Ma, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, T. Shibata, T. Endoh

2015 International Conference on Solid State Devices and Materials(SSDM)　O-4-2　1172-1173　2015/09/29
Gabor Filter Based on Stochastic Computation Peer-reviewed

Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

IEEE SIGNAL PROCESSING LETTERS　22　(9)　1224-1228　2015/09

DOI： 10.1109/LSP.2015.2392123 　

ISSN： 1070-9908

eISSN： 1558-2361
Challenge of MOS/MTJ-Hybrid Integrated Circuits Based on Nonvolatile Logic-in-Memory Architecture

T. Hanyu

2015 Spintronics Workshop on LSI　7　2015/06
Magnetic-tunnel-junction based low-energy nonvolatile flip-flop using an area-efficient self-terminated write driver Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

JOURNAL OF APPLIED PHYSICS　117　(17)　17B504-1-17B504-3　2015/05

DOI： 10.1063/1.4906760 　

ISSN： 0021-8979

eISSN： 1089-7550
不揮発ロジックインメモリアーキテクチャとその低電力VLSIシステムへの応用 Invited Peer-reviewed

羽生貴弘, 鈴木大輔, 望月明, 夏井雅典, 鬼沢直哉, 杉林直彦, 池田正二, 遠藤哲郎, 大野英男

集積回路研究会　115　(6)　57-61　2015/04/17
Publisher:
ISSN： 0913-5685
Nonvolatile field-programmable gate array using 2-transistor-1-MTJ-cell-based multi-context array for power and area efficient dynamically reconfigurable logic Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　54　(4)　2015/04

DOI： 10.7567/JJAP.54.04DE01 　

ISSN： 0021-4922

eISSN： 1347-4065
Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation Peer-reviewed

Hiroki Koike, Takashi Ohsawa, Sadahiko Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

JAPANESE JOURNAL OF APPLIED PHYSICS　54　(4)　04DE08　2015/04

DOI： 10.7567/JJAP.54.04DE08 　

ISSN： 0021-4922

eISSN： 1347-4065
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction Peer-reviewed

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEEE JOURNAL OF SOLID-STATE CIRCUITS　50　(2)　476-489　2015/02

DOI： 10.1109/JSSC.2014.2362853 　

ISSN： 0018-9200

eISSN： 1558-173X
Nonvolatile Logic-in-Memory Architecture for Ultra-Low-Power VLSI Systems Invited Peer-reviewed

T. Hanyu

Forum in ISSCC 2015　2015/02
リカレントニューラルネットワークに基づく時系列データ誤り訂正技術とその応用

菅谷直登, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2015　93-93　2015
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2015.0_93 　
MTJベース不揮発ロジックLSIにおける電源スイッチ構造の最適化設計

田畑佑樹, 鈴木大輔, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2015　92-92　2015
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2015.0_92 　
Fabrication of a 3000-6-Input-LUTs Embedded and Block-Level Power-Gated Nonvolatile FPGA Chip Using p-MTJ-Based Logic-in-Memory Structure Peer-reviewed

D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS)　2015-August　7223644　2015

DOI： 10.1109/VLSIT.2015.7223644 　
Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm Invited Peer-reviewed

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki

2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)　1006-+　2015

ISSN： 1530-1591
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors Peer-reviewed

Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu

2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　109-114　2015

DOI： 10.1109/ISMVL.2015.28 　

ISSN： 0195-623X
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time Peer-reviewed

Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu

2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　152-157　2015

DOI： 10.1109/ISMVL.2015.18 　

ISSN： 0195-623X
Design of an STT-MTJ Based True Random Number Generator Using Digitally Controlled Probability-Locked Loop Peer-reviewed

Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu

2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　2015

DOI： 10.1109/NEWCAS.2015.7182089 　

ISSN： 2472-467X
Fabrication of a 3000-6-Input-LUTs Embedded and Block-Level Power-Gated Nonvolatile FPGA Chip Using p-MTJ-Based Logic-in-Memory Structure Peer-reviewed

D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

2015 SYMPOSIUM ON VLSI TECHNOLOGY (VLSI TECHNOLOGY)　172-173　2015
A Sudden Power-Outage Resilient Nonvolatile Microprocessor for Immediate System Recovery Peer-reviewed

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

PROCEEDINGS OF THE 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 15)　39-44　2015

DOI： 10.1109/NANOARCH.2015.7180584 　

ISSN： 2327-8218
Frequency-Flexible Stochastic Gabor Filter Peer-reviewed

Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP)　458-462　2015

DOI： 10.1109/ICDSP.2015.7251914 　
Design of an MTJ-Based Nonvolatile Lookup Table Circuit Using an Energy-Efficient Single-Ended Logic-In-Memory Structure Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)　317-320　2015

DOI： 10.1109/MWSCAS.2015.7282195 　

ISSN： 1548-3746
Scaled IIR Filter Based on Stochastic Computation Peer-reviewed

Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu

2015 IEEE 58TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)　297-300　2015

DOI： 10.1109/MWSCAS.2015.7282118 　

ISSN： 1548-3746
Stochastic Implementation of the Disparity Energy Model for Depth Perception Peer-reviewed

Kaushik Boga, Naoya Onizawa, Francois Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross

2015 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2015)　1-6　2015

DOI： 10.1109/SiPS.2015.7344982 　
Multiple-Event-Transient Soft-Error Gate-Level Simulator for Harsh Radiation Environments Peer-reviewed

Akira Mochizuki, Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

TENCON 2015 - 2015 IEEE REGION 10 CONFERENCE　1-6　2015

DOI： 10.1109/TENCON.2015.7373147 　

ISSN： 2159-3442
Design of a Computational Nonvolatile RAM for a Greedy Energy-Efficient VLSI Processor Peer-reviewed

Akira Mochizuki, Naoto Yube, Takahiro Hanyu

IECON 2015 - 41ST ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY　3283-3288　2015

DOI： 10.1109/IECON.2015.7392606 　

ISSN： 1553-572X
磁気ランダムアクセスメモリ（MRAM）の最新技術動向 Invited Peer-reviewed

小池洋紀, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎

CVD研究会　2014/12/18
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture Peer-reviewed

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS　4　(4)　460-474　2014/12

DOI： 10.1109/JETCAS.2014.2361061 　

ISSN： 2156-3357
Cost-Efficient Self-Terminated Write Driver for Spin-Transfer-Torque RAM and Logic Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu

IEEE TRANSACTIONS ON MAGNETICS　50　(11)　3402104~1-3402104~4　2014/11

DOI： 10.1109/TMAG.2014.2322387 　

ISSN： 0018-9464

eISSN： 1941-0069
MTJ-Based Low-Energy Nonvolatile Flip-Flop Using Area-Efficient Self-Terminated Write Driver Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

59th Annual Conference on Magnetism & Magnetic Materials (MMM)　813　2014/11
Algorithm and Architecture for a Multiple-Field Context-Driven Search Engine Using Fully-Parallel Clustered Associative Memories Peer-reviewed

Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

2014 IEEE International Workshop on Signal Processing Systems (SIPS)　133-138　2014/10

DOI： 10.1007/s11265-014-0886-z 　
A 500ps/8.5ns Array Read/Write Latency 1Mb Twin 1T1MTJ STT-MRAM designed in 90nm CMOS/40nm MTJ Process with Novel Positive Feedback S/A Circuit Peer-reviewed

T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

International Conference on Solid State Dvices and Materails (SSDM)　A-8-3　2014/09/09
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip Peer-reviewed

Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E97D　(9)　2304-2311　2014/09

DOI： 10.1587/transinf.2013LOP0024 　

ISSN： 1745-1361
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model Peer-reviewed

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E97D　(9)　2286-2295　2014/09

DOI： 10.1587/transinf.2013LOP0010 　

ISSN： 1745-1361
Optimally Self-Terminated Compact Switching Circuit Using Continuous Voltage Monitoring Achieving High Read Margin for STT MRAM and Logic Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu

IEEE Intermag 2014　2506-2507　2014/09
Challenge of Nonvolatile Logic-in-Memory Architecture: Design Examples and the Future Prospects Invited

Takahiro Hanyu

2014 Spintronics Workshop on LSI　3　2014/09
Nonvolatile FPGA Using 2T-1MTJ-Cell-Based Multi-Context Array for Power and Area Efficient Dynamically Reconfigurable Logic Peer-reviewed

Daisuke Suzuki, Takahiro Hanyu

International Conference on Solid State Devices and Materials (SSDM)　450-451　2014/09
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model Peer-reviewed

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY　76　(2)　185-194　2014/08

DOI： 10.1007/s11265-013-0854-z 　

ISSN： 1939-8018

eISSN： 1939-8115
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs Peer-reviewed

Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E97D　(6)　1546-1556　2014/06

DOI： 10.1587/transinf.E97.D.1546 　

ISSN： 1745-1361
Analysis of single-event upset of magnetic tunnel junction used in spintronic circuits caused by radiation-induced current Peer-reviewed

N. Sakimura, R. Nebashi, M. Natsui, H. Ohno, T. Sugibayashi, T. Hanyu

JOURNAL OF APPLIED PHYSICS　115　(17)　17B748-1-17B748-3　2014/05

DOI： 10.1063/1.4869287 　

ISSN： 0021-8979

eISSN： 1089-7550
Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure Peer-reviewed

D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, S. Fukami, H. Sato, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

JOURNAL OF APPLIED PHYSICS　115　(17)　17B742-1-17B742-3　2014/05

DOI： 10.1063/1.4868332 　

ISSN： 0021-8979

eISSN： 1089-7550
Studies on read-stability and write-ability of fast access STT-MRAMs Peer-reviewed

T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)　1-2　2014/04/28

DOI： 10.1109/VLSI-TSA.2014.6839665 　
全文検索システム向け階層的パワーゲーティングを活用した低エネルギー不揮発TCAMエンジンチップ Peer-reviewed

松永翔雲, 崎村昇, 根橋竜介, 杉林直彦(N, 夏井雅典, 望月明, 遠藤哲郎, 大野英男, 羽生貴弘

信学技報　114　(13)　39-44　2014/04/17

ISSN： 0913-5685
1.5ns/2.1nsのランダム読出／書込サイクル時間を達成した不揮発性混載メモリ用1Mb STT-MRAM －6T2MTJセルにバックグラウンド書き込み（BGW）方式を適用 Invited Peer-reviewed

大澤隆, 小池洋紀, 三浦貞彦, 木下啓藏, 本庄弘明, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎

信学技報　114　(13)　33-38　2014/04/17
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper reports on a 1Mb STT-MRAM achieving 2.1nsec write cycle with background write (BGW) scheme applied to a 6T2MTJ memory cell in which a pair of MTJs are switched by using the data updated in a CMOS latch in a fast write cycle. By this scheme, fast embedded memories like L3 and L2 cache can be made nonvolatile to achieve low-power computers.
MTJベース不揮発フリップフロップを用いた3μsec-Entry/Exit 遅延時間のマイクロプロセッサ Invited Peer-reviewed

小池洋紀, 崎村昇, 根橋竜介, 辻幸秀, 森岡あゆ香, 三浦貞彦, 本庄弘明, 杉林直彦, 大澤隆, 池田正二, 羽生貴弘, 大野英男, 遠藤哲郎

信学技報　114　(13)　85-90　2014/04/17
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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We propose a novel power-gated microprocessor unit (MPU) using a nonvolatile flip-flop (NV-F/F) with magnetic tunnel junction (MTJ). By using the NV-F/F to store the MPU's internal state, this MPU realizes power-gating operation with a small 3-μsec entry/exit delay penalty in power-on/power-off. To achieve this short entry/exit delay, an appropriate NV-F/F circuit, which can perform stable high speed store/recall operations, has been developed. The MPU will help in the realization of low power systems due to its easy controllability for the power gating mode.
Design and evaluation of a 67% area-less 64-bit parallel reconfigurable 6-input nonvolatile logic element using domain-wall motion devices Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　53　(4)　04EM03-1-04EM03-5　2014/04

DOI： 10.7567/JJAP.53.04EM03 　

ISSN： 0021-4922

eISSN： 1347-4065
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism Peer-reviewed

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS　61　(3)　865-876　2014/03

DOI： 10.1109/TCSI.2013.2283997 　

ISSN： 1549-8328

eISSN： 1558-0806
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router Peer-reviewed

Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu

IEEE TRANSACTIONS ON COMPUTERS　63　(3)　637-649　2014/03

DOI： 10.1109/TC.2013.81 　

ISSN： 0018-9340

eISSN： 1557-9956
Trend of tunnel magnetoresistance and variation in threshold voltage for keeping data load robustness of metal–oxide–semiconductor/magnetic tunnel junction hybrid latches Peer-reviewed

T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

Journal of Applied Physics (JAP)　115　(17)　17C728-1-17C728-3　2014/02/01

DOI： 10.1063/1.4867129 　
Power Reduction by Power Gating in Differential Pair Type STT-MRAMs for Low-Power Nonvolatile Cache Memories Peer-reviewed

Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Testuo Endoh

Japanese Journal of Applied Physics(JJAP)　53　(4S)　04ED04-1-04ED04-11　2014/02/01
Publisher: Institute of Physics
DOI： 10.7567/JJAP.53.04ED04 　

ISSN： 0021-4922
A Two-Transistor Bootstrap Type Selective Device for Spin-Transfer-Torque Magnetic Tunnel Junctions Peer-reviewed

Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Testuo Endoh

Japanese Journal of Applied Physics(JJAP)　53　(4S)　04ED03-1-04ED03-6　2014/02/01
Publisher: Institute of Physics
DOI： 10.7567/JJAP.53.04ED03 　

ISSN： 0021-4922
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing Peer-reviewed

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Proceedings - IEEE International Symposium on Circuits and Systems　1588-1591　2014
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/ISCAS.2014.6865453 　

ISSN： 0271-4310
Energy-aware current-mode inter-chip link for a dependable GALS NoC platform Peer-reviewed

Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu

Proceedings - IEEE International Symposium on Circuits and Systems　1865-1868　2014
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/ISCAS.2014.6865522 　

ISSN： 0271-4310
An NoC-based Evaluation Platform for Safety-Critical Automotive Applications Peer-reviewed

Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura

2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)　679-682　2014
Wide operational margin capability of 1 kbit spin-transfer-torque memory array chip with 1-PMOS and 1-bottom-pin-magnetic-tunnel-junction type cell Peer-reviewed

H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

Japanese Journal of Applied Physics　53　(4 SPEC. ISSUE)　2014

DOI： 10.7567/JJAP.53.04ED13 　

ISSN： 0021-4922

eISSN： 1347-4065
A 1Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell with 32b Fine-Grained Power Gating Scheme Peer-reviewed

T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno

IEEE Journal of Solid State Circuits　48　(6)　1511-1520　2014

DOI： 10.1109/JSSC.2013.2253412 　

ISSN： 0018-9200
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme Peer-reviewed

Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE ELECTRONICS EXPRESS　11　(3)　20131006-1-20131006-10　2014

DOI： 10.1587/elex.11.20131006 　

ISSN： 1349-2543
A 90nm 20MHz Fully Nonvolatile Microcontroller for Standby-Power-Critical Applications Peer-reviewed

Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi

2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)　57　184-+　2014

DOI： 10.1109/ISSCC.2014.6757392 　

ISSN： 0193-6530
Fabrication of a MTJ-Based Multilevel Resistor Towards Process-Variaton-Resilient Logic LSI Peer-reviewed

Masanori Natsui, Takahiro Hanyu

2014 IEEE 12TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　468-471　2014

DOI： 10.1109/NEWCAS.2014.6934084 　

ISSN： 2472-467X
Design of a Soft-Error Tolerant 9-Transistor/6-Magnetic-Tunnel-Junction Hybrid Cell Based Nonvolatile TCAM Peer-reviewed

Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

2014 IEEE 12TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　193-196　2014

DOI： 10.1109/NEWCAS.2014.6934016 　

ISSN： 2472-467X
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme Peer-reviewed

Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE ELECTRONICS EXPRESS　11　(10)　20140297-1-20140297-7　2014

DOI： 10.1587/elex.11.20140297 　

ISSN： 1349-2543
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure Peer-reviewed

Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE ELECTRONICS EXPRESS　11　(13)　20140296-1-20140296-11　2014

DOI： 10.1587/elex.11.20140296 　

ISSN： 1349-2543
A compact soft-error tolerant asynchronous TCAM based on a transistor/magnetic-tunnel-junction hybrid dual-rail word structure Peer-reviewed

Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

Proceedings - International Symposium on Asynchronous Circuits and Systems　1-8　2014
Publisher: IEEE Computer Society
DOI： 10.1109/ASYNC.2014.9 　

ISSN： 1522-8681
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-Chip Asynchronous Communication Link Peer-reviewed

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014)　67-72　2014

DOI： 10.1109/ISMVL.2014.20 　

ISSN： 0195-623X
Associative Memories Based on Multiple-Valued Sparse Clustered Networks Peer-reviewed

Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014)　208-213　2014

DOI： 10.1109/ISMVL.2014.44 　

ISSN： 0195-623X
Soft-Delay-Error Evaluation in Content-Addressable Memory Peer-reviewed

Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu

2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014)　220-225　2014

DOI： 10.1109/ISMVL.2014.46 　

ISSN： 0195-623X
Variation-effect analysis of MTJ-based multiple-valued programmable resistors Peer-reviewed

Masanori Natsui, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　243-247　2014
Publisher: IEEE Computer Society
DOI： 10.1109/ISMVL.2014.50 　

ISSN： 0195-623X
Energy-Aware Current-Mode Inter-Chip Link for a Dependable GALS NoC Platform Peer-reviewed

Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)　1865-1868　2014

DOI： 10.1109/ISCAS.2014.6865522 　

ISSN： 0271-4302
A Delay Circuit with 4-Terminal Magnetic-Random-Access-Memory Device for Power-Efficient Time-Domain Signal Processing Peer-reviewed

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)　1588-1591　2014

DOI： 10.1109/ISCAS.2014.6865453 　

ISSN： 0271-4302
Analog-to-Stochastic Converter Using Magnetic-Tunnel Junction Devices Peer-reviewed

Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu

2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH)　59-64　2014

DOI： 10.1109/NANOARCH.2014.6880490 　

ISSN： 2327-8218
Highly Reliable Single-Ended Current-Mode Circuit for an Inter-Chip Asynchronous Communication Link Peer-reviewed

Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu

2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS)　683-686　2014

DOI： 10.1109/APCCAS.2014.7032873 　
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element Peer-reviewed

Naoya Onizawail, Takahiro Hanyu

IEICE ELECTRONICS EXPRESS　11　(24)　20141017　2014

DOI： 10.1587/elex.11.20141017 　

ISSN： 1349-2543
Challenge of MOS/MTJ-Hybrid Nonvolatile Logic-in-Memory Architecture in Dark-Silicon Era Invited Peer-reviewed

Takahiro Hanyu, Daisuke Suzuki, Akira Mochizuki, Masanori Natsui, Naoya Onizawa, Tadahiko Sugibayashi, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno

2014 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)　28.2.1-28.2.3　2014

DOI： 10.1109/IEDM.2014.7047124 　
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electronics Express　10　(23)　20130772　2013/11/21

DOI： 10.1587/elex.10.20130772 　

ISSN： 1349-2543
A Power-Gated MPU with 3-microsecond Entry/Exit Delay using MTJ-Based Nonvolatile Flip-Flop Peer-reviewed

Hiroki Koike, Takashi Ohsawa, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Katsuya Miura, Hiroaki Honjo, Tadahiko Sugibayashi, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

IEEE Asian Solid-State Circuits Conference (ASSCC2013)　317-320　2013/11/11

DOI： 10.1109/ASSCC.2013.6691046 　
Trend of TMR and Variation in Vth for Keeping Data Load Robustness of MOS/MTJ Hybrid Latches Peer-reviewed

Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

The 58th Annual Magnetism and Magnetic Materials Conference (MMM2013)　GT-10　693-693　2013/11/04
MTJ resistance distribution and its bit error rate of 1-kbit 1T-1MTJ STT-MRAM cell arrays fabricated on a 300-mm wafer Peer-reviewed

H. Koike, T. Ohsawa, S. Miura, H. Honjo, S. Ikeda, T. Hanyu, H. Ohno

58th Annual Conference on Magnetism & Magnetic Materials Abstract　2013/11
Fabrication of a Perpendicular-MTJ-Based Compact Nonvolatile Programmable Switch Using Shared-Write-Control-Transistor Structure Peer-reviewed

D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

Abst. 58th Annual Conference on Magnetism and Magnetic Materials　233　2013/11
Spintronics-based integrated circuits and contribution to energy saving society

Hideo Ohno, Takahiro Hanyu, Shoji Ikeda, Tetsuo Endoh, Yasuo Ando, Naoki Kasai

Journal of the Institute of Electronics, Information and Communication Engineers　96　(10)　771-775　2013/10

ISSN： 0913-5693
Probabilistic Search Schemes for High-Speed Low-Power Content-Addressable Memories Peer-reviewed

N. Onizawa, S. Matsunaga, V. C. Gaudet, W. J. Gross, T. Hanyu

2013 International Conference on Analog VLSI Circuit　100-105　2013/10
スピントロニクスを用いた集積回路と省エネ社会への貢献(<特別小特集>東北から明るい未来を創るICT技術) Peer-reviewed

大野英男, 遠藤哲郎, 羽生貴弘, 安藤康夫, 笠井直記, 池田正二

電子情報通信学会誌　96　(10)　771-775　2013/10/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5693
Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications Peer-reviewed

R. Nebashi, Y. Tsuji, H. Honjo, N. Sakimura, A. Morioka, K. Tokutome, S. Miura, S. Fukami, M. Yamanouchi, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi

2013 International Conference on Solid State Devices and Materials (SSDM)　M-8-3　1102-1103　2013/09/24
Strategy of STT-MRAM Cell Design and Its Power Gating Technique for Low-Voltage and Low-Power Cache Memories Peer-reviewed

Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

2013 International Conference on Solid State Devices and Materials (SSDM)　M-7-1　1090-1091　2013/09/24
Studies on Selective Devices for Spin-Transfer-Torque Magnetic Tunnel Junctions Peer-reviewed

Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

2013 International Conference on Solid State Devices and Materials (SSDM)　M-8-4　1104-1105　2013/09/24
A 4x4 Nonvolatile Multiplier Using Novel MTJ-CMOS Hybrid Latch and Flip-Flop Peer-reviewed

Takashi Ohsawa, Sadahiro Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

2013 International Conference on Solid State Devices and Materials (SSDM)　M-6-3　1086-1087　2013/09/24
Wide Operational Margin Capability of 1kbit STT-MRAM Array Chip with 1-PMOS and 1-Bottom-Pin-MTJ Type Cell Peer-reviewed

Hiroki Koike, Takashi Ohsawa, Sadahiro Miura, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

2013 International Conference on Solid State Devices and Materials (SSDM)　M-7-3　1094-1095　2013/09/24
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links Peer-reviewed

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E96D　(9)　1952-1961　2013/09

DOI： 10.1587/transinf.E96.D.1952 　

ISSN： 0916-8532

eISSN： 1745-1361
Design of a Three-Terminal MTJ-Based Nonvolatile Logic Element with a 2-ns 64-Bit-Parallel Reconfiguration Capability Peer-reviewed

D. Suzuki, M. Natsui, A. Mochizuki, T. Hanyu

Ext. Abstr. 2013 Int. Conf. Solid-State Devices and Materials　386-387　2013/09
IEEE Journal of Solid-State Circuits Peer-reviewed

T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

A 1 Mb nonvolatile embedded memory using 4T2MTJ cell with 32 b fine-grained power gating scheme　48　(6)　1511-1520　2013/06/22
A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories Peer-reviewed

Takashi Ohsawa, Sadahiro Miura, Keizo Kinoshita, Hiroaki Honjo, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

2013 Symposium on VLSI Technology (VLSIT) & 2013 Symposium on VLSI Cricuit (VLSIC) Digest of Technical Papers　C110-C111　2013/06/12
A Model Reflecting Preheat Effect by Two-step Writing Technique for High Speed and Stable STT-MRAM Peer-reviewed

Yasuhiro Yoshida, Hiroki Koike, Masakazu Muraguchi, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

16th International Workshop on Computational Electronics (IWCE)　248-249　2013/06/04
Fabrication of a 99%-Energy-Less Nonvolatile Multi-Functional CAM Chip Using Hierarchical Power Gating for a Massively-Parallel Full-Text-Search Engine Peer-reviewed

S. Matsunaga, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, H. Sato, S. Fukami, M. Natsui, A. Mochizuki, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

2013 Symposium on VLSI Circuits Digest of Technical Papers　106-107　2013/06
Challenge of Nonvolatile Logic-in-Memory Architecture Towards Cool LSI Chips Invited

T. Hanyu

2013 Spintronics Workshop on LSI　8　2013/06
A 1Mb STT-MRAM with Zero Array Standby Power and 1.5ns Quick Wake-up by 8b Fine-Grained Power Gating Peer-reviewed

Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno, Tetuso Endoh

5th IEEE International Memory Workshop (IMW)　80-83　2013/05/26

DOI： 10.1109/IMW.2013.6582103 　
制御情報共有化に基づく非同期細粒度パワーゲーティング技術とそのオンチップルータへの応用 Peer-reviewed

松本敦, 河野宇朗, 鬼沢直哉, 羽生貴弘

電子情報通信学会論文誌　96　(5)　73-84　2013/05
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
制御情報共有化に基づく非同期細粒度パワーゲーティング技術とそのオンチップルータへの応用 Peer-reviewed

松本敦, 河野宇朗, 鬼沢直哉, 羽生貴弘

信学論JD　J96-C　(5)　73-84　2013/05
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
スピン論理集積回路における基本ゲートの高信頼化技術 Peer-reviewed

辻幸秀, 根橋竜介, 崎村昇, 森岡あゆ香, 本庄弘明, 徳留圭一, 三浦貞彦, 鈴木哲広, 深見俊輔, 木下啓藏, 羽生貴弘, 遠藤哲郎, 笠井直記, 大野英男, 杉林

信学技報,　113　(1)　41-46　2013/04/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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Implementing redundancy within a Spintronis Primitive Gata (SPG) using multi-terminal DWM cells ensures high reliability for the logic use. The overheads of this technique, such as cell area, read margin, and write power consumption, have also been investigated.
4T-2MTJセル構造に基づく不揮発TCAMチップの実現 Peer-reviewed

松永翔雲, 三浦貞彦, 本庄弘明, 木下啓蔵, 池田正二, 遠藤哲郎, 大野英男, 羽生貴弘

信学技報,　113　(1)　33-38　2013/04/01
A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure Peer-reviewed

Daisuke Suzuki, Yuhui Lin, Masanori Natsui, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　52　(4)　04CM04-1-04CM04-6　2013/04

DOI： 10.7567/JJAP.52.04CM04 　

ISSN： 0021-4922

eISSN： 1347-4065
不揮発性STT-MRAMの開発と今後の展望 Invited

遠藤哲郎, 大澤隆, 伊賀文崇, 池田正二, 羽生貴弘, 大野英男

応用物理学会・特別シンポジウム　2013/03/01
Nonvolatile Look-up Table Circuit Using Three-Terminal MTJ-Based Logic-in-Memory Structure

D. Suzuki, T. Hanyu

The 3rd CSIS International Symposium on Spintronics-based VLSIs　32　2013/02
Design of Low-Energy Nonvolatile TCAM Using Logic-in-Memory Architecture

S. Matsunaga, T. Hanyu

The 3rd CSIS International Symposium on Spintronics-based VLSIs　35　2013/02
Two-step writing method for STT-MTJ to improve switching probability and write-speed Peer-reviewed

Fumitaka Iga, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

The 3nd CSIS International Symposium on Spintronics-based VLSIs　2013/01/31
A fine-grained power gating architecture for MTJ-based embedded memories Peer-reviewed

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

The 3nd CSIS International Symposium on Spintronics-based VLSIs　2013/01/31
600MHz Nonvolatile Latch Based on a New MTJ/CMOS Hybrid Circuit Concept Peer-reviewed

Tetsuo Endoh, Shuta Togashi, Fumitaka Iga, Yasuhiro Yoshida, Takashi Ohsawa, Hiroki Koike, Shunsuke Fukami, Shoji Ikeda, Naoki Kasai, Noboru Sakimura, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

The 3nd CSIS International Symposium on Spintronics-based VLSIs　2013/01/31
省エネシステムのためのSTT-MRAMと、そのロジック応用 Invited

遠藤哲郎, 小池洋紀, 大澤隆, 羽生貴弘, 笠井直記, 大野英男

ゲートスタック研究会　2013/01/25
MRAMの最新動向 Invited

遠藤哲郎, 池田正二, 羽生貴弘, 笠井直記, 大野英男

電子ジャーナル,　2013/01/11
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI Peer-reviewed

Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi

Proceedings - IEEE International Symposium on Circuits and Systems　105-108　2013

DOI： 10.1109/ISCAS.2013.6571793 　

ISSN： 0271-4310
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices Peer-reviewed

Masanori Natsui, Takahiro Hanyu

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　21　(5-6)　597-608　2013

ISSN： 1542-3980
Nonvolatile Logic-in-Memory Array Processor in 90nm MTJ/MOS Achieving 75% Leakage Reduction Using Cycle-Based Power Gating Peer-reviewed

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

2013 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)　56　194-+　2013

DOI： 10.1109/ISSCC.2013.6487696 　

ISSN： 0193-6530
High-throughput CAM based on a synchronous overlapped search scheme Peer-reviewed

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

IEICE ELECTRONICS EXPRESS　10　(7)　20130148-1-20130148-9　2013

DOI： 10.1587/elex.10.20130148 　

ISSN： 1349-2543
High-throughput CAM based on a synchronous overlapped search scheme Peer-reviewed

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

IEICE ELECTRONICS EXPRESS　10　(7)　20130148　2013

DOI： 10.1587/elex.10.20130148 　

ISSN： 1349-2543
MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI Peer-reviewed

Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)　105-108　2013

DOI： 10.1109/ISCAS.2013.6571793 　

ISSN： 0271-4302
Challenge of MTJ/MOS-Hybrid Logic-in-Memory Architecture for Nonvolatile VLSI Processor Invited Peer-reviewed

Takahiro Hanyu

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)　117-120　2013

DOI： 10.1109/ISCAS.2013.6571796 　

ISSN： 0271-4302
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems Peer-reviewed

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

2013 IEEE 19TH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC)　8-15　2013

DOI： 10.1109/ASYNC.2013.16 　

ISSN： 1522-8681
Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications Peer-reviewed

Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu

2013 IEEE 43RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2013)　146-151　2013

DOI： 10.1109/ISMVL.2013.23 　

ISSN： 0195-623X
Lowering error floors in stochastic decoding of ldpc codes based on wire-delay dependent asynchronous updating Peer-reviewed

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

Proceedings of The International Symposium on Multiple-Valued Logic　254-259　2013

DOI： 10.1109/ISMVL.2013.35 　

ISSN： 0195-623X
Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information Peer-reviewed

Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto

2013 IEEE 43RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2013)　266-271　2013

DOI： 10.1109/ISMVL.2013.11 　

ISSN： 0195-623X
Design of a Compact Nonvolatile Lookup-Table Circuit Using Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure Peer-reviewed

D. Suzuki, Y. Lin, M. Natsui, T. Hanyu

Ext. Abstr. Solid-State Devices and Materials (SSDM)　392-393　2012/09
MTJ based Non Volatile Logic for Ultimate Power Management Invited Peer-reviewed

Tetsuo Endoh, Takashi Ohsawa, Takahiro Hanyu, Hideo Ohno

the 19th International Conference on Magnetism with Strongly Correlated Electron Systems (ICM2012 with SCES)　Session BI02　5-7　2012/06/26
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling Peer-reviewed

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E95A　(6)　1018-1029　2012/06

DOI： 10.1587/transfun.E95.A.1018 　

ISSN： 1745-1337
Challenge of Nonvolatile Logic-in-Memory Architecture Towards Cool LSI Chips Invited

Takahiro Hanyu

2012 Spintronics Workshop on LSI　8-8　2012/06
MTJ based non volatile SRAM and low power non volatile logic-in-memory architecture Invited Peer-reviewed

Tetsuo Endoh, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Naoki Kasai, Hideo Ohno

IEEE International Magnetics Conference (INTERMAG2012)　HB-06-HB-06　2012/05/09
3端子磁壁移動型セルを用いた不揮発性コンテントアドレッサブルメモリ Peer-reviewed

根橋竜介, 崎村昇, 辻幸秀, 深見俊輔, 本庄弘明, 齊藤信作, 三浦貞彦, 石綿延行, 木下啓蔵, 羽生貴弘, 遠藤哲郎, 笠井直記, 大野英男, 杉林直彦

信学技報　112　(15)　49-54　2012/04/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A 5-ns search operation of a non-volatile content addressable memory was demonstrated. The CAM macro, with a capacity of 16 kb, was fabricated using 90-nm CMOS and domain wall (DW) motion processes. The operating speed was comparable to that of SRAM-based CAM.
Design of a Compact Nonvolatile Four-Input Logic Element Using a Magnetic Tunnel Junction and Metal-Oxide-Semiconductor Hybrid Structure Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　51　(4)　04DM02-1-04DM02-5　2012/04

DOI： 10.1143/JJAP.51.04DM02 　

ISSN： 0021-4922

eISSN： 1347-4065
Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions Peer-reviewed

D. Suzuki, M. Natsui, T. Endoh, H. Ohno, T. Hanyu

JOURNAL OF APPLIED PHYSICS　111　(7)　07E318-1-07E318-3　2012/04

DOI： 10.1063/1.3672411 　

ISSN： 0021-8979

eISSN： 1089-7550
Design of a 270ps-access 7-transistor/2-magnetic-tunnel-junction cell circuit for a high-speed-search nonvolatile ternary content-addressable memory Peer-reviewed

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

JOURNAL OF APPLIED PHYSICS　111　(7)　07E336-1-07E336-3　2012/04

DOI： 10.1063/1.3677875 　

ISSN： 0021-8979

eISSN： 1089-7550
Nonvolatile Logic-in-Memory Architecture Using an MTJ/MOS-Hybrid Structure and Its Applications Invited

Takahiro Hanyu

IEEE Symposium on Low-Power and High-Speed Chips (Cool Chips XV)　11-1-11-21　2012/04
Proposal of New MTJ-Based Nonvolatile Memories Invited Peer-reviewed

T. Ohsawa, H. Koike, T. Hanyu, S. Ikeda, H. Ohno, T. Endoh

The 2nd CSIS International Symposium on Spintronics-based VLSIs　F6　23-23　2012/02/02
A Content Adddressable Memory Using Three-Terminal Magnetic Domain Wall Motion Cells Invited Peer-reviewed

R. Nebashi, N. Sakimura, Y Tsuji, S. Fukami, H. Honjo, S. Saito, S.Miura, N.Ishiwata, K. kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi

The 2nd CSIS International Symposium on Spintronics-based VLSIs　F7　24-24　2012/02/02
High-Density Ternary Content-Addressable Memory Using MTJ-Based Nonvolatile Logic-in-Memory Architecture

Takahiro Hanyu

The 2nd CSIS International Symposium on Spintronics-based VLSIs and the 8th RIEC International Workshop on Spintronics　25-25　2012/02
Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory Peer-reviewed

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　51　(2)　02BM06-1-02BM06-5　2012/02

DOI： 10.1143/JJAP.51.02BM06 　

ISSN： 0021-4922
High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction Peer-reviewed

Takashi Ohsawa, Fumitaka Iga, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

JAPANESE JOURNAL OF APPLIED PHYSICS　51　(2)　02BD01-1-02BD01-6　2012/02

DOI： 10.1143/JJAP.51.02BD01 　

ISSN： 0021-4922
Time-Resolved Switching Characteristic in Magnetic Tunnel Junction with Spin Transfer Torque Write Scheme Peer-reviewed

Fumitaka Iga, Yasuhiro Yoshida, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

JAPANESE JOURNAL OF APPLIED PHYSICS　51　(2)　02BM02-1-02BM02-5　2012/02

DOI： 10.1143/JJAP.51.02BM02 　

ISSN： 0021-4922
遅延情報データベースに基づく高速・高精度非同期NoC設計・検証CADに関する一考察

渡邉友馬, 松本敦, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2012　224-224　2012
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2012.0_224 　
低スイッチング電力基本論理ゲートの構成に関する一考察

樫内清弘, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2012　225-225　2012
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2012.0_225 　
Design of an MTJ-Based Variation-Resilient Basic Gate of Differential Logic

Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan　2012　7-7　2012
Publisher: Organizing Committee of Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, Japan
DOI： 10.11528/tsjc.2012.0_7 　
Clockless stochasic decoding of low-density parity-check codes Peer-reviewed

N. Onizawa, W. J. Gross, T. Hanyu, V. C. Gaudet

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation　143-148　2012

DOI： 10.1109/SiPS.2012.53 　

ISSN： 1520-6130
High-speed simulator including accurate MTJ models for spintronics integrated circuit design Peer-reviewed

Sakimura, N.a, Nebashi, R, Tsuji, Y, Honjo, H.a, Sugibayashi, T, Koike, H, Ohsawa, T, Fukami, S, Hanyu, T, Ohno, H, Endoh, T

ISCAS - IEEE Int. Symp. Circuits Syst.　6271663-1974　2012

DOI： 10.1109/ISCAS.2012.6271663 　

ISSN： 0271-4302
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique Peer-reviewed

Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　19　(1-3)　219-231　2012

ISSN： 1542-3980
Implementation of a Perpendicular MTJ-Based Read-Disturb-Tolerant 2T-2R Nonvolatile TCAM Based on a Reversed Current Reading Scheme Peer-reviewed

S. Matsunaga, M. Natsui, S. Ikeda, K. Miura, T. Endoh, H. Ohno, T. Hanyu

2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)　475-476　2012

DOI： 10.1109/ASPDAC.2012.6164998 　

ISSN： 2153-6961
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism Peer-reviewed

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu

2012 18TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS (ASYNC)　41-48　2012

DOI： 10.1109/ASYNC.2012.25 　

ISSN： 1522-8681
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links Peer-reviewed

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　13-18　2012

DOI： 10.1109/ISMVL.2012.51 　

ISSN： 0195-623X
Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes Peer-reviewed

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross

2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　92-97　2012

DOI： 10.1109/ISMVL.2012.35 　

ISSN： 0195-623X
Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM Peer-reviewed

Shoun Matsunaga, Takahiro Hanyu

2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　98-103　2012

DOI： 10.1109/ISMVL.2012.67 　

ISSN： 0195-623X
Process-Variation-Resilient OTA Using MTJ-Based Multi-Level Resistance Control Peer-reviewed

Masanori Natsui, Takaaki Nagashima, Takahiro Hanyu

2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　214-219　2012

DOI： 10.1109/ISMVL.2012.52 　

ISSN： 0195-623X
Variation-Resilient Current-Mode Logic Circuit Design Using MTJ Devices Peer-reviewed

Youngkeun Kim, Masanori Natsui, Takahiro Hanyu

2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012)　2705-2708　2012

DOI： 10.1109/ISCAS.2012.6271866 　

ISSN： 0271-4302
A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture Peer-reviewed

Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEEE Symposium on VLSI Circuits, Digest of Technical Papers　J-C6.2　44-45　2012

DOI： 10.1109/VLSIC.2012.6243781 　
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times Peer-reviewed

T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

IEEE Symposium on VLSI Circuits, Digest of Technical Papers　J-C6.3　46-47　2012

DOI： 10.1109/VLSIC.2012.6243782 　
Spintronics primitive gate with high error correction efficiency 6(P error) 2 for logic-in memory architecture Peer-reviewed

Y. Tsuji, R. Nebashi, N. Sakimura, A. Morioka, H. Honjo, K. Tokutome, S. Miura, T. Suzuki, S. Fukami, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi

Digest of Technical Papers - Symposium on VLSI Technology　T7.4　63-64　2012

DOI： 10.1109/VLSIT.2012.6242462 　

ISSN： 0743-1562
Restructuring of memory hierarchy in computing system with spintronics-based technologies Invited

Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno

Digest of Technical Papers - Symposium on VLSI Technology　T10.3　89-90　2012

DOI： 10.1109/VLSIT.2012.6242475 　

ISSN： 0743-1562
Scalable Serial-Configuration Scheme for MTJ/MOS-Hybrid Variation-Resilient VLSI System Peer-reviewed

Masanori Natsui, Takahiro Hanyu

2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　97-100　2012

DOI： 10.1109/NEWCAS.2012.6328965 　

ISSN： 2472-467X
Fine-Grained Power-Gating Scheme of a Nonvolatile Logic-in-Memory Circuit for Low-Power Motion-Vector Extraction Peer-reviewed

Magdalena Sihotang, Shoun Matsunaga, Takahiro Hanyu

2012 IEEE 10TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS)　485-488　2012

DOI： 10.1109/NEWCAS.2012.6329062 　

ISSN： 2472-467X
Area-Efficient LUT Circuit Design Based on Asymmetry of MTJ's Current Switching for a Nonvolatile FPGA Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu

2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)　334-337　2012

DOI： 10.1109/MWSCAS.2012.6292025 　

ISSN： 1548-3746
Building Blocks to Use in Innovative Non-Volatile FPGA Architecture Based on MTJs. Peer-reviewed

Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki

2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI)　302-307　2012

DOI： 10.1109/ISVLSI.2012.21 　
CLOCKLESS STOCHASIC DECODING OF LOW-DENSITY PARITY-CHECK CODES Peer-reviewed

N. Onizawa, W. J. Gross, T. Hanyu, V. C. Gaudet

2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS)　143-148　2012

DOI： 10.1109/SiPS.2012.53 　

ISSN： 2162-3562
Multi-chip NoCs for automotive applications Peer-reviewed

Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC　105-110　2012

DOI： 10.1109/PRDC.2012.20 　

ISSN： 1541-0110
Design of a 270ps-Access 7T-2MTJ-Cell Nonvolatile Ternary Content-Addressable Memory Peer-reviewed

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

56th Annual Conference on Magnetism and Magnetic Materials(MMM2011)　479-479　2011/11
50%-Transistor-Less Standby-Power-Free 6-input LUT Circuit Using Redundant MTJ-Based Nonvolatile Logic-in-Memory Architecture Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

56th Annual Conference on Magnetism and Magnetic Materials(MMM2011)　480-480　2011/11
MTJ-Based Optimal Vth-Tuning Technique for a Process-Variation-Aware VLSI processor Peer-reviewed

Masanori Natsui, Kim Yong Kun, Takahiro Hanyu

56th Annual Conference on Magnetism and Magnetic Materials(MMM2011)　480-481　2011/11
MTJ-based Nonvolatile Logic-in-Memory Architecture and Its Application Invited

Takahiro Hanyu

The 11th Non-Volatile Memory Technology Symposium (NVMTS 2011)　81-82　2011/11
Evaluation of Vth-Variation Effect on Multiple-Valued Current-Mode Circuits

Kiyohiro Kashiuchi, Masanori Natsui, Takahiro Hanyu

Japan-China-Korea Conference on Electronics & Communications 2011 (GWEI''11)　157-157　2011/10
Delay-Aware Model-Based Accurate Simulator for Asynchronous NoC Design

Yuma Watanabe, Atsushi Matsumoto, Takahiro Hanyu

Japan-China-Korea Conference on Electronics & Communications 2011 (GWEI''11)　181-181　2011/10
Studies on Static Noise Margin and Scalability for Low-Power and High-Density Nonvolatile SRAM using Spin -Transfer -Torque (STT) MTJs Peer-reviewed

Takashi Ohsawa, Fumitaka Iga, Shoji Ikeda, Takahiro, Hanyu, Hideo Ohno, Testuo Endoh

2011 International Conference on Solid State Devices and Materials (SSDM2011)　959-960　2011/09/28
Novel 2step Writing Method for STT-RAM to Improve Switching Probability and Write Speed Peer-reviewed

Fumitaka. Iga, Yasuhiko Suzuki, Takashi Ohsawa, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

2011 International Conference on Solid State Devices and Materials (SSDM2011)　963-964　2011/09/28
Scalable STT RAM Technology for Low Power Systems Invited Peer-reviewed

T. Endoh, S. Ikeda, T Hanyu, N. Kasai, H. Ohno

Samsung Semiconductor Future Technology Forum 2011　2011/09/23
Sub-20nm STT-MRAM as a replacement for DRAM:Its Challenges and Opportunities Invited Peer-reviewed

T. Endoh, S. Ikeda, T Hanyu, N. Kasai, H. Ohno

Samsung Semiconductor Future Technology Forum 2011　2011/09/23
A Compact Nonvolatile Logic Element Using an MTJ/MOS-Hybrid Structure Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Hideo Ohno, Takahiro Hanyu

2011 International Conference on Solid State Devices and Materials (SSDM)　1464-1465　2011/09
High-Speed-Search Nonvolatile TCAM Using MTJ Devices Peer-reviewed

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

2011 International Conference on Solid State Devices and Materials (SSDM)　454-455　2011/09
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding Peer-reviewed

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS　58　(8)　1933-1943　2011/08

DOI： 10.1109/TCSI.2011.2107271 　

ISSN： 1549-8328
Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device Peer-reviewed

Satoru Hanzawa, Takahiro Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E94C　(8)　1302-1310　2011/08

DOI： 10.1587/transele.E94.C.1302 　

ISSN： 1745-1353
Time-Dependent Switching Characteristics of Magnetic Tunnel Junction (MTJ) Peer-reviewed

Y. Yoshida, F. Iga, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2011)　2B.7　167-170　2011/06/29
Study of the Resistive Switching in CoFeB/MgO/CoFeB Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuit Peer-reviewed

F. Iga, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh

2011 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2011)　2B.8　171-174　2011/06/29
Design and Fabrication of a One-Transistor/One-Resistor Nonvolatile Binary Content-Addressable Memory Using Perpendicular Magnetic Tunnel Junction Devices with a Fine-Grained Power-Gating Scheme Peer-reviewed

Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　50　(6)　063004-1-063004-7　2011/06

DOI： 10.1143/JJAP.50.063004 　

ISSN： 0021-4922
Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control Peer-reviewed

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Shunsuke Fukami, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

2011 Symposium on VLSI Circuits, Digest of Technical Papers　298-299　2011/06
A Content Addressable Memory Using Magnetic Domain Wall Motion Cells Peer-reviewed

R. Nebashi, N. Sakimura, Y. Tsuji, S. Fukami, H. Honjo, S. Saito, S. Miura, N. Ishiwata, K. Kinoshita, T. Hanyu, T. Endoh, N. Kasai, H. Ohno, T. Sugibayashi

2011 Symposium on VLSI Circuits, Digest of Technical Papers　300-301　2011/06
不揮発性ロジックインメモリアーキテクチャが拓く新概念VLSI設計パラダイム Invited

夏井雅典, 羽生貴弘

LSIとシステムのワークショップ2011　65-70　2011/05
不揮発性ロジックインメモリアーキテクチャが拓く新コンピューティングパラダイムの展望 Invited

夏井雅典, 羽生貴弘

第58回応用物理学関係連合講演会　58th　78-78　2011/03
Nonvolatile Computer Systems and Memory Hierarchy Transformation with STT RAM Technology Invited Peer-reviewed

Tetsuo Endoh, S. Ikeda, T. Hanyu, N. Kasai, H. Ohno

The 1st CSIS International Symposium on Spintronics-based VLSIs and The 7th RIEC International Workshop on Spintronisc　17　2011/02/03
不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討

キムヨンクン, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2011　269-269　2011
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2011.0_269 　
MTJ素子を用いた待機電力フリー不揮発ロジック基本ゲートの構成

マグダレナシホタン, 松永翔雲, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2011　266-266　2011
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2011.0_266 　
磁壁移動素子を用いた不揮発性論理回路の構成

鈴木大輔, 林玉輝, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2011　267-267　2011
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2011.0_267 　
可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討

長嶋孝晃, 夏井雅典, 桝井昇一, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2011　268-268　2011
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2011.0_268 　
Accurate asynchronous network-on-chip simulation based on a delay-aware model Peer-reviewed

Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

Lecture Notes in Electrical Engineering　105　17-30　2011

DOI： 10.1007/978-94-007-1488-5_2 　

ISSN： 1876-1100 1876-1119
Adjacent-state monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system Peer-reviewed

Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

Proceedings - IEEE International Symposium on Circuits and Systems　2067-2070　2011

DOI： 10.1109/ISCAS.2011.5938004 　

ISSN： 0271-4310
Three-terminal domain-wall cell architectures Peer-reviewed

N. Ishiwata, S. Fukami, S. Saitho, R. Nebashi, N. Sakimura, H. Honjo, S. Miura, T. Sugibayashi, Y. Thuji, M. Murahata, H. Ohno, T. Endoh, T. Hanyu, N. Kasai

International Magnetics Conference 2011 abstract　2011
Interconnect-Fault-Resilient Delay-Insensitive Asynchronous Communication Link Based on Current-Flow Monitoring Peer-reviewed

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)　776-781　2011

ISSN： 1530-1591
Adjacent-State Monitoring Based Fine-Grained Power-Gating Scheme for a Low-Power Asynchronous Pipelined System Peer-reviewed

Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)　2067-2070　2011

DOI： 10.1109/ISCAS.2011.5938004 　

ISSN： 0271-4302
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme Peer-reviewed

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu

2011 41ST IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　99-104　2011

DOI： 10.1109/ISMVL.2011.41 　

ISSN： 0195-623X
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links Peer-reviewed

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

2011 41ST IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　236-241　2011

DOI： 10.1109/ISMVL.2011.30 　

ISSN： 0195-623X
A 600MHz MTJ-Based Nonvolatile Latch Making Use of Incubation Time in MTJ Switching Peer-reviewed

T. Endoh, S. Togashi, F. Iga, Y. Yoshida, T. Ohsawa, H. Koike, S. Fukami, S. Ikeda, N. Kasai, N. Sakimura, T. Hanyu, H. Ohno

2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)　4.3.1-4.3.2　2011

DOI： 10.1109/IEDM.2011.6131487 　
Magnetic Tunnel Junction for Nonvolatile CMOS Logic Invited Peer-reviewed

Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu, Naoki Kasai, Shoji Ikeda

2010 International Electron Devices Meeting　9.4.1-9.4.4　2010/12/06

DOI： 10.1109/IEDM.2010.5703329 　
Design of a Process-Variation-Aware Nonvolatile MTJ-Based Lookup-Table Circuit Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Hideo Ohno, Takahiro Hanyu

2010 International Conference on Solid-State Devices and Materials, Workshop　1146-1147　2010/09
Power-Aware Bit-Serial Binary Content-Addressable Memory Using Magnetic-Tunnel-Junction-Based Fine-Grained Power-Gating Scheme Peer-reviewed

Shoun Matsunaga, Masanori Natsui, Hideo Ohno, Takahiro Hanyu

2010 International Conference on Solid-State Devices and Materials, Workshop　565-566　2010/09
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme Peer-reviewed

Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E93D　(8)　2080-2088　2010/08

DOI： 10.1587/transinf.E93.D.2080 　

ISSN： 0916-8532
Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link Peer-reviewed

Naoya Onizawa, Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E93D　(8)　2089-2099　2010/08

DOI： 10.1587/transinf.E93.D.2089 　

ISSN： 1745-1361
Logic-in-Memory Architecture Using Si-MOSFETs and Magnetic Tunnel Junctions Invited

Takahiro Hanyu

6th International Conference on Physics and Applications of Spin Related Phenomena in Semiconductors (PASPS-VI)　176-176　2010/08
Transient characteristic of fabricated Magnetic Tunnel Junction (MTJ) programmed with CMOS circuit Peer-reviewed

M. Kamiyanagi, F. Iga, S. Ikeda, K. Miura, J. Hayakawa, H. Hasegawa, T. Hanyu, H. Ohno, T. Endoh

IEICE Transacions on Electronics　E93-C　(5)　602-607　2010/05
Publisher: The Institute of Electronics, Information and Communication Engineers
DOI： 10.1587/transele.E93.C.602 　

ISSN： 0916-8524

More details Close

In this paper, it is shown that our fabricated MTJ of 60×180nm², which is connected to the MOSFET in series by 3 levels via and 3 levels metal line, can dynamically operate with the programming current driven by 0.14µm CMOSFET. In our measurement of transient characteristic of fabricated MTJ, the pulse current, which is generated by the MOSFET with an applied pulse voltage of 1.5V to its gate, injected to the fabricated MTJ connected to the MOSFET in series. By using the current measurement technique flowing in MTJ with sampling period of 10nsec, for the first time, we succeeded in monitor that the transition speed of the resistance change of 60×180nm² MTJ is less than 30ns with its programming current of 500µA and the resistance change of 1.2kΩ.
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-end Metal Line of CMOS Circuits Peer-reviewed

F. Iga, M. Kamiyanagi, S. Ikeda, K. Miura, J. Hayakawa, H. Hasegawa, T. Hanyu, H. Ohno, T. Endoh

IEICE Transacions on Electronics　E93-C　(5)　608-613　2010/05
Publisher: The Institute of Electronics, Information and Communication Engineers
DOI： 10.1587/transele.E93.C.608 　

ISSN： 0916-8524

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In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/1-poly Gate 0.14µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60×180nm² achieves a large change in resistance of 3.52kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.
Process-Variation-Aware VLSI Design Using an Emerging Functional Devices and Its Impact

M. Natsui, T. Hanyu

Booklet of the 19th International Workshop on Post-Binary ULSI Systems　20-25　2010/05
The performance of magnetic tunnel junction integrated on the back-end metal line of complimentary metal-oxide-semiconductor circuits Peer-reviewed

T. Endoh, F. Iga, S. Ikeda, K. Miura, J. Hayakawa, M. Kamiyanagi, H. Hasegawa, T. Hanyu, H. Ohno

Japanese Journal of Applied Physics　49　(4)　04DM06-(1)-04DM06-(5)　2010/04/20
Publisher: The Japan Society of Applied Physics
DOI： 10.1143/JJAP.49.04DM06 　

ISSN： 0021-4922

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In this paper, we have described the complementary metal–oxide–semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3 nm with 0.14 μm CMOS process and $60 \times 180$ nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 k$\Omega$ (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.
MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture and Its Impact Invited

T. Hanyu

28th IEEE VLSI Test Symposium　258-258　2010/04
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning Peer-reviewed

Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　18　(3)　482-489　2010/03

DOI： 10.1109/TVLSI.2008.2011360 　

ISSN： 1063-8210
TMRデバイスを用いたしきい値変動補償を有する電流モード多値回路の構成 Peer-reviewed

廣崎旭宏, 松本敦, 羽生貴弘

電子情報通信学会論文誌D　J93-D　(1)　10-19　2010/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1880-4535
MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture and Its Applications Invited

T. Hanyu

11th Joint MMM-Intermag Conf.　FZ-02　1533-1533　2010/01
Fine-Grained Power-Gating Scheme of a Metal-Oxide-Semiconductor and Magnetic-Tunnel-Junction-Hybrid Bit-Serial Ternary Content-Addressable Memory Peer-reviewed

Shoun Matsunaga, Masanori Natsui, Kimiyuki Hiyama, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

JAPANESE JOURNAL OF APPLIED PHYSICS　49　(4)　04DM05-1-04DM05-5　2010

DOI： 10.1143/JJAP.49.04DM05 　

ISSN： 0021-4922
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control Peer-reviewed

Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu

40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010　235-240　2010

DOI： 10.1109/ISMVL.2010.51 　

ISSN： 0195-623X
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control Peer-reviewed

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010　211-216　2010

DOI： 10.1109/ISMVL.2010.47 　

ISSN： 0195-623X
High-Throughput Protocol Converter Based on an Independent Encoding/Decoding Scheme for Asynchronous Network-on-Chip Peer-reviewed

Naoya Onizawa, Takahiro Hanyu

2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS　157-160　2010

DOI： 10.1109/ISCAS.2010.5538027 　

ISSN： 0271-4302
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model Peer-reviewed

Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010)　357-362　2010

DOI： 10.1109/ISVLSI.2010.45 　

ISSN： 2159-3469

eISSN： 2159-3477
Ultra-Low Power IC Technology Integrated with Innovative Materials Invited

T. Hanyu

Proc. of International Conference on Solid State Devices and Materials　1-9　2009/10
MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture Invited

Masanori Natsui, Takahiro Hanyu

Proc. of International Conference on Solid State Devices and Materials　1398-1399　2009/10
Fine-Grain Power-Gating Scheme of a CMOS/MTJ-Hybrid Bit-Serial Ternary Content-Addressable Memory Peer-reviewed

Shown Matsunaga, Atsushi Matsumoto, Masanori Natusi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proc. of International Conference on Solid State Devices and Materials　1382-1383　2009/10
A MOS/MTJ-Hybrid Circuit with Nonvolatile Logic-in-Memory Architecture Invited

T. Hanyu

Proc. of Advances in Magnetic Nanostructures　21-21　2009/10
TMR ロジックに基づくルックアップテーブル回路とその瞬時復帰可能FPGA への応用 Invited Peer-reviewed

鈴木大輔, 夏井雅典, 羽生貴弘

電子情報通信学会論文誌C　J92-C　(7)　233-240　2009/07
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving Invited Peer-reviewed

Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet

IEICE TRANSACTIONS ON ELECTRONICS　E92C　(6)　867-874　2009/06

DOI： 10.1587/transele.E92.C.867 　

ISSN： 1745-1353
双方向シングルトラック非同期転送方式に基づく高速・低電力LDPCデコーダLSIの構成 Invited

鬼沢直哉, 羽生貴弘, Vincent Gaudet

LSIとシステムのワークショップ2009講演論文集　354-356　2009/05
MTJ・CMOSハイブリッド回路に基づく低電力・高信頼LSI技術 Invited

夏井雅典, 羽生貴弘

LSIとシステムのワークショップ2009講演論文集　351-353　2009/05
Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices Invited Peer-reviewed

Shoun Matsunaga, Kimiyuki Hiyama, Atsushi Matsumoto, Shoji Ikeda, Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

APPLIED PHYSICS EXPRESS　2　(2)　023004-1-023004-3　2009/02

DOI： 10.1143/APEX.2.023004 　

ISSN： 1882-0778
MTJ-Based Nonvolatile Logic-in-Memory Circuit, Future Prospects and Issues Peer-reviewed

Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3　433-+　2009

ISSN： 1530-1591
高信頼電流モード多値集積回路技術とその応用 Invited

白濱弘勝, 永井亮, 羽生貴弘

電子情報通信学会「多値論理とその応用」第二種研究会技術報告　MVL-09　1-6　2009/01
多値データ転送に基づく高性能NoCの構成 Invited

松本敦, 羽生貴弘

電子情報通信学会「多値論理とその応用」第二種研究会技術報告　MVL-09　24-27　2009/01
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control Invited Peer-reviewed

Naoya Onizawa, Takahiro Hanyu

ISMVL: 2009 39TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　36-41　2009

DOI： 10.1109/ISMVL.2009.44 　
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System Invited Peer-reviewed

Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu

ISMVL: 2009 39TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　60-65　2009

DOI： 10.1109/ISMVL.2009.52 　
High-Performance Asynchronous Intra-Chip Communication Link Based on a Multiple-Valued Current-Mode Single-Track Scheme Invited Peer-reviewed

Yo Ohtake, Naoya Onizawa, Takahiro Hanyu

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5　1000-1003　2009

DOI： 10.1109/ISCAS.2009.5117927 　
Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array Invited Peer-reviewed

Daisuke Suzuki, Masanori Natsui, Shoji Ikeda, Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS　80-+　2009
TMR Logic: Nonvolatile Logic Circuit Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Takahiro Hanyu

PRiME2008 Meeting Abstracts　2105　2008/10
MTJ-Based Nonvolatile Logic-in-Memory Circuit Invited

Takahiro Hanyu, Shoun Matsunaga

CNSI-RIEC Workshop on Nanoelectronics, Spintronics and Phototronics　10　2008/10
MTJ-Based Vth Calibration Circuit Toward Design-for-Variability Era Invited

Atsushi Matsumoto, Akihiro Hirosaki, Takahiro Hanyu

CNSI-RIEC Workshop on Nanoelectronics, Spintronics and Phototronics　35　2008/10
Nonvolatile Lookup Table Circuit for a Standby-Power-Free Field-Programmable Gate Array Invited

Daisuke Suzuki, Takahiro Hanyu

Proceedings of the 1st Student Organizing International Mini-Conference on Information Electronics Systems　1　(S4L-2)　181-182　2008/10
Impact of a TMR-Based Nonvolatile Logic-in-Memory Circuit Invited

Shoun Matsunaga, Takahiro Hanyu

Proceedings of the 1st Student Organizing International Mini-Conference on Information Electronics Systems　1　(S3L-1)　169-170　2008/10
Asynchronous Data-Transfer Interface for an Interleaver in Fully-Parallel Low-Density Parity-Check Decoders Invited

Naoya Onizawa, Takahiro Hanyu

Proceedings of the 1st Student Organizing International Mini-Conference on Information Electronics Systems　1　(S2K-4)　131-132　2008/10
Design of a Processing Element Based on Multiple-Valued Current-Mode Logic for a Many-Core Processor Invited

Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the 1st Student Organizing International Mini-Conference on Information Electronics Systems　1　(S3L-2)　171-172　2008/10
Systematic Design and Verification of Binary/Multiple-Valued Fused Logic Circuits Invited

Takashi Arimitsu, Tasuku Nagai, Masanori Natsui, Takahiro Hanyu

Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information　178　2008/10
MTJ-Based Nonvolatile Logic-in-Memory Circuit and Its Application Invited

Toshiki Taketani, Shoun Matsunaga, Takahiro Hanyu

Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information　195　2008/10
Asynchronous Multiple-Valued Data Transfer and Its Application Invited

Tomoyoshi Funazaki, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of 2008 China-Korea-Japan Graduates Workshop on Electronic Information　186　2008/10
Fabrication of a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions Invited Peer-reviewed

Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Haruhiro Hasegawa, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

APPLIED PHYSICS EXPRESS　1　(9)　091301-1-091301-3　2008/09

DOI： 10.1143/APEX.1.091301 　

ISSN： 1882-0778
Fabrication of a Standby-Power-Free TMR-Based Nonvolatile Memory-in-Logic Circuit Chip with a Spin-Injection Write Scheme Invited Peer-reviewed

Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

International Conference on Solid State Devices and Materials　(C-3-6)　274-275　2008/09
適応的電流源制御に基づくパイプライン電流モード多値演算回路の低電力化 Invited

松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘

多値論理研究ノート　31　15-1-15-6　2008/09
次世代VLSI向き多値回路の系統的設計 Invited

夏井雅典, 羽生貴弘

多値論理研究ノート　31　16-1-16-6　2008/09
TMR素子を用いた高密度不揮発TCAMの構成 Invited

樋山公之, 松永翔雲, 羽生貴弘

平成20年度電気関係学会東北支部連合大会講演論文集　(2E16)　368　2008/08
出力状態モニタリングに基づく電流モード多値順序回路の低消費電力化 Invited

松浦貴史, 白濱弘勝, 夏井雅典, 羽生貴弘

平成20年度電気関係学会東北支部連合大会講演論文集　2008　(2J17)　369　2008/08
電流モードsingle-track方式に基づく非同期データ転送の高速化 Invited

大竹遥, 鬼沢直哉, 松本敦, 羽生貴弘

平成20年度電気関係学会東北支部連合大会講演論文集　(2J18)　370　2008/08
High-Level Synthesis of Asynchronous Circuits and Its Optimization Invited

Atsushi Matsumoto, Tomohiro Yoneda, Takahiro Hanyu

Proc. 17th International Workshop on Post-Binary ULSI Systems　5-8　2008/05
Highly reliable multiple-valued current-mode comparator based on active-load dual-rail operation Peer-reviewed

Masatomo Miura, Takahiro Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E91C　(4)　589-594　2008/04

DOI： 10.1093/ietele/e91-c.4.589 　

ISSN： 1745-1353
Power-aware asynchronous peer-to-peer duplex communication system based on multiple-valued one-phase signaling Peer-reviewed

Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E91C　(4)　581-588　2008/04

DOI： 10.1093/ietele/e91-c.4.581 　

ISSN： 1745-1353
TMRロジックとその応用

羽生貴弘

日本磁気学会第159回研究会資料　39-46　2008/03
TMRロジックとその可能性 Invited

羽生貴弘, 松本敦, 松永翔雲

第55回応用物理関係連合講演会講演予稿集　27p-A-10　2008/03
電流モード多値回路および電圧モード多値回路の構成と評価 Invited

白濱弘勝, 羽生貴弘

電子情報通信学会「多値論理とその応用」第二種研究会技術報告（多値技報）　MVL-08　(15)　93-98　2008/01
多値符号化に基づく非同期式転送方式の検討 Invited

松本敦, 羽生貴弘

電子情報通信学会「多値論理とその応用」第二種研究会技術報告（多値技報）　MVL-08　(16)　99-104　2008/01
Design of high-performance quaternary adders based on output-generator sharing Peer-reviewed

Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　38　8-13　2008

DOI： 10.1109/ISMVL.2008.11 　

ISSN： 0195-623X
Vth-variation compensation of multiple-valued current-mode circuit using TMR devices Peer-reviewed

Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　38　14-19　2008

DOI： 10.1109/ISMVL.2008.13 　

ISSN： 0195-623X
High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit Invited Peer-reviewed

Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　38　70-75　2008

DOI： 10.1109/ISMVL.2008.12 　

ISSN： 0195-623X
TMR-Logic-Based LUT for Quickly Wake-up FPGA Invited Peer-reviewed

Daisuke Suzuki, Tetsuo Endoh, Takahiro Hanyu

2008 51ST MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2　326-+　2008

DOI： 10.1109/MWSCAS.2008.4616802 　

ISSN： 1548-3746
多値非同期データ転送方式に基づく高性能LDPCデコーダLSIの実現 Invited

鬼沢直哉, 羽生貴弘, Vincent Gaudet

第11回システムLSIワークショップ講演資料集およびポスター資料集　272-274　2007/11
Implementation of an Asynchronous LDPC Decoder Chip Using Multiple-Valued Duplex Interleaving Peer-reviewed

N. Onizawa, T. Hanyu, V.C. Gaudet

2007 Analog Decoding Workshop　2007/05
Magnetic tunnel junctions for spintronic memories and beyond Peer-reviewed

Shoji Ikeda, Jun Hayakawa, Young Min Lee, Futnihifo Matsukura, Yuzo Ohno, Takahiro Hanyu, Hideo Ohno

IEEE TRANSACTIONS ON ELECTRON DEVICES　54　(5)　991-1002　2007/05

DOI： 10.1109/TED.2007.894617 　

ISSN： 0018-9383

eISSN： 1557-9646
Active-Load Differential Comparator for Crosstalk-Noise Reduction Peer-reviewed

Akira Mochizuki, Masatomo Miura, Takahiro Hanyu

IEEE International Symposium on Multiple-Valued Logic　37　2007/05
Design and evaluation of a 54 x 54-bit multiplier based on differential-pair circuitry Peer-reviewed

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E90C　(4)　683-691　2007/04

DOI： 10.1093/ietele/e90-c.4.683 　

ISSN： 0916-8524

eISSN： 1745-1353
High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction Peer-reviewed

Akira Mochizuki, Masatomo Miura, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　2007

DOI： 10.1109/ISMVL.2007.28 　

ISSN： 0195-623X
Implementation of a standby-power-free CAM based on complementary ferro elect ric-capacitor logic Peer-reviewed

S. Matsunaga, T. Hanyu, H. Kimura, T. Nakamura, H. Takasu

PROCEEDINGS OF THE ASP-DAC 2007　116-+　2007

DOI： 10.1109/ASPDAC.2007.357968 　

ISSN： 2153-6961
TMRロジックに基づく低消費電力FPGAの構成と評価

渡邊康広, 羽生貴弘

電子情報通信学会「多値論理とその応用」第二種研究会技術報告　MVL-07　(1)　1-7　2007/01

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Asynchronous peer-to-peer simplex/duplex-compatible communication system using a one-phase signaling scheme Peer-reviewed

Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu

Proceedings of The International Symposium on Multiple-Valued Logic　37　2007

DOI： 10.1109/ISMVL.2007.8 　

ISSN： 0195-623X
Design of a processing element based on quaternary differential logic for a multi-core SIMD processor Peer-reviewed

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

Proceedings of The International Symposium on Multiple-Valued Logic　37　2007

DOI： 10.1109/ISMVL.2007.14 　

ISSN： 0195-623X
3.2-Gb/s 1024-b rate-1/2 LDPC decoder chip using a flooding-type update-schedule algorithm Peer-reviewed

Naoya Onizawa, Tomokazu Ikeda, Takahiro Hanyu, Vincent C. Gaudet

2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3　50　182-+　2007

DOI： 10.1109/MWSCAS.2007.4488574 　

ISSN： 1548-3746
A standby-power-free TCAM based on TMR logic Peer-reviewed

Kei Kimura, Takahiro Hanyu

2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3　50　715-718　2007

DOI： 10.1109/MWSCAS.2007.4488707 　

ISSN： 1548-3746
Design of a Fluid Analysis Simulator Based on Lattice Gas Cellular Automaton

Daisuke Suzuki, Takahiro Hanyu

Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.　132-134　2006/11

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通研インポート200703
Automatic Place and Route Scheme in Multiple-Valued Current-Mode Circuit Design

Tasuku Nagai, Tomohiro Takahashi, Naoya Onizawa, Takahiro Hanyu

Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.　57-58　2006/11

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通研インポート200703
TMR-Based Differential Logic for Vt-Variation Compansation

Akihiro Hirosaki, Masatomo Miura, Akira Mochizuki, Takahiro Hanyu

Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.　51-52　2006/11

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通研インポート200703
Low-Power Latch Based on Dynamic Differential Logic

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu

Proc. 3rd Workshop of Yeungnum Univ. and Tohoku Univ.　138-140　2006/11

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通研インポート200703
Implementation of a high-speed asynchronous data-transfer chip based on multiple-valued current-signal multiplexing Peer-reviewed

Tomohiro Takahashi, Takahiro Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E89C　(11)　1598-1604　2006/11

DOI： 10.1093/ietele/e89-c.11.1598 　

ISSN： 1745-1353
Design and evaluation of a NULL-convention circuit based on dual-rail current-mode differential logic Peer-reviewed

Naoya Onizawa, Takahiro Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E89C　(11)　1575-1580　2006/11

DOI： 10.1093/ietele/e89-c.11.1575 　

ISSN： 1745-1353
Design of a low-power quaternary flip-flop based on dynamic differential logic Peer-reviewed

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E89C　(11)　1591-1597　2006/11

DOI： 10.1093/ietele/e89-c.11.1591 　

ISSN： 1745-1353
TMRロジックとその応用

羽生貴弘, 望月明, 渡邊康広

応用電子物性分科会誌　12　(4)　154-159　2006/10

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通研インポート200703
多値2線符号化に基づく高性能非同期データ転送VLSI

高橋知宏, 水澤一泰, 羽生貴弘

信学技報　106　(315)　37-42　2006/10
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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通研インポート200703
多値2線符号化に基づく双方向非同期データ転送LSIの高性能化

水澤一泰, 高橋知宏, 羽生貴弘

平成18年度電気関係学会東北支部連合大会講演論文集　342　2006/08

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通研インポート200703
差動ロジックに基づく高性能VLSIの展望

望月明, 羽生貴弘

多値論理研究ノート　29　19-1-19-6　2006/08

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通研インポート200703
隣接データの類似性に着目した高速LDPC復号化とその評価

池田智和, 鬼沢直哉, 羽生貴弘

平成18年度電気関係学会東北支部連合大会講演論文集　70　2006/08

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通研インポート200703
２線差動論理に基づくノイズフリー多値集積回路

三浦成友, 望月明, 羽生貴弘

平成18年度電気関係学会東北支部連合大会講演論文集　341　2006/08

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通研インポート200703
TMRロジックに基づく低消費電力TCAMの構成

木村圭, 渡邊康広, 羽生貴弘

平成18年度電気関係学会東北支部連合大会講演論文集　206　2006/08

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通研インポート200703
Ferroelectric-Based Logic Circuit and Its Application to Content-Addressable Memory Peer-reviewed

H. Kimura, Y. Fujimori, T. Nakamura, H. Takasu, T. Hanyu

Proceeding of IEEE The 2006 International Meeting for Future Electron Devices　41-42　2006/04

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通研インポート200703
強誘電体CAMとその応用

堀田健介, 羽生貴弘

電子情報通信学会「多値論理とその応用」第二種研究会技術報告　MVL-06　(1)　86-91　2006/01

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通研インポート200703
Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic Peer-reviewed

Akira Mochizuki, Takahiro Hanyu

ISMVL 2006: 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　32-37　2006

DOI： 10.1109/ISMVL.2006.24 　

ISSN： 0195-623X
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits Peer-reviewed

Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu

ISMVL 2006: 36th International Symposium on Multiple-Valued Logic　86-91　2006

DOI： 10.1109/ISMVL.2006.18 　

ISSN： 0195-623X
TMR-based logic-in-memory circuit for low-power VLSI Peer-reviewed

A Mochizuki, H Kimura, M Ibuki, T Hanyu

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E88A　(6)　1408-1415　2005/06

DOI： 10.1093/ietfec/e88-a.6.1408 　

ISSN： 0916-8508

eISSN： 1745-1337
TMR-Based Logic-in-Memory Circuit and Its Application Invited

Takahiro Hanyu, Akira Mochizuki, Mitsuru Ibuki

14th International Workshop on Post-Binary ULSI Systems　22-29　2005/05
0.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI Invited

Akira Mochizuki, Takahiro Hanyu

14th International Workshop on Post-Binary ULSI Systems　35-41　2005/05
Multiple-valued duplex asynchronous data transfer scheme for interleaving in LDPC decoders Peer-reviewed

N Onizawa, A Mochizuki, T Hanyu, VC Gaudet

35TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　138-143　2005

ISSN： 0195-623X
Design of a low-power multiple-valued integrated circuit based on dynamic source-coupled logic Peer-reviewed

A Mochizuki, T Hanyu, M Kameyama

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　11　(5-6)　481-497　2005

ISSN： 1542-3980
Control signal multiplexing based asynchronous data transfer scheme using multiple-valued bidirectional current-mode circuits Peer-reviewed

T Takahashi, T Hanyu

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　11　(5-6)　499-517　2005

ISSN： 1542-3980

eISSN： 1542-3999
Logic-in-memory VLSI circuit for fully parallel nearest pattern matching based on floating-gate-MOS pass-transistor logic Peer-reviewed

T Hanyu, S Kaeriyama, M Kameyama

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　11　(5-6)　619-632　2005

ISSN： 1542-3980

eISSN： 1542-3999
A 1.88ns 54x54-bit multiplier in 0.18 mu m CMOS based on multiple-valued differential-pair circuitry Peer-reviewed

A Mochizuki, T Hanyu

2005 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS　264-267　2005

DOI： 10.1109/VLSIC.2005.1469382 　
Dynamically function-programmable bus architecture for high-throughput intra-chip data transfer Peer-reviewed

A Mochizuki, T Takeuchi, T Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E87C　(11)　1915-1922　2004/11

ISSN： 1745-1353
Low-power motion-vector detection VLSI processor based on pass-gate logic with dynamic supply-voltage/clock-frequency scaling Peer-reviewed

A Mochizuki, D Nishinohara, T Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E87C　(11)　1876-1883　2004/11

ISSN： 0916-8524

eISSN： 1745-1353
Differential operation oriented multiple-valued encoding and circuit realization for asynchronous data transfer Peer-reviewed

T Takahashi, N Onizawa, T Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E87C　(11)　1928-1934　2004/11

ISSN： 1745-1353
Low-Powor Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its Application Peer-reviewed

A. Mochizuki, D. Nishinohara, T. Hanyu

2004 International Conference on Circuits/Systems, Computers and Communications　6CIL-5-1-6CIL-5-4　2004/07
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI Peer-reviewed

H. Kimura, M. Ibuki, T. Hanyu

2004 International Conference on Circuits/Systems, Computers and Communications　8　8C3L-3-1-8C3L-3-4　2004/07
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI Peer-reviewed

H Kimura, T Hanyu, M Kameyama, Y Fujimori, T Nakamura, H Takasu

IEEE JOURNAL OF SOLID-STATE CIRCUITS　39　(6)　919-926　2004/06

DOI： 10.1109/JSSC.2004.827802 　

ISSN： 0018-9200
Asynchronous Data Transfer Scheme Based on Simultaneous Control in a Bidirectional Way and Its VLSI Design Peer-reviewed

T. Takahashi, T. Hanyu, M. Kameyama

Transaction on IEICE C　Vol.J87-C　(No.5)　459-468　2004/05
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
Low-power multiple-valued current-mode logic using substrate bias control Peer-reviewed

A Mochizuki, T Hanyu

IEICE TRANSACTIONS ON ELECTRONICS　E87C　(4)　582-588　2004/04

ISSN： 1745-1353
Ferroelectric non-volatile logic devices Peer-reviewed

H Takasu, Y Fujimori, T Nakamura, H Kimura, T Hanyu, M Kameyama

INTEGRATED FERROELECTRICS　61　83-88　2004

DOI： 10.1080/10584580490458793 　

ISSN： 1058-4587
Intra-chip address-presetting data-transfer scheme using four-valued encoding Peer-reviewed

A Mochizuki, T Takeuchi, T Hanyu

34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　192-197　2004

ISSN： 0195-623X
Multiple-valued multiple-rail encoding scheme for low-power asynchronous communication Peer-reviewed

T Takahashi, T Hanyu

34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　20-25　2004

ISSN： 0195-623X
A study of multiple-valued magnetoresistive RAM (MRAM) using binary MTJ devices Peer-reviewed

H Kimura, K Pagiamtzis, A Sheikholeslami, T Hanyu

34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　340-345　2004

ISSN： 0195-623X
Design of Ferroelectric-Based Logic-in-Memory VLSI Peer-reviewed

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu

IEICE Transactions on Electronics　J86-C　(8)　886-893　2003/08
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
Complementary Ferroelectric-Capacitor Logic and Its Application Peer-reviewed

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu

IEEE International Solid-State Circuits Conference Digest of Technical Papers　46　160-161　2003/02
Ferroelectric non-volatile logic devices Peer-reviewed

Y Fujimori, T Nakamura, H Takasu, H Kimura, T Hanyu, M Kameyama

INTEGRATED FERROELECTRICS　56　1003-1012　2003

DOI： 10.1080/10584580390259489 　

ISSN： 1058-4587
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI Peer-reviewed

H Kimura, T Hanyu, M Kameyama, Y Fujimori, T Nakamura, H Takasu

2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS　46　160-+　2003

ISSN： 0193-6530
Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimimzation Peer-reviewed

Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama

Journal of Multiple-Valued Logic & Soft Computing　9　(1)　5-21　2003/01
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Applications Peer-reviewed

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

Journal of Multiple-Valued Logic & Soft Computing　9　(1)　23-42　2003/01
Bidirectional data transfer based asynchronous VLSI system using multiple-valued current mode logic Peer-reviewed

T Hanyu, T Takahashi, M Kameyama

33RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　33　99-104　2003

ISSN： 0195-623X
Multiple-valued dynamic source-coupled logic Peer-reviewed

T Hanyu, A Mochizuki, M Kameyama

33RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　33　207-212　2003

ISSN： 0195-623X
New Paradigm VLSI Computing Research and IT Policy

Takahiro Hanyu

Proc. 2002 International Symposium on New Paradigm VLSI Computing　1　9-12　2002/12
VLSI System Based on Ferroelectric Logic-in-Memory Architecture

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

International Symposium on New Paradigm VLSI Computing　1　60-65　2002/12
Implementation of a DRAM-cell-based multiple-valued logic-in-memory circuit Peer-reviewed

H Kimura, T Hanyu, M Kameyama

IEICE TRANSACTIONS ON ELECTRONICS　E85C　(10)　1814-1823　2002/10

ISSN： 1745-1353
Dynamic-storage-based logic-in-memory circuit and its application to a fine-grain pipelined system Peer-reviewed

H Kimura, T Hanyu, M Kameyama

IEICE TRANSACTIONS ON ELECTRONICS　E85C　(2)　288-296　2002/02

ISSN： 0916-8524

eISSN： 1745-1353
Ferroelectric-based functional pass-gate for fine-grain pipelined VLSI computation Peer-reviewed

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu

Digest of Technical Papers-IEEE International Solid-State Circuits Conference　164-165　2002

DOI： 10.1109/ISSCC.2002.992195 　

ISSN： 0193-6530
Multiple-valued logic-in-memory VLSI based on ferroelectric capacitor storage and charge addition Peer-reviewed

H Kimura, T Hanyu, M Kameyama

ISMVL 2002: 32ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　32　161-166　2002

ISSN： 0195-623X
Fully source-coupled logic based multiple-valued VLSI Peer-reviewed

T Ike, T Hanyu, M Kameyama

ISMVL 2002: 32ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　32　270-275　2002

ISSN： 0195-623X
Ferroelectric-based functional pass-gate for low-power VLSI Peer-reviewed

H Kimura, T Hanyu, M Kameyama, Y Fujimori, T Nakamura, H Takasu

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS　196-199　2002
Asynchronous current-mode multiple-valued VLSI system based on two-color two-rail coding Peer-reviewed

T Hanyu, M Kameyama

ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS　84　(11)　60-67　2001

ISSN： 8756-663X
Dual-rail multiple-valued current-mode VLSI with biasing current sources Peer-reviewed

T Ike, T Hanyu, M Kameyama

31ST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　31　21-26　2001

ISSN： 0195-623X
Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits

T Hanyu, M Kameyama, K Shimabukuro, C Zukeran

31ST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　31　167-172　2001

ISSN： 0195-623X
Integration of Asynchronous and Self-Checking Multiple-Valued Current-Mode Circuits Based on Dual-Rail Differential Logic Peer-reviewed

T. Hanyu, T. Ike, M. Kameyama

Pacific Rim International Symposium on Dependable Computing　7　27-33　2001

DOI： 10.1109/PRDC.2000.897281 　
2線式電流モード多値論理に基づくセルフチェッキングVLSI Peer-reviewed

池司, 羽生貴弘, 亀山充隆

電子情報通信学会論文誌　J83-C　(4)　318-325　2000
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
2色2線式符号化に基づく非同期電流モード多値VLSIシステム Peer-reviewed

羽生貴弘, 亀山充隆

電子情報通信学会論文誌　J83-C　(6)　463-470　2000
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
Logic-in-Memory VLSI Using Ferroelectric Devices and Its Application Peer-reviewed

木村啓明, 羽生貴弘, 亀山充隆

IEICE Transactions.　J83-C　(8)　749-756　2000
Design of a Parallel VLSI Processor for Road Extraction Based on Logic-in Memory Architecture Peer-reviewed

工藤隆男, 羽生貴弘, 亀山充隆

Trans. of the SICE　36　(11)　1009-1018　2000
Publisher: The Society of Instrument and Control Engineers
DOI： 10.9746/sicetr1965.36.1009 　

ISSN： 0453-4654

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New logic-in-memory architecture of a high-performance road-extraction VLSI processor is proposed to solve data transfer bottleneck between a memory and processing elements. A VLSI-oriented algorithm having parallelism and regularity is developed to check whether a car can go through the 3D topographical map obtained from 3D instrumentation. To execute the algorithm very fast based on locally parallel processing, a highly parallel VLSI processor with many redundant processing elements is discussed. The processing element consists of an arithmetic element and a register for the storage of the topographical data. A shift register is constructed in the processing element array, so that data transfer between adjacent registers is effectively done. The topographical data once read out from a memory is being stored in shift registers and it is reused until the related processing is completed, so that memory bandwidth becomes minimum. Allocation such that data transfer bottleneck between processing elements becomes minimum is discussed, and it is made clear that the logic-in-memory architecture based on dynamic active control of the redundant processing elements is very useful for the high-performance parallel processing. Finally, the evaluation of the proposed VLSI processor is done, and its superiority to other equivalent processors is made clear from the viewpoint of performance and hardware complexity.
Low-power dual-rail multiple-valued current-mode logic circuit using multiple input-signal levels Peer-reviewed

T Hanyu, T Ike, M Kameyama

30TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　30　382-387　2000

ISSN： 0195-623X
DRAM-cell-based multiple-valued logic-in-memory VLSI with charge addition and charge storage Peer-reviewed

T Hanyu, H Kimura, M Kameyama

30TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　30　423-429　2000

ISSN： 0195-623X
Arithmetic-oriented multiple-valued logic-in-memory VLSI based on current-mode logic Peer-reviewed

S Kaeriyama, T Hanyu, M Kameyama

30TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　30　438-443　2000

ISSN： 0195-623X
Arithmetic-Oriented Logic-in-Memory VLSI Using Floating-Gate MOS Transistors Peer-reviewed

S. Kaeriyama, T. Hanyu, M. Kameyama

Multiple-Valued Logic International Journal　8　(1)　33-51　2000/01
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic Peer-reviewed

T Hanyu, T Ike, M Kameyama

2000 PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS　27-33　2000

DOI： 10.1109/PRDC.2000.897281 　
Asynchronous Current-Mode Multiple-Valued VLSI System Based on Two-Color Two-Rail Coding

HANYU Takahiro, KAMEYAMA Michitaka

ITE Technical Report　23　(58)　41-47　1999/09/21
Publisher: The Institute of Image Information and Television Engineers
DOI： 10.11485/itetr.23.58.0_41 　

ISSN： 1342-6893

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This paper presents a new asynchronous data-transfer scheme based on two-color two-rail complementary coding, which is suitable for a multiple-valued current-mode VLSI circuit. Two kinds of R-valued two-rail complementary signals, called ' two-color two-rail codes, ' which represent 'data values, ' are used in odd and even phases, respectively. The sum of R-valued two-rail complementary values in an odd phase is a constant (R-1), while the sum of R-valued two-rail complementary values in an even phase is also a constant 3 (R-1). The difference of these constant values in the two-color coding makes it easy to detect a data-arrival state from a data-transition state without spacers. Moreover, basic components to realize the above asynchronous VLSI system, a signal-state detector to detect a data-arrival state, and a two-color code generator to produce two-color two-rail signals can be easily designed by a multiple-valued current-mode circuit technology based on dual-rail differential logic. Finally, the advantage of the proposed asynchronous multiple-valued VLSI circuit is demonstrated in comparison with the corresponding binary implementation.
Multiple-valued logic-in-memory VLSI architecture based on floating-gate-MOS pass-transistor logic Peer-reviewed

T Hanyu, M Kameyama

IEICE TRANSACTIONS ON ELECTRONICS　E82C　(9)　1662-1668　1999/09

ISSN： 0916-8524

eISSN： 1745-1353
Innovation of Intelligent Integrated System Architecture Peer-reviewed

M. Kameyama, T. Hanyu, M. Hariyama

Int. Symp. on Future of Intellectual Integrated Electronics　231-247　1999
Multiple-Valued Logic-in-Memory VLSI and Its Applications Peer-reviewed

T. Hanyu, M. Kameyama

Int. Symp. on Future of Intellectual Integrated Electronics　271-281　1999
Multiple-valued content-addressable memory using metal-ferroelectric-semiconductor FETs Peer-reviewed

T Hanyu, H Kimura, M Kameyama

1999 29TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　29　30-35　1999

ISSN： 0195-623X
Self-checking multiple-valued circuit based on dual-rail current-mode differential logic Peer-reviewed

T Hanyu, T Ike, M Kameyama

1999 29TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　29　275-279　1999

ISSN： 0195-623X
Design of Multiple-Valued Logic-in-Memory VLSI Based on Linear Summation Peer-reviewed

S. Kaeriyama, T. Hanyu, M. Kameyama

Korea-Japan Joint Symposium on Multiple-Valued Logic　1　211-218　1999
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application Peer-reviewed

Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama

Systems and Computers in Japan　29　(11)　40-47　1998
Publisher: John Wiley and Sons Inc.
DOI： 10.1002/(SICI)1520-684X(199810)29:11<40::AID-SCJ5>3.0.CO;2-S 　

ISSN： 0882-1666
ディジットパラレル多値CAMの構成と評価 Peer-reviewed

羽生貴弘, 寺西要, 亀山充隆

電子情報通信学会論文誌　J81　(D-I)　151-156　1998
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0915-1915
電流モードディープサブミクロン多値集積回路の最適設計とその応用 Peer-reviewed

齋藤敬弘, 羽生貴弘, 亀山充隆

電子情報通信学会論文誌　J81　(D-I)　157-164　1998
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0915-1915
Multiple-Valued Logic-in-Memory VLSI Based on a Floating-Gate-MOS Pass-Transistor Network Peer-reviewed

T. Hanyu, K. Teranishi, M. Kameyama

IEEE International Solid-State Circuits Conference Digest of Technical Papers　41　194-195　1998
Asynchronous multiple-valued VLSI system based on dual-rail current-mode differential logic Peer-reviewed

T Hanyu, T Saito, M Kameyama

1998 28TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - PROCEEDINGS　28　134-139　1998

ISSN： 0195-623X
Multiple-valued floating-gate-MOS pass logic and its application to logic-in-memory VLSI Peer-reviewed

T Hanyu, K Teranihi, M Kameyama

1998 28TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - PROCEEDINGS　28　270-275　1998

ISSN： 0195-623X
Non-volatile one-transistor-cell multiple-valued CAM with a digit-parallel-access scheme and its applications Peer-reviewed

T Hanyu, N Kanagawa, M Kameyama

COMPUTERS & ELECTRICAL ENGINEERING　23　(6)　407-414　1997/11

DOI： 10.1016/S0045-7906(97)00027-X 　

ISSN： 0045-7906
Design and implementation of a low-power multiple-valued current-mode integrated circuit with current-source control Peer-reviewed

T Hanyu, S Kazama, M Kameyama

IEICE TRANSACTIONS ON ELECTRONICS　E80C　(7)　941-947　1997/07

ISSN： 0916-8524

eISSN： 1745-1353
Design and evaluation of a 4-valued universal-literal CAM for cellular logic image processing Peer-reviewed

T Hanyu, M Arakaki, M Kameyama

IEICE TRANSACTIONS ON ELECTRONICS　E80C　(7)　948-955　1997/07

ISSN： 0916-8524

eISSN： 1745-1353
A transistor cell 4-valued universal-literal CAM for a cellular logic image processor Peer-reviewed

T Hanyu, M Arakaki, M Kameyama

1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS　40　46-47　1997

ISSN： 0193-6530
One-transistor-cell 4-valued universal-literal CAM for cellular logic image processing Peer-reviewed

T Hanyu, M Arakaki, M Kameyama

27TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - 1997 PROCEEDINGS　27　175-180　1997

ISSN： 0195-623X
Design and evaluation of a multiple-valued arithmetic integrated circuit based on differential logic Peer-reviewed

T Hanyu, A Mochizuki, M Kameyama

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS　143　(6)　331-336　1996/12

DOI： 10.1049/ip-cds:19960710 　

ISSN： 1350-2409
Design of a one-transistor-cell multiple-valued CAM Peer-reviewed

T Hanyu, N Kanagawa, M Kameyama

IEEE JOURNAL OF SOLID-STATE CIRCUITS　31　(11)　1669-1674　1996/11

ISSN： 0018-9200
Design of a Rule-Based Highly-Safe Intelligent Vehicle Using a Confent-Addressable Memory Peer-reviewed

T. Hanyu, S. Abe, M. Kameyama, T. Higuchi

Trans. of the Society of Instrument and Control Engineers　32　(1)　114-121　1996
Publisher:
DOI： 10.9746/sicetr1965.32.114 　

ISSN： 0453-4654
Synthesis of Multiple-Valued Logic Metworks Based on Super Pass Gates Peer-reviewed

X. Deng, T. Hanyu, M. Kameyama

Multiple-Valued Logic International Journal　1　(1)　161-183　1996
One-transistor-cell multiple-valued CAM for a collision detection VLSI processor Peer-reviewed

T Hanyu, N Kanagawa, M Kameyama

1996 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS　39　264-265　1996

ISSN： 0193-6530
A multiple-valued ferroelectric content-addressable memory Peer-reviewed

A Sheikholeslami, PG Gulak, T Hanyu

1996 26TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　26　74-79　1996

ISSN： 0195-623X
Quaternary universal-literal CAM for cellular logic image processing Peer-reviewed

T Hanyu, M Arakaki, M Kameyama

1996 26TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　26　224-229　1996

ISSN： 0195-623X
Non-Volatile One-Transistor-Cell CAM and its Applications Peer-reviewed

T. Hanyu, N. Kanagawa, M. Kameyama

International Conference on Soft Computing　4　101-104　1996
Low-power multiple-valued current-mode integrated circuit with current-source control and its application Peer-reviewed

T Hanyu, S Kazama, M Kameyama

PROCEEDINGS OF THE ASP-DAC '97 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1997　413-418　1996
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic Peer-reviewed

T Hanyu, M Kameyama

IEEE JOURNAL OF SOLID-STATE CIRCUITS　30　(11)　1239-1245　1995/11

DOI： 10.1109/4.475711 　

ISSN： 0018-9200
MULTIPLE-VALUED LOGIC NETWORK USING QUANTUM-DEVICE-ORIENTED SUPERPASS GATES AND ITS MINIMIZATION Peer-reviewed

DENG, X, T HANYU, M KAMEYAMA

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS　142　(5)　299-306　1995/10

DOI： 10.1049/ip-cds:19952168 　

ISSN： 1350-2409
QUANTUM-DEVICE-ORIENTED MULTIPLE-VALUED LOGIC SYSTEM BASED ON A SUPER PASS GATE Peer-reviewed

XW DENG, T HANYU, M KAMEYAMA

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E78D　(8)　951-958　1995/08

ISSN： 0916-8532
FUNCTIONALLY SEPARATED, MULTIPLE-VALUED CONTENT-ADDRESSABLE MEMORY AND ITS APPLICATIONS Peer-reviewed

T HANYU, S ARAGAKI, T HIGUCHI

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS　142　(3)　165-172　1995/06

DOI： 10.1049/ip-cds:19951949 　

ISSN： 1350-2409
Prospects of Intelligent Integrated Systems towards Giga-Scale System-on-Chip Invited Peer-reviewed

M. Kameyama, T. Hanyu

Journal of the Institute of Electronics, Information and Communication Engineers　78　(2)　187-194　1995/02
Rule-Based Highly-Safe Intelligent Vehicle Using a New Content-Addressable Memory Peer-reviewed

T. Hanyu, S. Abe, M. Kameyama, T. Higuchi

IEEE Proc. of the Intelligent Vehicles Symposium　467-472　1995
A 1.5V-SUPPLY 200MHZ PIPELINED MULTIPLIER USING MULTIPLE-VALUED CURRENT-MODE MOS DIFFERENTIAL LOGIC CIRCUITS Peer-reviewed

T HANYU, A MOCHIZUKI, M KAMEYAMA

1995 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, DIGEST OF TECHNICAL PAPERS　38　314-315　1995

ISSN： 0193-6530
Multiple-valued arithmetic integrated circuits based on 1.5V-supply dual-rail source-coupled logic Peer-reviewed

T Hanyu, A Mochizuki, M Kameyama

1995 25TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　25　64-69　1995

ISSN： 0195-623X
Quantum device model based super pass gate for multiple-valued digital systems Peer-reviewed

XW Deng, T Hanyu, M Kameyama

1995 25TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　25　92-97　1995

ISSN： 0195-623X
On-chip hardware accelerator for model-based 3-D instrumentation using run-length matching Peer-reviewed

M Kamoshida, T Hanyu, M Kameyama

PROCEEDINGS OF THE 1995 IEEE IECON - 21ST INTERNATIONAL CONFERENCE ON INDUSTRIAL ELECTRONICS, CONTROL, AND INSTRUMENTATION, VOLS 1 AND 2　21　1319-1323　1995

ISSN： 1553-572X
DESIGN AND EVALUATION OF A CURRENT-MODE MULTIPLE-VALUED PLA BASED ON A RESONANT-TUNNELING TRANSISTOR MODEL Peer-reviewed

DENG, X, T HANYU, M KAMEYAMA

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS　141　(6)　445-450　1994/12

DOI： 10.1049/ip-cds:19941389 　

ISSN： 1350-2409
LOW-POWER 8-VALUED CELLULAR ARRAY VLSI FOR HIGH-SPEED IMAGE-PROCESSING Peer-reviewed

T HANYU, M KUWAHARA, T HIGUCHI

IEICE TRANSACTIONS ON ELECTRONICS　E77C　(7)　1042-1048　1994/07

ISSN： 0916-8524

eISSN： 1745-1353
MULTIPLE-VALUED CURRENT-MODE MOS INTEGRATED-CIRCUITS BASED ON DUAL-RAIL SOURCE-COUPLED LOGIC Peer-reviewed

T HANYU, A MOCHIZUKI, M KAMEYAMA

TWENTY-FOURTH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　24　19-26　1994

ISSN： 0195-623X
Rule-Based Highly-Safe Intelligent Vehicle Using a New Content-Addressable Memory Peer-reviewed

M. Hariyama, T. Hanyu, M. Kameyama

IEEE Proc. of the Intelligent Vehicles Symposium　143-148　1994
A HIGH-DENSITY MULTIPLE-VALUED CONTENT-ADDRESSABLE MEMORY-BASED ON ONE TRANSISTOR CELL Peer-reviewed

S ARAGAKI, T HANYU, T HIGUCHI

IEICE TRANSACTIONS ON ELECTRONICS　E76C　(11)　1649-1656　1993/11

ISSN： 0916-8524

eISSN： 1745-1353
MULTIPLE-VALUED PROGRAMMABLE LOGIC ARRAY BASED ON A RESONANT-TUNNELING DIODE MODEL Peer-reviewed

T HANYU, Y YABE, M KAMEYAMA

IEICE TRANSACTIONS ON ELECTRONICS　E76C　(7)　1126-1132　1993/07

ISSN： 0916-8524

eISSN： 1745-1353
3-D OBJECT RECOGNITION SYSTEM BASED ON 2-D CHAIN CODE MATCHING Peer-reviewed

T HANYU, S CHOI, M KAMEYAMA, T HIGUCHI

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E76A　(6)　917-923　1993/06

ISSN： 0916-8508

eISSN： 1745-1337
PROSPECTS OF MULTIPLE-VALUED VLSI PROCESSORS Peer-reviewed

T HANYU, M KAMEYAMA, T HIGUCHI

IEICE TRANSACTIONS ON ELECTRONICS　E76C　(3)　383-392　1993/03

ISSN： 0916-8524

eISSN： 1745-1353
RULE-PROGRAMMABLE MULTIPLE-VALUED MATCHING VLSI PROCESSOR FOR REAL-TIME RULE-BASED SYSTEMS Peer-reviewed

T HANYU, K TAKEDA, T HIGUCHI

IEICE TRANSACTIONS ON ELECTRONICS　E76C　(3)　472-479　1993/03

ISSN： 0916-8524

eISSN： 1745-1353
High-Speed Multiple-Valued Associative Memory Based on N-Ary-Tree Network Peer-reviewed

羽生貴弘, 樋口龍雄

Transactions of the Institute of Electronics, Information and Communication Engineers　J76-D-I　(2)　54-62　1993
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0915-1915
Beyond-Binary Circuits for Signal Processing Peer-reviewed

T. Hanyu, M. Kameyama, T. Higuchi

IEEE International Solid-State Circuits Conference Digest of Technical Papers　36　134-135　1993
A MULTIPLE-VALUED CONTENT-ADDRESSABLE MEMORY USING LOGIC-VALUE CONVERSION AND THRESHOLD FUNCTIONS Peer-reviewed

S ARAGAKI, T HANYU, T HIGUCHI

TWENTY-THIRD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC : PROCEEDINGS　23　170-175　1993

ISSN： 0195-623X
PROSPECTS OF MULTIPLE-VALUED ASSOCIATIVE VLSI PROCESSORS Peer-reviewed

T HANYU, M KAMEYAMA

PROCEEDINGS OF THE 36TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2　36　1484-1488　1993
Design of a Low-Power Multiple-Valued Cellular Array Using Dynamic Circuits and Its Application to Image Processing Peer-reviewed

T. Hanyu, M. Kuwahara, T. Higuchi

IEEE Int. Workshop on Intelligent Signal Processing and Communication Systems　309-314　1993
DIGIT-PIPELINED ON-CHIP CLIQUE-FINDING VLSI PROCESSOR FOR REAL-TIME 3-D OBJECT RECOGNITION Peer-reviewed

T HANYU, T KODAMA, T HIGUCHI

ELECTRONICS LETTERS　28　(8)　722-724　1992/04

DOI： 10.1049/el:19920458 　

ISSN： 0013-5194
DYNAMICALLY RULE-PROGRAMMABLE VLSI PROCESSOR FOR FULLY-PARALLEL INFERENCE Peer-reviewed

T HANYU, K TAKEDA, T HIGUCHI

ELECTRONICS LETTERS　28　(7)　695-697　1992/03

DOI： 10.1049/el:19920439 　

ISSN： 0013-5194
DESIGN OF A MULTIPLE-VALUED RULE-PROGRAMMABLE MATCHING VLSI CHIP FOR REAL-TIME RULE-BASED SYSTEMS Peer-reviewed

T HANYU, K TAKEDA, T HIGUCHI

PROCEEDINGS - THE TWENTY-SECOND INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　22　274-281　1992
VLSI-Oriented 3-D Object Recognition Algorithm Based on Chain Code Matching Peer-reviewed

S. Choi, T. Hanyu, M. Kameyama, T.Higuchi

Joint Technical Conf. on Circuits/Systems, Computers and Communications　36-40　1992
200-VERTEX ON-CHIP CLIQUE-FINDING VLSI PROCESSOR FOR REAL-TIME 3-D OBJECT RECOGNITION Peer-reviewed

T HANYU, T KODAMA, T HIGUCHI

PROCEEDINGS OF THE 1992 INTERNATIONAL CONFERENCE ON INDUSTRIAL ELECTRONICS, CONTROL, INSTRUMENTATION, AND AUTOMATION, VOLS 1-3　3　1379-1384　1992
A DESIGN OF A HIGH-DENSITY MULTILEVEL MATCHING ARRAY CHIP FOR ASSOCIATIVE PROCESSING Peer-reviewed

T HANYU, H ISHII, T HIGUCHI

IEICE TRANSACTIONS ON COMMUNICATIONS ELECTRONICS INFORMATION AND SYSTEMS　74　(4)　918-928　1991/04

ISSN： 0917-1673
A MULTIPLE-VALUED LOGIC ARRAY VLSI BASED ON 2-TRANSISTOR DELTA-LITERAL CIRCUIT AND ITS APPLICATION TO REAL-TIME REASONING SYSTEMS Peer-reviewed

T HANYU, Y KOJIMA, T HIGUCHI

PROCEEDINGS OF THE TWENTY-FIRST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　21　16-23　1991
A FLOATING-GATE-MOS-BASED MULTIPLE-VALUED ASSOCIATIVE MEMORY Peer-reviewed

T HANYU, T HIGUCHI

PROCEEDINGS OF THE TWENTY-FIRST INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　21　24-31　1991
DESIGN OF A HIGH-DENSITY MULTIPLE-VALUED CONTENT-ADDRESSABLE MEMORY BASED ON FLOATING-GATE MOS DEVICES Peer-reviewed

T HANYU, T HIGUCHI

PROCEEDINGS OF THE TWENTIETH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　20　18-23　1990
HIGH-DENSITY QUATERNARY LOGIC ARRAY CHIP FOR KNOWLEDGE INFORMATION-PROCESSING SYSTEMS Peer-reviewed

T HANYU, T HIGUCHI

IEEE JOURNAL OF SOLID-STATE CIRCUITS　24　(4)　916-921　1989/08

DOI： 10.1109/4.34071 　

ISSN： 0018-9200
多値連想メモリの構成 Peer-reviewed

羽生貴弘, 樋口龍雄

電子情報通信学会論文誌　J71-D　(8)　1502-1510　1988
Publisher:
ISSN： 0913-5731
Design of a Highly Parallel AI Processor Using New Multiple-Valued MOS Devices Peer-reviewed

T. Hanyu, T. Higuchi

Proc. IEEE International Symposium on Multiple-Valued Logic　18　300-306　1988
High-Density Quaternary Logic Array Chip for Knowledge Information Processing Systems Peer-reviewed

T. Hanyu, T. Higuchi

IEEE Symposium VLSI Circuits Digest of Technical Papers　3　29-30　1988
DESIGN AND IMPLEMENTATION OF QUATERNARY NMOS INTEGRATED-CIRCUITS FOR PIPELINED IMAGE-PROCESSING Peer-reviewed

M KAMEYAMA, T HANYU, T HIGUCHI

IEEE JOURNAL OF SOLID-STATE CIRCUITS　22　(1)　20-27　1987/02

DOI： 10.1109/JSSC.1987.1052666 　

ISSN： 0018-9200
Design and implementation of an nmos image processor based on quaternary logic Peer-reviewed

Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi

Systems and Computers in Japan　18　(3)　92-106　1987

DOI： 10.1002/scj.4690180309 　

ISSN： 1520-684X 0882-1666
高速パターンマッチング用4値ゲートアレーの構成 Peer-reviewed

羽生貴弘, 亀山充隆, 樋口龍雄

電子情報通信学会論文誌　J70-D　(2)　493-496　1987
Publisher:
ISSN： 0913-5731
Quaternary Gate Array for Pattern Matching and its Application to Knowledge Information Processing System Peer-reviewed

T. Hanyu, M. Kameyama, T. Higuchi

Proc. IEEE International Symposium on Multiple-Valued Logic　17　181-187　1987
4値論理に基づくNMOS画像処理プロセッサの構成と試作 Peer-reviewed

羽生貴弘, 亀山充隆, 樋口龍雄

電子通信学会論文誌　J69-D　(5)　667-678　1986
Publisher:
ISSN： 0374-468X
AN NMOS PIPELINED IMAGE-PROCESSOR USING QUATERNARY LOGIC Peer-reviewed

M KAMEYAMA, T HANYU, M ESASHI, T HIGUCHI

ISSCC DIGEST OF TECHNICAL PAPERS　28　86-87　1985

ISSN： 0193-6530
Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing Peer-reviewed

M. Kameyama, T. Hanyu, M. Esashi, T. Higuchi, T. Ito

Proc. IEEE International Symposium on Multiple-Valued Logic　15　226-232　1985
4値TゲートNMOS集積回路 Peer-reviewed

亀山充隆, 樋口龍雄, 江刺正喜, 羽生貴弘

電子通信学会論文誌　J67-D　(9)　1064-1065　1984

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Misc. 131

Nonvolatile field-programmable gate array using a standard-cell-based design flow

Daisuke Suzuki, Takahiro Hanyu

IEICE Transactions on Information and Systems　E104D　(8)　1111-1120　2021
Publisher: Institute of Electronics Information Communication Engineers
DOI： 10.1587/transinf.2020LOP0010 　

ISSN： 1745-1361 0916-8532
New-Paradigm Logic-LSI Design Technology Based on Nonvolatile Storage Functionality and Its Future Prospects

夏井雅典, 羽生貴弘

電子情報通信学会論文誌 C(Web)　J104-C　(6)　2021

ISSN： 1881-0217
パワーゲーティング機能付き不揮発RISC-V CPUの基礎検討

坂本佳介, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM)　2021　2021
Operating-Condition-Aware Power-Gating-Switch Control Technique and Its Application to Nonvolatile Logic LSI

ZHONG Fangcen, ZHONG Fangcen, 夏井雅典, 羽生貴弘

電子情報通信学会技術研究報告(Web)　121　(277(VLD2021 17-48))　2021

ISSN： 2432-6380
Power-Gating Switch-Control Technique for Nonvolatile Logic LSI

ZHONG Fangcen, 夏井雅典, 羽生貴弘

電子情報通信学会技術研究報告(Web)　120　(234(VLD2020 11-38))　2020

ISSN： 2432-6380
非相補抵抗状態検出機能を有する高信頼MTJベース不揮発性フリップフロップの構成

山岸源征, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM)　2019　2019
省エネルギー二値化ニューラルネットワーク向けMTJベース積和演算回路の構成

千葉智貴, 夏井雅典, 羽生貴弘

電子情報通信学会技術研究報告　119　(284(ICD2019 28-43))　2019

ISSN： 0913-5685
次世代IoT社会に向けた脳型LSI設計技術

夏井雅典, 羽生貴弘

電子情報通信学会大会講演論文集(CD-ROM)　2018　2018

ISSN： 1349-144X
不揮発量子化ニューラルネットワーク構成に基づく小型・超低消費電力XNOR回路の構成

千葉智貴, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM)　2018　2018
Prospects of an Error-Correction Technique of Intra-Chip Data Transmission Using Time-Series Feature

117　(277)　33-38　2017/11/06
Publisher: 電子情報通信学会
ISSN： 0913-5685
Special Section on Multiple-Valued Logic and VLSI Computing FOREWORD

Takahiro Hanyu

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS　E100D　(8)　1555-1555　2017/08

ISSN： 1745-1361
Spintronics Materials and Devices for Working Memory Technology FOREWORD

Hideo Ohno, Masafumi Yamamoto, Tetsuo Endoh, Yasuo Ando, Takahiro Hanyu, Kohei M. Itoh, Masaaki Tanaka, Seiji Mitani, Hitoshi Wakabayashi

JAPANESE JOURNAL OF APPLIED PHYSICS　56　(8)　2017/08

DOI： 10.7567/JJAP.56.080201 　

ISSN： 0021-4922

eISSN： 1347-4065
MTJ/MOSハイブリッド回路技術

Takahiro Hanyu

応用物理学会誌　86　(8)　662-665　2017/08
Publisher: 応用物理学会
ISSN： 0369-8009
ストカスティック演算に基づく省エネルギー脳型LSI設計技術

N. Onizawa, K. Matsumiya, T. Hanyu

IEICE Fundamental Review　11　(1)　28-39　2017/07
Publisher: IEICE
DOI： 10.1587/essfr.11.1_28 　
Stochastic Computation for Energy-Efficient Brainware LSI

30　202-207　2017/05/11
Publisher: [電子情報通信学会]
Measurement of Magnitude Response of FIR Filters Based on Stochastic Computation

30　38-40　2017/05/11
Publisher: [電子情報通信学会]
On Measurement Methods of Frequency Magnitude Responses for Digital Filters Based on Stochastic Computation

2017　(19)　1-6　2017/03/13
Publisher: 電気学会
視覚的注意計算モデルのハードウェア実装に向けた基礎的考察

西野海斗, 鬼沢直哉, 松宮一道, 塩入論, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM)　2017　2017
Design of High-Speed Low-Power Analog-to-Digital Converter for a Nonvolatile Micro-controller : High-Speed Low-Power Reference-Less SAR-ADC

116　(334)　51-56　2016/11/29
Publisher: 電子情報通信学会
ISSN： 0913-5685
Hardware Implementation of Stochastic Gammatone Filter

116　(95)　29-34　2016/06/16
Publisher: 電子情報通信学会
ISSN： 0913-5685
C-12-34 A Self-Terminated MTJ Write Driver and Its Application to a Random Number Generator

Suzuki Daisuke, Hanyu Takahiro

Proceedings of the IEICE General Conference　2016　(2)　107-107　2016/03/01
Publisher: The Institute of Electronics, Information and Communication Engineers
D-6-4 Design of a VLSI Processor with C-RAM-based Bit-Series/Bit-Parallel-Hybrid Structure

Yube Naoto, Mochizuki Akira, Hanyu Takahiro

Proceedings of the IEICE General Conference　2015　(1)　68-68　2015/02/24
Publisher: The Institute of Electronics, Information and Communication Engineers
D-10-5 Efficient fault injection method for soft error with asymmetric transition probability

Nebashi Ryusuke, Sakimura Noboru, Hanyu Takahiro, Sugibayashi Tadahiko

Proceedings of the IEICE General Conference　2015　(1)　156-156　2015/02/24
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-27 Design of an MTJ-Based True Random Number Generator with Probability-Variation Suppressing

Oosawa Satoshi, Konishi Takayuki, Onizawa Naoya, Hanyu Takahiro

Proceedings of the IEICE General Conference　2015　(2)　88-88　2015/02/24
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-15 DESIGN OF A POWER MANAGEMENT MODULE FOR A LOGIC-IN-MEMORY-BASED NONVOLATILE FPGA

Suzuki Daisuke, Tabata Yuki, Hanyu Takahiro

Proceedings of the IEICE General Conference　2015　(2)　76-76　2015/02/24
Publisher: The Institute of Electronics, Information and Communication Engineers
A 90-nm Three-terminal MRAM Embedded Nonvolatile Microcontroller for Standby-Power-Critical Applications

SAKIMURA Noboru, TSUJI Yukihide, NEBASHI Ryusuke, HONJO Hiroaki, MORIOKA Ayuka, ISHIHARA Kunihiko, KINOSHITA Keizo, FUKAMI Shunsuke, MIURA Sadahiko, KASAI Naoki, ENDOH Tetsuo, OHNO Hideo, HANYU Takahiro, SUGIBAYASHI Tadahiko

Technical report of IEICE. ICD　114　(175)　39-44　2014/08/04
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A 90-nm fully nonvolatile microcontroller employing three-terminal eMRAM cell into both nonvolatile logic and memory circuits was demonstrated. It achieved 20-MHz operating frequency, zero standby leakage by power gating technique and 120-ns wakeup time without forwarding of re-boot code from memory.
Fault-Tolerant Logical Integrated Circuits Based on Stochastic Computation

KATAGIRI Daisaku, ONIZAWA Naoya, HANYU Takahiro

IEICE technical report. Dependable computing　114　(22)　27-31　2014/04/25
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper introduces fault-tolerant logical integrated circuits based on stochastic computation. In the stochastic computation realized in a probabilistic domain, a probability is represented by a Bernoulli sequence that consists of a random sequence of bits. If an error occurs that flips a bit in the sequence, the probability is rarely affected because it is represented by the frequency of ones or zeros in the sequence. As a design example, an edge-detection circuit based on stochastic computation is designed using Verilog-HDL that shows comparison results with a conventional edge-detection circuit.
Low-Power IP Lookup LSI Based on Sparse Clustered Networks

ONIZAWA Naoya, GROSS Warren, HANYU Takahiro

IEICE technical report. Circuits and systems　113　(463)　193-198　2014/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, a novel architecture for low-power IP lookup engines is introduced. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry brute-force search of input addresses in TCAMs. The proposed hardware is designed under TSMC 65nm CMOS technology and is evaluated using HSPICE to show the energy efficiency compared to a conventional approach.
AT-1-3 Prospects of MTJ-Based Nonvolatile Logic-in-Memory VLSI

Hanyu Takahiro, Matsunaga Shoun, Suzuki Daisuke, Mochizuki Akira, Natsui Masanori

Proceedings of the IEICE General Conference　2014　"SS-16"　2014/03/04
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-48 Compact and Low Power Nonvolatile TCAM with High Resistance-Variation Tolerance

Matsunaga Shoun, Mochizuki Akira, Hanyu Takahiro

Proceedings of the IEICE General Conference　2014　(2)　112-112　2014/03/04
Publisher: The Institute of Electronics, Information and Communication Engineers
符号化技術に基づく不揮発LSIの低電力化に関する検討

阿久津赳明, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集(CD-ROM)　2014　2014
A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA

SUZUKI Daisuke, NATSUI Masanori, MOCHIZUKI Akira, HANYU Takahiro

Technical report of IEICE. ICD　113　(323)　49-53　2013/11/27
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, a design methodology for realizing power efficient nonvolatile FPGA (NVFPGA) using magnetic tunnel junction (MTJ) devices is discussed. Since circuit information in the NVFPGA remains without power supply, wasted standby power is eliminated. The relationship between the ultra low-power standby capability and MTJ read/write access power are discussed. As a typical application, an adder with a register is implemented on the proposed NVFPGA, which results in a total power reduction of 62% compared to that of an SRAM-based FPGA.
1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Gained Power Gating Technique : Achieves 1.0ns/200ps Wake-Up/Power-Off Times

ENDOH Tetsuo, OHSAWA Takashi, KOIKE Hiroki, MIURA Sadahiko, HONJO Hiroaki, TOKUTOME Keiichi, IKEDA Shoji, HANYU Takahiro, OHNO Hideo

Technical report of IEICE. ICD　113　(1)　27-32　2013/04/11
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A 1Mb embedded memory was designed and fabricated using a cell consisting of four NFETs and two spin-transfer torque magnetic tunnel junctions (STT-MTJs) which is a nonvolatile memory device with excellent write endurance. A 32b fine-grained power gating technique is applied to achieve a fast access/cycle times along with a low standby and operation powers. Since the 4T2MTJ cell size is defined by its four NFETs with the two MTJs put on them, the cell has a potential to become smaller than the SRAM cell. It was shown that the 4T2MTJ STT-RAM macro can be smaller than the SRAM counterpart by scaling the technology to 25nm-45nm and beyond, depending on its scaling scenarios, due to the MTJ switching current reduction by the scaling.
シリコン不揮発性メモリ技術の限界を突破するスピントルク注入型磁気メモリの最新動向

遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男

電子情報通信学会誌　95　(平成24年11月号)　986-991　2012/11/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5693
STT-MRAM for future high performance Nonvolatile memory

遠藤哲郎, 大澤隆, 小池洋紀, 羽生貴弘, 笠井直記, 大野英男

電子情報通信学会誌　(平成24年11月号)　2012/11/01
Design of MTJ-Based Fully-Parallel Nonvolatile TCAM

MATSUNAGA Shoun, HANYU Takahiro

Technical report of IEICE. ICD　112　(15)　43-48　2012/04/16
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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Ternary content-addressable memories (TCAMs) are specific hardware accelerators which can realize high-speed fully-parallel pattern matching. In the TCAMs, higher density and lower energy consumption have been required. In this paper, we propose a compact 6-transistor/2-magnetic-tunnel-junction (6T-2MTJ)-based fully-parallel nonvolatile TCAM cell circuit where nonvolatile storage function and logic function are compactly merged, and 9T-2MTJ-based high-speed TCAM cell circuit where a sense amplifier is embedded to increase driving capability of the cell circuit. By using these cell circuits in combination with match-line segmentation scheme, active energy consumption can be greatly reduced. Moreover, standby energy consumption can be cut off due to their nonvolatility.
C-12-7 Design of a Fine-Grained Pipelined Circuit Using a Nonvolatile Logic Gate

Matsunaga Shoun, Hanyu Takahiro

Proceedings of the IEICE General Conference　2012　(2)　79-79　2012/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers
Design of a High-Density and Low-Power Nonvolatile Logic Element Using MTJ Devices

SUZUKI Daisuke, HANYU Takahiro

Technical report of IEICE. ICD　111　(388)　15-19　2012/01/19
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A compact nonvolatile logic element (NVLE) using a magnetic-tunnel-junction (MTJ) and MOS-hybrid structure is proposed for a compact, low-power field-programmable gate array. The combination of an MTJ/MOS-hybrid structure and dynamic current-mode logic (DyCML) makes it possible to realize both logic function and storage function with a compact hardware. Moreover, the DyCML-based circuitry also makes it possible to perform a high-speed switching operation with low active-power dissipation. In fact, the proposed 4-input NVLE reduces transistor counts to 55% with the switching delay and he active power reduction to 83% and 64% respectively, compared to those of a conventional MTJ-based nonvolatile-SRAM-based implementation with a standby-power elimination capability during an idle phase.
Design of a High-Density and Low-Power Nonvolatile Logic Element Using MTJ Devices

2012　(3)　1-5　2012/01/12
スピンを用いた不揮発ロジックの展望

羽生貴弘, 夏井雅典

技術総合誌 OHM　99　(1)　28-30　2012/01
Publisher: オーム社
ISSN： 0386-5576
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

KAWANO Takao, ONIZAWA Naoya, Matsumoto Atsushi, HANYU Takahiro

Technical report of IEICE. VLD　111　(324)　215-220　2011/11/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, a new fine-grained power-gating technique is proposed. Fine-grained power-gating technique has the potential to much leakage power dissipation of idle circuit blocks. A fine-grained power-gating controller tends to be large because of complexity of power-gating control. Since asynchronous signals generated by asynchronous controllers are local control signals, these signals indicate conditions of circuit blocks. Therefore, a fine-grained power-gating technique with a small power-gating controller is realized by sharing the asynchronous controller in asynchronous pipelined system. The proposed power-gating technique is applied to a Network-on-Chip (NoC) router. As a result, leakage power reduction of the NoC router is realized.
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

KAWANO Takao, ONIZAWA Naoya, Matsumoto Atsushi, HANYU Takahiro

IEICE technical report. Dependable computing　111　(325)　215-220　2011/11/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, a new fine-grained power-gating technique is proposed. Fine-grained power-gating technique has the potential to much leakage power dissipation of idle circuit blocks. A fine-grained power-gating controller tends to be large because of complexity of power-gating control. Since asynchronous signals generated by asynchronous controllers are local control signals, these signals indicate conditions of circuit blocks. Therefore, a fine-grained power-gating technique with a small power-gating controller is realized by sharing the asynchronous controller in asynchronous pipelined system. The proposed power-gating technique is applied to a Network-on-Chip (NoC) router. As a result, leakage power reduction of the NoC router is realized.
Fault-Detectable 2-Color Code for Asynchronous Bidirectional Communication Links

MATSUMOTO Atsushi, ONIZAWA Naoya, HANYU Takahiro

IEICE technical report. Dependable computing　111　(325)　37-42　2011/11/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, we propose an encoding scheme for multiple-valued two-color data representation with open-wire fault detectability in bidirectional asynchronous links. Correct signal states are detected by using the summation of current signals in a data transmission based on multiple-valued encoding. Therefore, by using proposed "Complementary Encoding" based data representation, a data transmission is always stopped when there is any open-wire fault in the link. As a result, open-wire fault can be detected. In this paper, mathematical proof of open-wire fault detectability by using proposed encoding is discussed. Furthermore, as a simple application, an asynchronous bidirectional link based on proposed encoding is demonstrated.
Controller-Sharing Based Asynchronous Power-Gating Scheme and Its Application

2011　(38)　1-6　2011/11/21
Design of a Fully-Parallel High-Density Nonvolatile TCAM Using MTJ Devices

KATSUMATA Akira, MATSUNAGA Shoun, HANYU Takahiro

Technical report of IEICE. SDM　111　(281)　63-68　2011/11/10
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685
MTJ素子に基づく不揮発性ロジックインメモリVLSIアーキテクチャの展望

羽生貴弘

まぐね/Magnetics Jpn.　6　(1)　23-28　2011/01
C-12-10 非同期式チップ間リンク速度の定量的評価手法(センサ・有線通信,C-12.集積回路,一般セッション)

鬼沢直哉, 羽生貴弘

電子情報通信学会ソサイエティ大会講演論文集　2010　(2)　71-71　2010/08/31
Publisher: 一般社団法人電子情報通信学会
C-007 Asynchronous Communication Scheme based on Multiple-valued 1-color Encoding and Its Application toward Network-on-Chip

Matsumoto Atsushi, Onizawa Naoya, Hanyu Takahiro

9　(1)　385-386　2010/08/20
Publisher: Forum on Information Technology
Fault-Resilient Multiple-Valued Asynchronous Data-Transfer Scheme

MATSUMOTO Atsushi, ONIZAWA Naoya, HANYU Takahiro

IEICE technical report　110　(168)　7-11　2010/07/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, we propose an asynchronous data-transmission scheme which is robust against a wire-fault on the communication links. Even if a wire-fault occurs, the quantity of data-transmission can be kept as same as it before the wire-fault by utilizing data representation of multiple-valued encoding which is defined on the rest non-fault wires. In other words, the capability of data-transmission before and after the wire-fault can be maintained in the proposed scheme. Furthermore, to clarify the usefulness of the proposed scheme, the detailed mechanism of the proposed scheme through the three-wire data-transmission and its hardware implementation example by utilizing multiple-valued current-mode circuit technique are shown.
Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array

SUZUKI Daisuke, NATSUI Masanori, IKEDA Shoji, HASEGAWA Haruhiro, MIURA Katsuya, HAYAKAWA Jun, ENDOH Tetsuo, OHNO Hideo, HANYU Takahiro

IEICE technical report　110　(9)　47-52　2010/04/15
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnetic Tunnel Junction) device-based logic technology. To utilize a capability of MTJ devices, the combinational logic circuitry is implemented based on differential current-mode logic methodology. Since the circuit performs current-mode logic operations under low voltage swing, the variation of current flows through MTJ devices can be applied as logic signals directly with no signal amplification. It results in a compact circuit implementation. The proposed LUT circuit fabricated by a 0.14μm CMOS/MTJ-hybrid process achieves area reduction by 2/3 compared to a conventional SRAM-based one, and complete elimination of standby power dissipation.
Accurate Asynchronous Network-on-Chip Simulation Based on Reactive Delay Model

FUNAZAKI Tomoyoshi, ONIZAWA Naoya, MATSUMOTO Atsushi, HANYU Takahiro

IEICE technical report　110　(3)　9-14　2010/04/06
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip(NoC)architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a reactive delay model is proposed for implementing an appropriate asynchronous NoC system. While the unit delay between circuit blocks at every pipeline stage is constant in the conventional cycle-accurate simulator, which causes poor accuracy, the unit delay between circuit blocks in the proposed approach is determined independently by its desirable logic function. The use of this "reactive delay" model makes it accurate to simulate asynchronous NoC systems. As a design example, a 16-core asynchronous Spidergon NoC system is simulated by the conventional cycle-accurate and the proposed simulator whose results, such as latency and throughput, are validated with a highly precise transistor-level simulation result. As a result, the proposed simulator achieves almost the same accuracy as one of the transistor-level simulators with the simulation speed comparable to the cycle-accurate simulator.
A-1-44 Design of Fully-Parallel LDPC Decoders Based on Stochastic Computation

Onizawa Naoya, Hanyu Takahiro

Proceedings of the IEICE General Conference　2010　44-44　2010/03/02
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-70 Design of a Nonvolatile Functional Lookup Table Circuit

Suzuki Daisuke, Hanyu Takahiro

Proceedings of the IEICE General Conference　2010　(2)　147-147　2010/03/02
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-37 Design of a High-Density Nonvolatile Binary Content-Addressable Memory Based on Magnetic Tunnel Junction Devices

Matsunaga Shoun, Hanyu Takahiro

Proceedings of the IEICE General Conference　2010　(2)　114-114　2010/03/02
Publisher: The Institute of Electronics, Information and Communication Engineers
MTJ素子を用いた不揮発性論理回路とその応用

羽生貴弘, 松永翔雲, 夏井雅典

応用物理学関係連合講演会講演予稿集(CD-ROM)　57th　2010
完全並列形不揮発TCAM向けワード回路の構成

勝俣翠, 松永翔雲, 松永翔雲, 夏井雅典, 夏井雅典, 羽生貴弘, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2010　2010
C-036 Design of a Circuit-Level Verification Environment for Asynchronous Network-on-Chip

Matsumoto Atsushi, Funazaki Tomoyosi, Onizawa Naoya, Hanyu Takahiro

8　(1)　519-520　2009/08/20
Publisher: Forum on Information Technology
高信頼オンチップ非同期データ転送技術に関する一検討

鬼沢直哉, 松本敦, 羽生貴弘, 米田友洋

電子情報通信学会技術研究報告　DC-2009　(18)　1-6　2009/08
Impact of Silicon Technology in "Beyond CMOS" World

ENDOH Tetsuo, HANYU Takahiro

IEICE technical report　109　(133)　73-78　2009/07/09
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In recent years, the Beyond CMOS technology is studied in addition to More Moore technology and More than Moore technology, as current CMOS technology face to a wall. However, the beyond CMOS technology still has a lot of problems as the power saving and reliability, etc. Therefore, the continuously development of the silicon technology and fusion technology with CMOS technology and beyond CMOS technology are still indispensable. From above viewpoints, in this paper, the impact of the silicon technology in the Beyond CMOS technology is discussed as following two focuses. First, for achieving the super-low power consumption logic, new nonvolatile logic (spin logic) technology is discussed. Next, for achieving a large capacity and high reliability at the same time, new 3D structured memory with Vertical cell is discussed.
二次元LUTを用いた電流モード多値回路向け高速・高精度動作検証手法の一考察

有光貴志, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会講演論文集　2009　2009
An approach to tolerating delay faults based on asynchronous circuits

YONEDA Tomohiro, IMAI Masashi, MATSUMOTO Atsushi, HANYU Takahiro, NAKAMURA Yuichi

IEICE technical report　DC-2008　(10)　55-60　2008/04
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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Recent advances in semiconductor process technologies cause new types of faults, which should be handled in order to obtain large and dependable VLSI systems. This report focuses on a type of faults that are caused by the stress during the operation and degrade performance of the circuit components. We analyze the influence of those delay faults in a data-flow level of bardware accelerators showing that asynchronous circuits are more robust than synchronous circuits with respect to such delay faults, and propose an approach to tolerating them using asynchronous circuit technologies and operational unit reallocation.
Logic integrated circuit using tunneling-magnetoresistive devices -Next-generation Ligic-LSI paradigm using nonvolatile devices-

Takahiro Hanyu

Applied Physics　76　(12)　1388-1393　2007/12
Publisher: 応用物理学会
ISSN： 0369-8009
非同期式回路のFPGA実現とその評価

松本敦, 米田友洋, 羽生貴弘

電子情報通信学会技術研究報告　DC-2007　(10)　25-30　2007/08
C-12-4 Research Institute of Electrical Communication, Tohoku University

Takahashi Tomohiro, Hanyu Takahiro

Proceedings of the IEICE General Conference　2007　(2)　83-83　2007/03/07
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-8 Implementation of an LDPC Decoder LSI Based on Multiple-Valued Asynchronous Data-Transfer Scheme

Onizawa Naoya, Hanyu Takahiro

Proceedings of the IEICE General Conference　2007　(2)　87-87　2007/03/07
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-12 FPGA Implementation of a Lattice-Gas Cellular Array VLSI for Fluid Analysis

Suzuki Daisuke, Hanyu Takahiro

Proceedings of the IEICE General Conference　2007　(2)　91-91　2007/03/07
Publisher: The Institute of Electronics, Information and Communication Engineers
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

MOCHIZUKI Akira, SHIRAHAMA Hirokatsu, HANYU Takahiro

IEICE Trans. Electron., C　89　(11)　1591-1597　2006/11/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18μm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic

ONIZAWA Naoya, HANYU Takahiro

IEICE transactions on electronics　89　(11)　1575-1580　2006/11/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18μm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.
Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing

TAKAHASHI Tomohiro, HANYU Takahiro

IEICE Trans. Electron, C　89　(11)　1598-1604　2006/11/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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This paper presents an asynchronous multiple-valued current-mode data-transfer controller chip based on a 1-phase dual-rail encoding technique. The proposed encoding technique enables "one-way delay" asynchronous data transfer because request and acknowledge signals can be transmitted simultaneously and valid states are detected by calculating the sum of dual-rail codewords. Since a key component, a current-to-voltage conversion circuit in a valid-state detector, is tuned so as to obtain a sufficient voltage range to improve switching speed of a comparator, signal detection can be performed quickly in spite of using 6-level signals. It is evaluated using HSPICE simulation with a 0.18-μm CMOS that the throughput of the proposed circuit based on the 1-phase dual-rail scheme attains 435Mbps/wire which is 2.9 times faster than that of a CMOS circuit based on a conventional 4-phase dual-rail scheme. The test chip is fabricated, and the asynchronous data-transfer behavior of the proposed scheme is confirmed.
High-Performance Asynchronous Data Transfer VLSI Based on Multiple-Valued Dual-Rail Encoding

TAKAHASHI Tomohiro, MIZUSAWA Kazuyasu, HANYU Takahiro

2006　(111)　141-146　2006/10/27
Publisher: Information Processing Society of Japan (IPSJ)
ISSN： 0919-6072

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A full-duplex asynchronous communication scheme based on one-phase dual-rail encoding is proposed for on-chip high-speed communication. Since control signals and data from mutual modules are multiplexed using a multi-level dual-rail codeword, full-duplex data transfer without clocks can be realized by using only two wires;one wire per bit. As compared to uni-directional scheme, the increased level of multiple-valued signal is slight because different valid states are assigned on a common codeword. As a result, it is evaluated by using a 0.18-μm CMOS technology that the throughput and energy dissipation of the proposed asynchronous scheme attains a value of 1.18Gb/s/wire and 0.78pJ/bit, respectively, at a wire length of 1mm.
Complementary Ferroelectric Capacitor Logic and its Application to Fully Parallel Arithmetic VLSI

MATSUNAGA Shoun, HANYU Takahiro

Technical report of IEICE. VLD　105　(148)　61-65　2005/06/21
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, we propose a Complementary Ferroelectric Capacitor Logic-in-Memory circuit that makes it possible easily to realize fully parallel structures with a quick-on function. The Complementary Ferroelectric Capacitor Logic-in-Memory circuit can realize fully parallel structures compactly without a overhead of storage circuits, because the realization of a logic function using a ferroelectric capacitor enables to merge a non-volatile storage function and a logic function compactly at the device level. Since the result of a logic operation is stored in the ferroelectric capacitor automatically, the voltage source can be done switching on-off at any time, furthermore a quick-on VLSI can be realize easily. As a typical fully parallel arithmetic VLSI using the proposesd circuit, a fine-grain pipelined adder is discussed, and its performance is compared with that of a corresponding CMOS implementation.
Design and Evaluation of a Bit-Parallel Magnitude-Comparison CAM Based on TMR Logic

SHOJI Kohei, HANYU Takahiro

Technical report of IEICE. VLD　105　(148)　55-59　2005/06/21
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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The paper presents a new circuit style called "TMR logic" combining TMR (tunneling magnetoresistive) devices with connected MOS pass-transistor network, which results merging storage function into logic circuit plane with a small area. Since the TMR device can be regarded as a variable resistor with non-volatile storage capability, the logic function can be realized by series and parallel connection of the TMR devices and transistors. As a typical example, a content-addressable memory (CAM) where magnitude-compare in a bit-parallel fashion simply implemented based on TMR logic and its performance improvement is also demonstrated.
C-12-11 Design of a High-Performance PPG Based on Multiple-Valued Differential Logic

MOCHIZUKI Akira, SHIRAHAMA Hirokatsu, HANYU Takahiro

Proceedings of the IEICE General Conference　2005　(2)　74-74　2005/03/07
Publisher: The Institute of Electronics, Information and Communication Engineers
Multiple-valued logic as a new computing paradigm - A brief survey of Higuchi's research on multiple-valued logic

M Kameyama, T Hanyu, T Aoki

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　11　(5-6)　407-436　2005

ISSN： 1542-3980

eISSN： 1542-3999
Introduction: Special issue to recognize T. Higuchi's contributions to multiple-valued VLSI computing

M Kameyama, T Hanyu, T Aoki

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　11　(5-6)　I-II　2005

ISSN： 1542-3980
Multiple-Valued Current-Mode Differential-Pair Circuit for a High-Speed/High-Reliability Arithmetic VLSI System

MOCHIZUKI Akira, KITAMURA Takeshi, HANYU Takahiro

Technical report of IEICE. ICD　104　(522)　31-36　2004/12/17
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A new multiple-valued current-mode circuit based on complementary differential logic is proposed for the crosstalk-noise-free arithmetic VLSI while maintaining a high-speed operation. Since a fully complementary operation is performed by using two differential-pair circuits (DPCs), only one of the DPCs makes an error at the most, even if common-mode crosstalk noise is applied to dual-rail input lines. The above complementary duplication of DPCs makes the noise effect reduced by summing up the outputs from two DPCs. Consequently, the noisy outputs from the DPCs are completely recovered by a Schmitt-trigger circuit. As a typical design example of arithmetic VLSIs, it is discussed about a crosstalk-free radix-2 signed-digit full adder in a fabricated chip.
Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer

MOCHIZUKI Akira, TAKEUCHI Takashi, HANYU Takahiro

IEICE transactions on electronics　87　(11)　1915-1922　2004/11/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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A new common-bus architecture with temporal and spatial parallel access capabilities under wire-resource constraint is proposed to transfer vast quantities of data between modules inside a VLSI chip. Since bus controllers are distributed into modules, the proposed bus architecture can directly transfer data from one module to another without any central bus control unit like a Direct Memory Access (DMA) controller, which enables to reduce communication steps for data transfer between modules. Moreover, when a start address and the number of block data in both source/destination modules are determined at the first step of a data-transfer scheme, no additional address setting for the data transfer is required in the rest of the scheme, which allows us to use all the wire resources as only the "data bus." Therefore, the bus function is dynamically programmed, which results in achieving high throughput of bus communication. For example, in case of a 64-line common bus, it is evaluated that the maximum data throughput in the proposed architecture with dynamic bus-function programming is four times higher than that in the conventional DMA bus architecture with fixed 32-bit-address/32-bit-data buses.
Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer

TAKAHASHI Tomohiro, ONIZAWA Naoya, HANYU Takahiro

IEICE Trans. Electron., C　87　(11)　1928-1934　2004/11/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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This paper presents an asynchronous data transfer scheme using 2-color 2-phase dual-rail encoding based on a differential operation and its circuit realization. The proposed encoding enables seamless asynchronous data transfer without inserting a spacer, because each logic value is represented by two kinds of codewords with dual-rail, called "color" data. Since the difference x-x' between components of a codeword (x, x') becomes constant in every valid state, the data-arrival state can be detected by calculating the difference x-x'. From the viewpoint of circuit implementation, during the state transition, since the dual-rail x and x' are defined so as to transit differentially, the compatibility with a comparator using a differential amplifier becomes high, which results in reduction of the cycle time. It is evaluated using HSPICE simulation with a 0.18μm CMOS technology that communication speed using the proposed dual-rail encoding becomes 1.4 times faster than that using conventional dual-rail encoding.
Low-Power Logic-in-Memory VLSI Using a Complementary TMR/Transistor Network

MOCHIZUKI Akira, KIMURA Hiromitsu, HANYU Takahiro

Technical report of IEICE. ICD　104　(24)　37-42　2004/04/16
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A logic-in-memory architecture using tunneling magnetoresistive(TMR) devices is proposed to realize a low-power fine-grain arithmetic VLSI. Since the TMR device can be regarded as a variable resistor with non-volatile storage capability, the logic function can be realized by series and parallel connection of the TMR devices and transistors. Moreover, the use of the complementary dynamic logic style makes it possible to perform the high-speed and low-power operations. A design example of a fine-grain arithmetic circuit, such as an SAD unit, is discussed, and its advantage is demonstrated.
Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control

MOCHIZUKI Akira, HANYU Takahiro

IEICE Trans. Electron., C　87　(4)　582-588　2004/04/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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A new multiple-valued current-mode (MVCM) logic circuit using substrate bias control is proposed for low-power VLSI systems at higher clock frequency. Since a multi-level threshold value is represented as a threshold voltage of an MOS transistor, a voltage comparator is realized by a single MOS transistor. As a result, two basic components, a comparator and an output generator in the MVCM logic circuit can be merged into a single MOS differential-pair circuit where the threshold voltages of MOS transistors are controlled by substrate biasing. Moreover, the leakage current is also reduced using substrate bias control. As a typical example of an arithmetic circuit, a radix-2 signed-digit full adder using the proposed circuit is implemented in a 0.18-μm CMOS technology. Its dynamic and static power dissipations are reduced to about 79 percent and 14 percent, respectively, in comparison with those of the corresponding binary CMOS implementation at the supply voltage of 1.8 V and the clock frequency of 500MHz.
SC-11-11 Design of a Low-Power Multiple-Valued Integrated Circuit Based on Body Bias Control

Mochizuki Akira, Hanyu Takahiro

Proceedings of the IEICE General Conference　2004　(2)　"S-71"-"S-72"　2004/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
SC-11-13 Low-Power Logic-in-Memory Circuit Technique Using TMR Devices

Kimura Hiromitsu, Ibuki Mitsuru, Hanyu Takahiro

Proceedings of the IEICE General Conference　2004　(2)　"S-75"-"S-76"　2004/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
SC-11-12 Fabrication of a High-Speed Asynchronous Data Transfer LSI Based on Current-Mode Control-Signal Multiplexing

Takahashi Tomohiro, Hanyu Takahiro

Proceedings of the IEICE General Conference　2004　(2)　"S-73"-"S-74"　2004/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
Intra-Chip High-Speed Data Transfer Scheme Based on Autonomous Distributed Bus Control

TAKEUCHI Takashi, MOCHIZUKI Akira, HANYU Takahiro

Technical report of IEICE. ICD　103　(648)　33-37　2004/01/30
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a new bus architecture for high-speed data transfer with vast quantities of data inside a VLSI chip. In the proposed bus architecture, since a bus is utilized as an "address bus" or a "data bus" in a time-sharing fashion, data can be transferred from one module to another with the maximum width of bus. Moreover autonomous distributed bus control in each module makes it possible to transfer data directly between modules, which results in high throughput of bus communication. It is demonstrated in case of a 64-line bus that the peak throughput of the proposed bus control is about four times higher than that of direct memory access control.
Logic-in-Memory VLSI Using Non-Volatile Devices

KIMURA Hiromitsu, HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. ICD　103　(2)　23-27　2003/04/03
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A logic-in-memory architectuire using tunneling magnetoresistive (TMR) devices is presented to realize a data-transfer bottleneck-free VLSI processor. Since the resistivity of the TMR device changes depending on stored data, a switching function is realized by voltage division with cascade connection of the TMR devices where complementary data are stored. TMR non-volatile storage elements can be distributed over logic-circuit plane with small area overhead, which results in compact logic-in-memory VLSI while maintaining a high-speed processing capability. An application to a content-addressable memory is discussed, and their advantages are demonstrated.
Ferroelectric Nonvolatile Logic Devices

FUJIMORI Yoshikazu, NAKAMURA Takashi, TAKASU Hidemi, KIMURA Hiromitsu, HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. SDM　102　(732)　25-30　2003/03/11
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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Ferroelectric Nonvolatile Logic is proposed. It is low power and dynamic reconfigurable logic technologies by storing logic state or circuit configuration nonvolatility. Cost of LSIs can be decreased by switching circuit blocks. The fundamental device of nonvolatile latch was developed and characterized. Moreover, advanced functional device that can do operation at a ferroelectric capacitor was also fabricated. The durability and the low power were confirmed.
Prospects of System LSI Based on Ferroelectric Logic-in-Memory Architecture

KAMEYAMA Michitaka, HANYU Takahiro, KIMURA Hiromitsu

Technical report of IEICE. ICD　102　(525)　47-52　2002/12/12
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A ferroelectric-based logic-in-memory architecture is presented for a communication-bottleneck-free system LSI. A logic operation is performed by hysteresis characteristic and capacitive coupling of a ferroelectric capacitor, so that switching and storage functions are merged into a ferroelectric capacitor. Ferroelectric storage elements can be distributed over logic-circuit plane with small area overhead, which results in compact and low-power logic-in-memory VLSI while maintaining a high-speed processing capability. The application to a 54×54-bit pipelined multiplier and a 32-bit content-addressable memory are discussed, and their advantages are demonstrated.
High-Performance Multiple-Valued Integrated Circuit Based on Source-Coupled Logic and Its Application to an Image Processing VLSI Processor

IKE Tsukasa, HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. DSP　102　(400)　45-50　2002/10/18
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In multiple-valued current-mode circuits, the number of wires and the critical-path length can be greatly reduced by integrating multi-bit information into a single multiple-valued current-mode signal. However, the circuit technology which improves the performance of the basic gates is needed and required because the delay of the each basic gate is large. In this paper, the novel high-performance multiple-valued integrated circuit using differential-pair circuits, which has a high current-driving capability, as a switching gate is proposed. Moreover, the image processing VLSI processor is designed and evaluated to confirm the usefulness of the proposed circuit technology.
Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit

KIMURA Hiromitsu, HANYU Takahiro, KAMEYAMA Michitaka

IEICE transactions on electronics　85　(10)　1814-1823　2002/10/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-μm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.
Design of Ferroelectric-Based Logic-in-Memory VLSI

KIMURA Hiromitsu, HANYU Takahiro, KAMEYAMA Michitaka, FUJIMORI Yoshikazu, NAKAMURA Takashi, TAKASU Hidemi

Technical report of IEICE. ICD　102　(3)　7-12　2002/04/05
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A ferroelectric-based logic-in-memory VLSI is proposed to implement a highly-parallel VLSI processor compactly. Since the state-transition scheme of remnant polarization in a ferroelectric capacitor is utilized to perform switching functions, the storage and switching function is merged into a ferroelectric capacitor. The use of a proposed circuit makes it possible to distribute a high-speed storage elements over logic-circuit plane with a small area overhead. As a typical example, a 250MHz 54×54-bit pipelined multiplier is demonstrated with 7.82mm^2 estimated area in a 0.6μm ferroelectric/CMOS technology.
Low-Power VLSI Architecture Based on Adaptive Power-Supply Voltage Control

Yamaguchi Michitomo, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the IEICE General Conference　2002　(2)　103-103　2002/03/07
Publisher: The Institute of Electronics, Information and Communication Engineers
Design of a Multiple-Valued Domino Integrated Circuit Based on Source-Coupled Logic

MOCHIZUKI Takayoshi, HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. ICD　101　(386)　61-66　2001/10/19
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a multiple-valued domino circuit based on dual-rail source-coupled logic (SCL). The dual-rail SCL circuit operates with a small input-voltage swing while maintaining high current-driving capability. Since current-mode linear summation is performed by wiring, the critical path length can be shortened and device counts can be reduced. The use of precharge-evaluate logic in the proposed circuit makes the steady current flow cut off, thereby greatly saving power dissipation. As a typical application, it is demonstrated that the performance of a 54x54-bit signed-digit multiplier using the proposed circuit is 1.6-times faster than that of a corresponding binary CMOS implementation under the same power dissipation.
Design of a Logic-in-Memory VLSI for Gate-Level Pipelining

Kimura Hiromitsu, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the Society Conference of IEICE　2001　(2)　69-69　2001/08/29
Publisher: The Institute of Electronics, Information and Communication Engineers
Desigh of a Multiple-Valued Logic-in-Memory. VLSI Using Source-Coupled Circuits

Kogawa Tsuyoshi, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the Society Conference of IEICE　2001　(2)　70-70　2001/08/29
Publisher: The Institute of Electronics, Information and Communication Engineers
Design of a High-Performance Multiple-Valued Current-Mode Integrated Circuit

Ike Tsukasa, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the Society Conference of IEICE　2001　(2)　76-76　2001/08/29
Publisher: The Institute of Electronics, Information and Communication Engineers
Multiple-Valued Logic-Memory VLSI Circuit Based on Dynamic Storage

Kimura Hiromitsu, Hanyu Takahiro, Kameyama Michitaka, Koike Yasukatu

Proceedings of the IEICE General Conference　2001　(2)　115-115　2001/03/07
Publisher: The Institute of Electronics, Information and Communication Engineers
Design of a Multiple-Valued Integrated Circuit Based on Source-Coupled Logic

Ike Tsukasa, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the IEICE General Conference　114-114　2001
Publisher: The Institute of Electronics, Information and Communication Engineers
Dynamic-Storage-Based Multiple-Valued Logic-in-Memory Circuit and Its Aplication

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

Proc. 2nd Korea-Japan Joint Symposium on Multiple-Valued Logic　147-151　2001
Dynamic-Storage-Based Logic-in-Memory VLSI with Local Computability

KIMURA Hiromitsu, HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. VLD　100　(473)　53-58　2000/11/23
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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A new logic-in-memory VLSI for synchronous sequential circuits is proposed to localize data transfer between combinational logic circuits and storage elements. The combination of a locally computable state assignment and a dynamic storage-based-pass-transistor network, in which state registers are distributed over a combinational circuit, makes it possible to realize compact sequential circuits with local data transfer. As a typical application, a modulo-4 counter based on one-hot coding is designed by using the proposed circuit. Its performance is superior to that of corresponding binary CMOS implementation under a 0.35-μm CMOS technology.
Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Using High-Speed Current Mirrors

Ike Tsukasa, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the Society Conference of IEICE　2000　(2)　100-100　2000/09/07
Publisher: The Institute of Electronics, Information and Communication Engineers
Self-Checking Multiple-Valued Integrated Circuit Based on Dual-Rail Current-Mode Logic and Its Application to a High-Performance Arithmetic VLSI System

IKE Tsukasa, HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. FTS　100　(30)　17-24　2000/04/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a new totally self-checking circuit based on dual-rail multiple-valued current-mode(MVCM)logic, where almost all the basic components except a differential-pair circuit have been already duplicated, which results in small hardware overhead compared with a non-self-checking circuit based on dual-rail MVCM logic.It is demonstrated in a 0.35-μm CMOS technology that the performance of the 8×8-bit multiplier based on the proposed self-checking circuit is superior to that of full duplication of the non self-checking circuit based on dual-rail MVCM logic in terms of chip area and dynamic power dissipation under the same switching delay.
Two-Color Two-Rail Current-Mode Multiple-Valued Asynchronous VLSI System and Its Applications

HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. FTS　100　(30)　9-15　2000/04/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a new asynchronous data-transfer scheme based on two-color two-rail complementary coding, which is suitable for a multiple-valued current-mode VLSI circuit.Two kinds of R-valued two-rail complementary signals, called 'two-color two-rail codes, 'which represent'data values, 'are used in odd and even phases, respectively.The sum of R-valued two-rail complementary values in an odd phase is a constant(R-1), while the sum of R-valued two-rail complementary values in an even phase is also a constant 3(R-1).The difference of these constant values in the two-color coding makes it easy to detect a data-arrival state from a data-transition state without spacers.Moreover, basic components to realize the above asynchronous VLSI system, a signal-state detector to detect a data-arrival state, and a two-color code generator to produce two-color two-rail signals can be easily designed by a multiple-valued current-mode circuit technology based on dual-rail differential logic.Finally, it is also shown that the proposed two-color two-rail coding is suitable for the realization of a totally self-checking VLSI system.
Self-Checking VLSI System Based on Dual-Rail Multiple-Valued Current-Mode Logic

T. Ike, T. Hanyu, M. Kameyama

Trans. IEICE C　J83-C　(4)　318-325　2000
Asynchronous Current-Mode Multiple-Valued VLSI System Based on Two-Color Two-Rail Coding

T. Hanyu, M. Kameyama

Trans. IEICE C　J83-C　(6)　463-470　2000
High-Level Synthesis of a Logic-in-Memory VLSI system with an Interconnection Delay between Modules

59　3-4　1999/09/28
Publisher: 情報処理学会
Asynchronous Current-Mode Multiple-Valued VLSI System Based on Two-Color Two-Rail Coding

HANYU Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. ICD　99　(316)　41-47　1999/09/21
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685
Design of a Multiple-Valued Asynchrous VLSI System Based on Two-Color Two-Rail Coding

HANYU Takahiro, KAMEYAMA Michitaka

Proceedings of the IEICE General Conference　1999　(2)　124-124　1999/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
High-Level Synthesis of a Logic-in-Memory VLSI System with the Minimum Number of Shared Buses

HORII Takashi, HANYU Takahiro, KAMEYAMA Michitaka

Proceedings of the IEICE General Conference　1999　109-109　1999/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
Automated Design of a Multiple-Valued VLSI System Using a Binaly Logic Synthesis CAD

SUGIYAMA Tomohiro, HANYU Takahiro, KAMEYAMA Michitaka

Proceedings of the IEICE General Conference　1999　108-108　1999/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
Design of a Multiple-Valued Logic-in-Memory VLSI Using Floating-Gate MOS Transistors

HANYU Takahiro, TERANISHI Kaname, KAMEYAMA Michitaka

Technical report of IEICE. ICD　98　(66)　1-8　1998/05/22
Publisher: The Institute of Electronics, Information and Communication Engineers

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A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor. so that a single floating-gate MOS transistor is effectively employed to merge multiple-valued threshold-literal and pass-switch functions. Since. multiple-valued pass-transistor network is realized by multiple-valued threshold-literal and pass-switch functions, it can be designed compactly by using floating-gate MOS transistors. As an example of typical logic-in-memory VLSI systems. a fully parallel magnitude comparator is also presented. The performance of the proposed multiple-valued logic-in-memory VLSI is about 26 times higher than that of the corresponding implementation based on a binary content-addressable memory under a 0.8-μm flash EEPROM technology. Moreover, its effective chip area and power dissipation are reduced to about 42 and 20 percents, respectively, in comparison with those of binary implementation.
Design of an Asynchronous Processor Using Dual-rail Multiple-valued Current-mode Integrated Circuits

HANYU Takahiro, SAITO Takahiro, KAMEYAMA Michitaka

Technical report of IEICE. VLD　97　(577)　1-8　1998/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers

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This Paper presents a new asyhchronous data-transfer scheme in a multiple-valued current-mode VLSI circuit based on dual-rail differential logic.In the proposed 2-phase multiple-valued asynchronous communication, R-valued dual-rail complementary signals are used to represent a `data value, ' while the `spacer' is represented as(0, 0).The sum of R-valued dual-rail complementary values is a constant (R-1), which makes it easy to distinguish a data-arrival state from a data-transition state.This scheme can be extended to any multiple-valued data representation in the asynchronous communication.New basic components.a signal-state detector to detect a data-arrival state, and a current-controlled threshold detector to produce dual-rail spacer signals(0.0), are also proposed to realize a compact asynchronous control circuit.It is demonstrated that the overhead for the proposed asynchronous circuit is very small in comparison with the corresponding synchronous multiple-valued current-mode logic circuit.
Design and evaluation of a digit-parallel multiple-valued content-addressable memory

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama

Systems and Computers in Japan　29　(11)　48-54　1998
Publisher: John Wiley and Sons Inc.
DOI： 10.1002/(sici)1520-684x(199810)29:11<48::aid-scj6>3.0.co;2-1 　

ISSN： 0882-1666
Design and Evaluation of a Digit-Parallel Multiple-Valued Content-Addressable Memory

T. Hanyu, K. Teranishi, M. Kameyama

Trans. IEICE D-I　J81-D-I　(2)　151-156　1998
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0915-1915
Optimal Design of a Current-Mode Deep-SubmicronMultiple-Valued Integrated Circuit and Its Application

T. Saito, T. Hanyu, M. Kameyama

Trans. IEICE D-I　J81-D-I　(2)　157-164　1998
Wired-Logic-Based Digit-Parallel Multiple-Valued CAM

HANYU Takahiro, TERANISHI Kaname, KAMEYAMA Michitaka

Proceedings of the IEICE General Conference　1997　(1)　324-325　1997/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers
Optimal Design of a Low-Power Current-Mode Multiple-Valued Integrated Circuit

HANYU Takahiro, SAITO Takahiro, KAMEYAMA Michitaka

Proceedings of the IEICE General Conference　1997　(2)　158-158　1997/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers
One-Transistor-Cell Quaternary Universal-Literal CAM for Image Processing

HANYU Takahiro, ARAKAKI Manabu, KAMEYAMA Michitaka

Proceedings of the Society Conference of IEICE　1996　(2)　198-198　1996/09/18
Publisher: The Institute of Electronics, Information and Communication Engineers
Switched-Current Control Architecture for Low-Power High-Performance VLSI Systems

KAZAMA Satoshi, HANYU Takahiro, KAMEYAMA Michitaka

IEICE technical report. Electron devices　96　(107)　49-56　1996/06/20
Publisher: The Institute of Electronics, Information and Communication Engineers

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A new multiple-valued current-mode differential logic circuit is presented for high-speed operations with low-power dissipation. All the current sources are turned off in the non-active circuits, so that their current flows become zero. To control current sources, critical path is not increased by directly controlling the gate of each current source, which keeps high-speed operations with low-power dissipation. As a result, the power dissipation of the proposed multiplier can be reduced to less than 20% of a conventional multiple-valued one with keeping the same multiplication speed. In addition, under the same power dissipation with the supply voltage of 1.5V, the operating speed of the proposed multiplier is 1.3 times faster than that of a binary CMOS multiplier.
Design of a Multiple-Valued Content-Addressable Memory Based on a One-Transistor Cell and Its Application

HANYU Takahiro, KANAGAWA Naoki, KAMEYAMA Michitaka

Technical report of IEICE. ICD　96　(65)　31-38　1996/05/24
Publisher: The Institute of Electronics, Information and Communication Engineers

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A new high-density multiple-valued content-addressable memory (CAM) based on a digit-serial processing scheme is proposed to perform highly parallel search operations in a limited chip area. The number of cells in the CAM is reduced by the use of multiple-valued data representation. Since a multiple-valued threshold operation is performed in each CAM cell, a one-digit comparison is executed by a two-time access to the same cell with different input values. In a one-word comparison, two different CAM cells are activated simultaneously by using two match lines, which makes the access time reduced with no area overhead. Moreover, multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. As a result, the cell area of the proposed 4-valued CAM is reduced to 14% of that of a conventional dynamic binary CAM, and its performance is about 5.4-times higher than that of the corresponding binary one under a 0.8μm standard EEPROM technology. As a typical application, it is demonstrated that the proposed non-volatile CAM is useful as a key component of a collision-detection VLSI processor for real-time path planning.
Design of an Equivalence Logic Network Based on Multi-Emitter Quantum Effect Transistors

Hattori Takenao, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the IEICE General Conference　1996　(2)　163-163　1996/03/11
Publisher: The Institute of Electronics, Information and Communication Engineers
Design of a High-Density Digit-Parallel Multiple-Valued CAM

Kanagawa Naoki, Hanyu Takahiro, Kameyama Michitaka

Proceedings of the IEICE General Conference　1996　(2)　211-211　1996/03/11
Publisher: The Institute of Electronics, Information and Communication Engineers
A High-Density CAM Based on Multi-Level Threshold Control and Its Application

HANYU Takahiro, KANAGAWA Naoki, KAMEYAMA Michitaka

Technical report of IEICE. ICD　95　(72)　41-48　1995/05/26
Publisher: The Institute of Electronics, Information and Communication Engineers

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This paper presents a high-density content-addressable memory (CAM) based on multiple-valued logic. In the proposed CAM, various search operations in each cell are performed by a combination of two multiple-valued threshold operations with different thresholds. Since multiple-valued-encoded data corresponds to the threshold voltage of a transistor, each cell circuit can be simply designed using only a single floating-gate MOS transistor. As a result, the cell area of the proposed CAM is reduced to 19% in comparison with that of a conventional binary CAM cell. As a typical example, the proposed CAM is applied to a collision detection VLSI processor for an intelligent vehicle. The performance of the CAM-based VLSI processor is evaluated to be about 2.6 times higher than that of a conventional binary one.
1.5-V Source-Coupled Current-Mode Multiple-Valued Integrated Circuits and Its Application to a High-Speed Pipelined Multiplier

HANYU Takahiro, MOCHIZUKI Akira, KAMEYAMA Michitaka

IEICE technical report. Computer systems　95　(20)　33-39　1995/04/27
Publisher: The Institute of Electronics, Information and Communication Engineers

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This paper presents the design of a multiple-valued current-mode(MVCM) logic circuit with a low supply voltage for high-speed arithmetic systems at low power dissipation. A dual-rail source-coupled logic circuit is used as a basic component to make a signal-voltage swing small with keeping a large driving capability. Moreover, the pipeline architecture is suitable for efficiently employing the proposed MVCM logic circuits in high-speed arithmetic operations. The latched source-coupled logic circuits for the pipeline architecture can be simply designed by inserting two CMOS pass transistors at the gates of the source-coupled transistors. As a result, the operating speed of a 54-bit pipelined multiplier using the proposed MVCM logic circuits is evaluated to be 1.4 times faster than that of the corresponding binary implementation under the same power dissipation and the supply voltage of 1.5V.
Super Chip Architecture for Intelligent Integrated Systems

KAMEYAMA Michitaka, HANYU Takahiro

1994　(2)　255-256　1994/09/26
Publisher: The Institute of Electronics, Information and Communication Engineers
High-Speed Current-Mode Multiple-Valued Integrated Circuits with a Low Supply Voltage

MOCHIZUKI Akira, HANYU Takahiro, KAMEYAMA Michitaka

1994　(2)　156-156　1994/09/26
Publisher: The Institute of Electronics, Information and Communication Engineers
Generalized Hough Transform VLSI Processor for Model-Based Edge Detection

Yusuf Muhammad, Hanyu Takahiro, Kameyama Michitaka

1994　(2)　163-163　1994/09/26
Publisher: The Institute of Electronics, Information and Communication Engineers

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Edge detection is essential in the image processing such as pattern recognition, scene analysis, etc, but it is difficult to perform edge detection completely on a noisy image. To overcome this, we have proposed a modelbased edge detection system in which some models are selected from an incomplete input image (bottom-up procedure) and a determination of a model through a verification process (top-down procedure). For selecting the models in such a system, Generalized Hough Transform (GHT) is an appropriate solution, because it can find a known-object even at occluded or bad condition. However, GHT requires high computational power and large memory capacity for finding an appropriate candidate from all the models. In this article, we propose a design of VLSI processor for high-speed GHT. The proposed GHT processor is based on the concept that each candidate edge element in the given image is computed by shift operations in the parameter space. Using a new memory architecture with parallel read/write operations for one word of the memory cells, the processor can quickly determine the most likely models. As a result, the processor is compact in size and to be able to work 7500 times faster than its software implementation on workstation.
Source-Coupled Current-Mode Multiple-Valued Integrated Circuits and Their Application to a Pipelined Multiplier.

Mochizuki Akira, Hanyu Takahiro, Kameyama Michitaka

Technical report of IEICE. ICD　94　(175)　23-30　1994/07/25
Publisher: The Institute of Electronics, Information and Communication Engineers

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This paper presents,a design of new source-coupled current-mode multiple-valued integrated circuits for high-speed arithmetic systems with a low supply voltage.The source-coupled circuits have superior currentdriving capability using the dual-rail complementary input signals.Not only the reduction of the interconnection complexity but also the high-speed operation can be achieved under a low supply voltage.Moreover,the Pipeline architecture suitable for the circuit structure is effectively employed for high-speed arithmetic operation utilizing a dynamic binary-storage scheme.
A Collision Detection Multiprocessor for Intelligent Vehicles Using a High-Density CAM

M. Hariyama, T. Hanyu, M. Kameyama

IEEE Intelligent Vehicles Symp.　143-148　1994
Post-Binary Intelligent Integrated Systems

Hanyu Takahiro, Kameyama Michitaka

Technical report of IEICE. ICD　93　(231)　1-8　1993/09/17
Publisher: The Institute of Electronics, Information and Communication Engineers

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Toward the age of ultra-high-density ULSI,multiple-valued digital signal processing will be a key emerging technology in the application to intelligent integrated systems,such as intelligent robot systems,intelligent communication systems,and real-time instrument and control systems.A high degree of spatial parallelism is achieved utilizing the compactness of the multiple- valued arithmetic and logic modules.Moreover,locally computable hardware algorithms and their multiple-valued circuits are very suitable for high-speed signal processing.All the advantages of multiple-valued logic system can be effectively employed for realizing next-generation highly parallel ULSI processor systems. Finally,the effects of hardware algorithms and circuit technologies based on multiple-valued logic are clearly demonstrated in several VLSI processors.
Design of a Quaternary Gate Array for High-Speed Pattern Matching

T. Hanyu, M. Kameyama, T. Higuchi

Trans. of IEICE　J70-D　(2)　493-496　1987
Design and Implimentation of an nMOS Image Processor Based on Quaternary Logic

T. Hanyu, M. Kameyama, T. Higuchi

Trans. of IECE　J69-D　(5)　667-678　1986

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Books and Other Publications 4

Introduction to Magnetic Random-Access Memory

Takahiro Hanyu, Tetsuo Endoh, Shoji Ikeda, Tadahiko Sugibayashi, Naoki Kasai, Daisuke Suzuki, Masanori Natsui, Hiroki Koike, Hideo Ohno

Wiley-IEEE Press　2016/12

ISBN: 9781119009740
Spintronics-based Computing

T. Hanyu

Springer　2015

ISBN: 9783319151793
VLSI 2010 Annual Symposium: Selected Papers (Lecture Notes in Electrical Engineering)

N. Onizawa, F. Funazaki, A. Matsumoto, T. Hanyu

Springer-Verlag　2011/09/07

ISBN: 9400714874
半導体ストレージ2012

羽生貴弘, 池田正二, 杉林直彦, 笠井直紀, 遠藤哲郎, 大野英男

日経BP社　2011/07/29

ISBN: 9784822265588

Presentations 151

Prospects of nonvolatile logic for edge AI computing Invited

Takahiro Hanyu

2024/11/25
Design of a low-energy nonvolatile register based on differential data storing

T. Yoshida, M. Natsui, T. Hanyu

2024/11/12
Evaluation of error tolerance in nonvolatile neural networks with unitary weight representation

M. Natsui, T. Hanyu

2024/09/13
Design environment of edge AI hardware based on few-shot learning

R. Kanda, N. Onizawa, T. Hanyu

2024/08/29
Design of an energy-saved compact MTJ-based nonvolatile register for intermittent computing

T. Yoshida, M. Natsui, T. Hanyu

2024/05/09
Challenge of MTJ-Based Nonvolatile Hardware for Edge AI Applications Invited

Takahiro Hanyu

16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023)　2023/12/19
Stochastic Implementation of Simulated Quantum Annealing on PYNQ

Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

The 22nd International Conference on Field-Programmable Technology (FPT 2023), demo night　2023/12/12
Impact of Spintronics-Based Nonvolatile Hardware for Edge AI Applications Invited

Takahiro Hanyu, Naoya Onizawa, Daisuke Suzuki, Masanori Natsui

International Conference on Solid-State Materials and Devices (SSDM 2023)　2023/09/08
Study on a highly efficient design of nonvolatile AI acclerators using higjh-level synthesis

H. Watanabe, M. Natsui, T. Hanyu

2023/09/06
Challenge of nonvolatile logic for edge AI hardware Invited

Takahiro Hanyu

2023/09/01
Optimization of an MTJ-based nonvolatile register controller based on write-error characteristics

K. Sakai, M. Natsui, T. Hanyu

2022/12/18
Write-energy reduction technique of MTJ-based quantized neural-network hardware

K. Asano, M. Natsui, and T. Hanyu

2022/12/18
Study on stochastic simulated annealing architecture for a large-scale fully-connected graph optimization problem

T. Kubuta, T. Shin, N. Onizawa, T. Hanyu

2022/12/18
FPGA realization of high-speed large-scale spin annealing hardware based on stochastic computing

T. Shin, N. Onizawa, T. Hanyu

2022/09/07
Design of an energy-saved neural network using bit-error tolerance

K. Asano, Y. Sasaki, M. Natsui, T. Hanyu

2022/08/23
FPGA implementation and evaluation for high-speed solution in large-scale SC-SAs

T. Kubuta, T. Shin, N. Onizawa, T. Hanyu

2022/08/23
High-speed annealing technique using stochastic-computing-based QMC

R. Sasaki, N. Onizawa, T. Hanyu

2022/08/23
Design of highly reliable nonvolatile register with write-error detection

K. Sakai, M. Natsui, T. Hanyu

2022/08
Design of an energy-saved RISC-V-based nonvolatile CPU with accelerator-control instructions Invited

K. Sakamoto, M. Natsui, T. Hanyu

2022/05/09
Study on a programmable power-switch configuration and its dynamic control for nonvolatile LSI

F. Zhong, M. Natsui, T. Hanyu

2022/03/19
Spintronics-based nonvolatile FPGA: Challenge of an ultra-low-power reconfigurable hardware platform

D. Suzuki, M. Natsui, T. Hanyu

2022/03/18
Prospects of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications to AI Hardware Invited

Takahiro Hanyu

The 3rd International Symposium on AI and Electronics　2022/02/15
Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications

Takahiro Hanyu

Joint Seminar of BRAIN INSPIRED COMPUTING, PHYSICS, ARCHITECTURES, MATERIALS AND APPLICATIONS (BICPAMA)　2021/12/08
Behavior-aware power switch control technique and its application to nonvolatile logic LSI

F. Zhong, M. Natsui, T. Hanyu

2021/12/02
Challenge of MTJ-Based Nonvolatile Logic-in-Memory Circuits and Their Applications Invited

Takahiro Hanyu

16th IEEE/ACM International Symposium on Nanoscale Architectures　2021/11/10
High-speed simulated annealing technique based on integral stochastic computing

K. Katsuki, T. Shin, N. Onizawa, T. Hanyu

2021/08/26
Study on a nonvolatile RISC-V CPU with power gating

K. Sakamoto, M. Natsui, T. Hanyu

2021/08/26
Prospects of edge AI hardware paradigm using nonvolatile logic Invited

Takahiro Hanyu

2021/05/10
Design automation tools for large-scale CMOS invertible logic circuits

M. Kato, N. Onizawa, T. Hanyu

2021/01/09
Study on LUT data-shifting for binarized-convolutional neural network with nonvolatile FPGA

D. Suzuki, T. Hanyu

2020/12/04
Study on a power-gating switch-control technique for nonvolatile logic LSI

F. Zhong, M. Natsui, T. Hanyu

2020/11/17
Impact of a nonvolatile multiple-valued circuit technique for energy-efficient binarized neural-network hardware Invited

Takahiro Hanyu

2020/11/01
Challenge of brainware computing using nonvolatile logic Invited

Takahiro Hanyu

2020/10/30
Challenge of Nonvolatile Logic LSI for Edge AI Applications Invited

Takahiro Hanyu

U. of Aizu Research Cluster Forum　2020/10/24
Design automation technique for large-scale invertible logic circuits

M. Kato, N. Onizawa, T. Hanyu

2020/08/27
Spintronics-based nonvolatile FPGA and its prospects

D. Suzuki, T. Hanyu

2020/06/03
Design of an MTJ-based multiply-adder module for energy-saved binarized neural networks

T. Chiba, M. Natsui, T. Hanyu

2019/11/14
Stochastic learning algorithm using CMOS invertible logic

T. Shin, N. Onizawa, T. Hanyu

2019/11/14
Design of a high-performance MTJ-based true random-number generator

A. Tamakoshi, N. Onizawa, H. Yamagata, H. Fujita, T. Hanyu

2019/09/15
Design of a high-performance multi-context TCAM for approximate computing

R. Arakawa, N. Onizawa, T. Hanyu

2019/08/23
Implementation of high-speed learning hardware based on CMOS invertible logic

T. Shin, N. Onizawa, T. Hanyu

2019/08/23
Design of a highly reliable MTJ-based nonvolatile flip-flop with non-complementary resistance-state detectability

G. Yamagishi, M. Natsui, T. Hanyu

2019/08/23
Design of a nonvolatile fracturable LUT circuit with an MTJ-based logic-in-memory style

D. Suzuki, T. Hanyu

2019/03/21
Design of a low-power and compact MTJ-based bitcount circuit with variation compensation for binarized neural networks

T. Chiba, M. Natsui, T. Hanyu

2019/01/13
Recent Trends in MTJ-Based Nonvolatile FPGA

Daisuke Suzuki, Takahiro Hanyu

CSRN-Osaka Annual Workshop　2018/12/15
Challenge of AI hardware using post-CMOS circuit technologies Invited

Takahiro Hanyu

2018/12/05
AI hardware paradigm based on post-CMOS circuit technologies Invited

Takahiro Hanyu

2018/11/27
Design of an invertible logic circuit based on stochastic operations

K. Nishino, N. Onizawa, T. Hanyu

2018/09/14
Design of a compact and ultra-low-power XNOR circuit

T. Chiba, M. Natsui, T. Hanyu

2018/09/07
Design of a nonvolatile lookup-table circuit based on write-access minimization

T. Oka, D. Suzuki, T. Hanyu

2018/09/07
Design of MTJ-based nonvolatile lookup-table circuit with multiple functionality

D. Suzuki, T. Oka, T. Hanyu

2018/05/25
Design of a nonvolatile LUT circuit with MTJ-based rich functionality

D. Suzuki, T. Hanyu

2018/03/23
不揮発FPGAを用いた脳型情報処理アクセラレータの構成

鈴木大輔, 羽生貴弘

信学会第２種研究会「多値論理とその応用」　2018/01/06
脳型計算に基づく非シグネチャ不正侵入検出手法

須田拓樹, 夏井雅典, 羽生貴弘

信学会第２種研究会「多値論理とその応用」　2018/01/06
複数個の電圧電流変換特性を用いた低電力MTJベース真性乱数生成器の設計

向田渉吾, 鬼沢直哉, 羽生貴弘

信学会第２種研究会「多値論理とその応用」　2018/01/06
Contextual Cueing Model に基づく実時間画像認識プリプロセッサの検討

西野海斗, 鬼沢直哉, 袁正雄, 松宮一道, 塩入諭, 羽生貴弘

信学会第２種研究会「多値論理とその応用」　2018/01/06
時系列特徴を用いたチップ内データ転送エラー訂正手法とその可能性

加藤健太郎, 夏井雅典, 羽生貴弘

デザインガイア2017　2017/11/06
時系列特徴を用いた脳型計算ベース車載ネットワークセキュリティ技術

夏井雅典, 須田拓樹, 羽生貴弘

第40回多値論理フォーラム　2017/09/16
MTJベース多機能Lookup Table 回路の設計

鈴木大輔, 羽生貴弘

第40回多値論理フォーラム　2017/09/16
ストカスティック演算に基づく省面積・省エネルギー脳型LSI実現

鬼沢直哉, 松宮一道, 羽生貴弘

IEICEソサイエティ大会　2017/09/12
視覚的注意計算モデルのハードウェア実装に向けた基礎的考察

西野海斗, 鬼沢直哉, 松宮一道, 塩入諭, 羽生貴弘

平成29年度電気関係学会東北支部連合大会　2017/08/24
脳型計算に基づく車載ネットワークの不正侵入検出法

須田拓樹, 夏井雅典, 羽生貴弘

平成29年度電気関係学会東北支部連合大会　2017/08/24
ストカスティック演算に基づく省エネルギー脳型LSI実現の展望

鬼沢直哉, 松宮一道, 羽生貴弘

第30回回路とシステムのワークショップ　2017/05/11
ストカスティック演算に基づくFIRフィルタの振幅特性測定

鎌田裕成, 越田俊介, 鬼沢直哉, 阿部正英, 羽生貴弘, 川又政征

第30回回路とシステムのワークショップ　2017/05/11
Technologies to automatically design environments for low energy consumption and highly functional VLSI processors based on non-volatile memory International-presentation

Takahiro Hanyu

3rd CIES Technology Forum　2017/03/22
不揮発FPGAを用いた脳型情報処理アクセラレータ

鈴木大輔, 羽生貴弘

2017電子情報通信学会総合大会　2017/03/22
ストカスティック演算に基づくディジタルフィルタにおける周波数振幅特性の測定法に関する一検討

鎌田裕成, 越田俊介, 鬼沢直哉, 阿部正英, 羽生貴弘, 川又政征

電気学会制御研究会　2017/03/13
Challenge of a Nonvolatile FPGA for a Brainware LSI Platform International-presentation

Daisuke Suzuki, Takahiro Hanyu

The 4th International Symposium on Brainware LSI　2017/02/22
Brain-Inspired Computing for Error-Resilient VLSI System International-presentation

Masanori Natsui, Takahiro Hanyu

The 4th International Symposium on Brainware LSI　2017/02/22
Stochastic Computation for Deep Neural Networks International-presentation

Naoya Onizawa, Takahiro Hanyu

The 4th International Symposium on Brainware LSI　2017/02/22
不揮発マイコン向け高速・低電力アナログ/ディジタル変換器の構成

玉越晃, 夏井雅典, 羽生貴弘

デザインガイア2016　2016/11/28
ストカスティック演算に基づく省エネルギーガンマトーンフィルタのハードウェア実現

鬼沢直哉, 越田俊介, 坂本修一, 阿部正英, 川又政征, 羽生貴弘

第３１回信号処理シンポジウム　2016/11/08
stochastic演算による脳型LSI実現とその多値化の可能性

鬼沢直哉, 羽生貴弘

第39回多値論理フォーラム　2016/09/11
MTJベース不揮発FPGAの技術トレンドとその将来展望

鈴木大輔, 羽生貴弘

第39回多値論理フォーラム　2016/09/11
脳型LSIを拓く集積回路・アーキテクチャの展望

羽生貴弘

学振165委員会VLSI夏の学校2016　2016/08/25
Challenge of Spintronics-Based Nonvolatile Logic-in-Memory VLSI Architecture towards the IoE Era International-presentation

Takahiro Hanyu

2016 Spintronics Workshop on LSI　2016/06/20
Challenge of MOS/MTJ-Hybrid Nonvolatile VLSI Processor for IoE Applications International-presentation

Takahiro Hanyu

VLSI circuit symposium 2016　2016/06/20
Challenge of MOS/MTJ-Hybrid Nonvolatile VLSI Processor for IoE Applications International-presentation

Takahiro Hanyu

VLSI Technology Short Course 2016　2016/06/20
ストカスティック演算に基づくガンマトーンフィルタのハードウェア実現

鬼沢直哉, 越田俊介, 坂本修一, 阿部正英, 川又政征, 羽生貴弘

信学会・CAS研究会　2016/06/16
Design Automation of a Power Aware Nonvolatile FPGA International-presentation

Yuki Tabata, Daisuke Suzuki, Takahiro Hanyu

ULSI Workshop 2016　2016/05/17
Self-Terminated 機構に基づくMTJ 書込み回路とその乱数生成器への応用

鈴木大輔, 羽生貴弘

信学会・総合大会　2016/03/15
リカレントニューラルネットワークを用いた高性能誤り訂正符号技術

菅谷直登, 夏井雅典, 羽生貴弘

第29回多値論理とその応用研究会　2016/01/09
MTJ ベース不揮発FPGA の自動設計環境

田畑佑樹, 鈴木大輔, 羽生貴弘

第29回多値論理とその応用研究会　2016/01/09
Clocked-CMOS構造不揮発ロジックに基づく高性能Logic Element 回路の設計

鈴木大輔, 田畑祐樹, 羽生貴弘

第29回多値論理とその応用研究会　2016/01/09
リカレントニューラルネットワークを用いた高性能誤り訂正符号技術

菅谷直登, 夏井雅典, 羽生貴弘

第29回「多値論理とその応用」第２種研究会　2016/01/09
MTJ ベース不揮発FPGA の自動設計環境

田畑佑樹, 鈴木大輔, 羽生貴弘

第29回「多値論理とその応用」第２種研究会　2016/01/09
Clocked-CMOS構造不揮発ロジックに基づく高性能Logic Element 回路の設計

鈴木大輔, 田畑祐樹, 羽生貴弘

第29回「多値論理とその応用」第２種研究会　2016/01/09
ストカスティック論理に基づくガボールフィルタの構成とその高並列特徴抽出ハードウェアへの展開に関する研究

片桐大作, 鬼沢直哉, 松宮一道, グロスウォーレン, 羽生貴

NC研究会　2015/11/20
MTJ素子を活用した高性能・高信頼VLSI設計技術

夏井雅典, 鈴木大輔, 池田正二, 遠藤哲郎, 大野英男, 羽生貴弘

応用物理学会スピントロニクス研究会・日本磁気学会スピンエレクトロニクス専門研究会・日本磁気学会ナノマグネティックス専門研究会共同主催研究会　2015/11/12
ストカスティック演算に基づくFIRフィルタの性能評価

越田俊介, 鬼沢直哉, 阿部正英, 羽生貴弘, 川又政征

第30回信号処理シンポジウム　2015/11/04
リカレントニューラルネットワークに基づく高効率データ転送技術

夏井雅典, 菅谷直登, 羽生貴弘

第38回多値論理フォーラム　2015/09/12
デジタル制御型CMOS/MTJハイブリッド回路構造に基づく高ランダムネス真性乱数生成器の構成

大澤悟史, 鬼沢直哉, 羽生貴弘

第38回多値論理フォーラム　2015/09/12
MTJ ベース不揮発ロジックLSI における電源スイッチ構造の最適化設計

田畑佑樹, 鈴木大輔, 羽生貴弘

平成27年度電気関係学会東北支部連合大会　2015/08/27
リカレントニューラルネットワークに基づく時系列データ誤り訂正技術とその応用

菅谷直登, 夏井雅典, 羽生貴弘

平成27年度電気関係学会東北支部連合大会　2015/08/27
不揮発ロジックインメモリアーキテクチャとその低電力VLSIシステムへの応用

羽生貴弘, 鈴木大輔, 望月明, 夏井雅典, 鬼沢直哉, 杉林直彦, 池田正二, 遠藤哲郎, 大野英男

信学会ICD研究会　2015/04/16
確率変動緩和機構に基づくMTJベース真性乱数生成器の構成 International-presentation

大澤悟史, 小西貴之, 鬼沢直哉, 羽生貴弘

2015年電子情報通信学会総合大会　2015/03/10
C-RAMベースビット直並列構造VLSIプロセッサの構成 International-presentation

夕部直人, 望月明, 羽生貴弘

2015年電子情報通信学会総合大会　2015/03/10
非対称な遷移確率を有するソフトエラーの効率的な欠陥注入法

根橋竜介, 崎村昇, 羽生貴弘, 杉林直彦

2015年電子情報通信学会総合大会　2015/03/10
ロジックインメモリベース不揮発FPGA用電源制御モジュールの設計

鈴木大輔, 羽生貴弘

2015年電子情報通信学会総合大会　2015/03/10
ストカスティック演算に基づく高信頼低消費電力画像処理プロセッサの構成

片桐大作, 鬼沢直哉, 羽生貴弘

第28回多値論理とその応用研究会　2015/01/10
符号化技術を活用した低消費電力不揮発LSIの構成と評価

阿久津赳明, 夏井雅典, 羽生貴弘

第28回多値論理とその応用研究会　2015/01/10
A Nonvolatile FPGA Using MTJ-Based Logic-in-Memory Structure for Ultra Low-Power Reconfigurable Systems International-presentation

D. Suzuki, T. Hanyu

Int. Workshop on Electronics and Communications　2014/10/27
Design of a Time-Mode-Oriented Sensor Interface Using Pulse-Width-Modulated Signals International-presentation

T. Konishi, T. Hanyu

Int. Workshop on Electronics and Communications　2014/10/27
Analog-to-Stochastic Converter Using MTJ Devicesfor Highly Reliable Vision Chips

Naoya ONIZAWA, Daisaku KATAGIRI, Warren J. GROSS, Takahiro HANYU

多値論理研究ノート　2014/09/13
MTJベース不揮発ロジックLSI向け符号化方式とその評価,

夏井雅典, 阿久津赳明, 羽生貴弘

多値論理研究ノート　2014/09/13
符号化技術に基づく不揮発LSIの低電力化に関する検討

阿久津赳明, 夏井雅典, 羽生貴弘

平成26年度電気関係学会東北支部連合大会講演論文集,　2014/08
ストカスティック演算に基づく画像処理プロセッサのソフトエラー耐性の評価

片桐大作, 鬼沢直哉, 羽生貴弘

平成26年度電気関係学会東北支部連合大会講演論文集,　2014/08
Challenge of Nonvolatile TCAM Design Automation International-presentation

A.Mochizuki, M. Natsui, N. Sakimura, T. Sugibayashi, T. Hanyu

23rd International Workshop on Post-Binary ULSI Systems　2014/05
全文検索システム向け階層的パワーゲーティングを活用した低エネルギー不揮発TCAMエンジンチップ

松永翔雲, 崎村昇, 根橋竜介, 杉林直彦, 夏井雅典, 望月明, 遠藤哲郎, 大野英男, 羽生貴弘

集積回路研究会　2014/04
ストカスティック演算に基づく高信頼論理集積回路の構成に関する一検討

片桐大作, 鬼沢直哉, 羽生貴弘

DC研究会　2014/04
Sparse clustered networksに基づく低電力IPlookup処理用LSIの実現に関する研究

鬼沢直哉, Warren Gross, 羽生貴弘

CS,CAS,SIP研究会　2014/03/06
ばらつき耐性を有するコンパクト・低電力不揮発TCAM の構成

松永翔雲, 望月明, 羽生貴弘

2014年電子情報通信学会総合大会　2014/03
MTJ 素子を用いた不揮発ロジックインメモリLSI の展望

羽生貴弘, 松永翔雲, 鈴木大輔, 望月明, 夏井雅典

2014年電子情報通信学会総合大会　2014/03
MTJ素子を用いた不揮発FPGAの電力効最適化手法

鈴木大輔, 夏井雅典, 望月明, 羽生貴弘

デザインガイア2013 -VLSI設計の新しい大地-　2013/11
MTJ 素子を用いた不揮発ロジックLSI の低電力化に関する一考察

夏井雅典, 荒木敦司, 羽生貴弘

多値論理研究ノート　2013/09
- International-presentation

M. Sihotang, S. Matsunaga, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, H. Sato, S. Fukami, M. Natsui, T. Endoh, H. Ohno, T. Hanyu

2013 IEEE International Solid-State Circuits Conference (ISSCC), Student Research Preview　2013/02/17
Towards a New Paradigm LSI Based on Nonvolatile Logic-in-Memory Architecture International-presentation

T. Hanyu

The 3rd CSIS International Symposium on Spintronics-based VLSIs　2013/02/01
Standby-Power-Free Fully Parallel TCAM Chip Based on Compact Nonvolatile Logic-in-Memory Cell Structure International-presentation

S. Matsunaga, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu

The 3rd CSIS International Symposium on Spintronics-based VLSIs　2013/02/01
3端子MTJ素子を用いたコンパクト不揮発LUT回路の構成

林玉輝, 鈴木大輔, 羽生貴弘

第26回多値論理とその応用研究会　2013/01/12
低電圧動作差動論理基本ゲートに関する一考察

樫内清弘, 夏井雅典, 羽生貴弘

第35回多値論理フォーラム　2012/09/15
MTJ/MOS ハイブリッド論理集積回路のVLSI 設計環境に関する検討

夏井雅典, 玉越晃, 羽生貴弘

第35回多値論理フォーラム　2012/09/15
スピンロジック回路による情報処理の高機能化・省電力化

第73回応用物理学会学術講演会　2012/09
遅延情報データベースに基づく高速・高精度非同期NoC 設計・検証CADに関する一考察

渡邉友馬, 松本敦, 羽生貴弘

電気関係学会東北支部連合大会　2012/08/30
低スイッチング電力基本論理ゲートの構成に関する一考察

樫内清弘, 夏井雅典, 羽生貴弘

電気関係学会東北支部連合大会　2012/08/30
Design of an MTJ-Based Variation-Resilient Basic Gate of Differential Logic

Youngkeun Kim, Masanori Natsui, Takahiro Hanyu

電気関係学会東北支部連合大会　2012/08/30
Prospects of Nonvolatile Logic-in-Memory Architecture Using Magnetic Tunnel Junction Devices International-presentation

The CMOS Emerging Technologies conference　2012/07
MTJベース完全並列形不揮発TCAMの設計

松永翔雲, 羽生貴弘

電子情報通信学会「集積回路」研究会　2012/04/23
不揮発論理ゲートに基づく細粒度パイプライン回路の構成

松永翔雲, 羽生貴弘

電子情報通信学会総合大会　2012/03/20
MTJ素子を用いた高密度・低電力不揮発Logic Elementの構成

鈴木大輔, 羽生貴弘

電子情報通信学会「集積回路」研究会　2012/01/19
VTH補償機能を有するMTJ/MOSハイブリッド電流モードロジックとその最適化

第25回多値論理とその応用研究会　2012/01/07
MTJ/MOSハイブリッド構造に基づく待機電力フリー不揮発演算回路の構成と評価

第25回多値論理とその応用研究会　2012/01/07
故障検出機能を有する2色符号とその非同期双方向リンクへの応用

デザインガイア　2011/11/28
制御回路共有化に基づく非同期細粒度パワーゲーティング手法とその応用

デザインガイア　2011/11/28
MTJ素子を用いた完全並列形高密度不揮発TCAMの構成

SDM研究会　2011/11/10
MTJ素子を用いた待機電力フリー不揮発ロジック基本ゲートの構成

平成23年度電気関係学会東北支部連合大会　2011/08/25
磁壁移動素子を用いた不揮発性論理回路の構成に関する研究

平成23年度電気関係学会東北支部連合大会　2011/08/25
可変抵抗素子を用いたポストプロセスばらつき補償機能付きOTAの検討

平成23年度電気関係学会東北支部連合大会　2011/08/25
不揮発性可変抵抗素子を用いたLSIパラメータばらつき最小化アルゴリズムの検討

平成23年度電気関係学会東北支部連合大会　2011/08/25
不揮発性ロジックインメモリアーキテクチャに基づく高信頼VLSI設計技術

第73回ニューパラダイムコンピューティング研究会　2011/07/30
Instant Power-On Nonvolatile FPGA Based on MOS/MTJ-Hybrid Circuitry International-presentation

GLS-VLSI　2011/05/03
超低電力化を実現する新概念VLSI：不揮発性論理回路技術の展望

第58回春季応用物理関係連合講演会　2011/03/24
転送ボトルネックフリー多値ロジックインメモリＶＬＳＩシステムとその応用

姫路工業大学・特別講演.　2001/11/20
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI International-presentation

IEEE International Symposium on Multiple-Valued Logic　2001/05/24
転送ボトルネックフリー多値ロジックインメモリＶＬＳＩシステムとその応用

第４回FeRAM総合調査委員会・特別講演.　2000/11/06
Multiple-Valued Logic-in-Memory VLSI and Its Application International-presentation

9th International Workshop on Post-Binary ULSI Systems　2000/05/26
多値集積回路とその知能集積システムへの応用

豊橋技術科学大学・特別講演.　1998/11/19
多値情報処理の挑戦～ポストバイナリエレクトロニクスを目指して～

ＮＥＣマイクロエレクトロニクス研究所・特別講演.　1996/04/01
Rule-Programmable Multiple-Valued Matching VLSI Processor International-presentation

3rd International Workshop on Post-Binary ULSI Systems　1994/05/24
Prospects of Multiple-Valued Associative VLSI Processors International-presentation

IEEE Midwest Symposium on Circuits and Systems.　1993/08/16
Device-Model-Based Post-Binary Electronic Systems International-presentation

2nd International Workshop on Post-Binary ULSI Systems　1993/05/29
Beyond-Binary Circuits for Signal Processing International-presentation

1993 IEEE International Solid-State Circuits Conference　1993/02/24

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Industrial Property Rights 7

完全二重非同期通信システム

羽生貴弘, 高橋知宏

Property Type: Patent
磁気抵抗効果素子を用いたロジックインメモリ回路

羽生貴弘, 木村啓明

Property Type: Patent
論理演算回路，論理演算装置および論理演算方法

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視

Property Type: Patent
論理演算回路および論理演算方法

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視

Property Type: Patent
論理演算回路および論理演算方法

亀山充隆, 羽生貴弘, 木村啓明, 藤森敬和, 中村孝, 高須秀視

Property Type: Patent
Nonvolatile Content Addressable Memory

5,930,161

Property Type: Patent
Nonvolatile Content Addressable Memory

5,808,929

Property Type: Patent

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Research Projects 32

Device-Model-Based Electronics Competitive

System: Grant-in-Aid for Scientific Research

1986/01 - Present
Nonvolatile Logic-in-Memory VLSI Technology Competitive

System: Grant-in-Aid for Scientific Research

1986/01 - Present
Multiple-Valued Integrated Systems Competitive

System: Grant-in-Aid for Scientific Research

1983/10 - Present
Development of a high-speed and ultra-low-power die-hard logic LSI fundamental technology for IoT applications

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (A)

Institution: Tohoku University

2021/04/05 - 2025/03/31
確率的デバイスモデルに基づく量子モンテカルロ計算ハードウェアプラットフォーム構築

鬼沢直哉, 羽生貴弘

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 基盤研究(B)

Institution: 東北大学

2021/04/01 - 2025/03/31

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初年度は，代表者がこれまでに考案したストカスティック演算に基づく確率的デバイスモデル近似手法の拡張を行った. 具体的には，従来の手法はSA(シミュレーテッドアニーリング)計算アルゴリズム用に提案された手法であるため，本研究で対象とするQMC(量子モンテカルロ)計算用にアルゴリズムの拡張を行った．さらに，最終的な目標であるFPGA(field programmable gate array)によるハードウェア実現に向けて，提案QMC計算アルゴリズムをMATLABシミュレーションによって評価を行った．提案アルゴリズムの有効性を明らかにするため，小規模な組合せ最適化問題(グラフ同型性判定問題や巡回セールスマン問題やグラフの分割問題など)を対象として，従来SA計算アルゴリズムによるアニーリング処理と比較評価を行った. 小規模な組合せ最適化問題を対象として，ストカスティック演算に基づく提案手法を評価した．シミュレーション評価の結果，従来の決定論的手法に基づくSA法と比較して約３桁以上高速に最適解を得られることがわかった．この研究成果は2021年度東北支部連合大会において発表を行った．
スピントロニクスベース高性能・省電力・高信頼IoTセンサノードの基盤研究開発

夏井雅典, 羽生貴弘

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 基盤研究(B)

Institution: 東北大学

2021/04/01 - 2025/03/31

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本年度は，IoTセンサノードの高性能化・省エネルギー化，高信頼化それぞれの達成に必須となる以下の要素技術について，並行的に研究を推進した． 1．不要なエネルギー消費を徹底的に排除する細粒度パワーゲーティング（PG）技術：IoTセンサノードに想定される多様な動作環境の変化に応じて適切な電源供給の制御を可能とする動作環境適応型PGスイッチ制御技術に関して，所望の機能を実現するための回路構造に関する初期検討を行った．複数のパワースイッチの並列接続からなる回路構造を用い，動作環境に応じて適切なパワースイッチを選択することにより，パワーゲーティング前後における貫通電流や電源電圧変動を抑制可能であることを確認した． 2．多様な動作環境における安定動作を保証する高信頼要素回路技術：NV-LIM回路の省エネルギー性の本質である不揮発記憶機能を司るもっとも重要な要素回路である，不揮発フリップフロップ（NVFF）の高信頼化について，回路レベルの設計最適化に関する初期検討を行った．従来検討されてきた高信頼NVFFの回路構造の解析を行うとともに，自動合成技術糖を用いた設計フローに適用するためのRTLレベル記述について検討を行った． 3．高エネルギー効率な演算処理を可能とするIoTセンサノード向けアクセラレータ技術：センサノードにおいて多用される演算処理の高速化を目的としたアクセラレータ回路の構成方法について，対象とする処理の選定とアクセラレータに求められる性能・機能を調査した上で，開発するアクセラレータの具体的な仕様を検討した．
design efficiency, implementation and applications of CMOS/spintronics-hybrid AI semicoductors

Offer Organization: NEDO

Institution: Tohoku University, NEC, AISIN Corp.

2022/10 - 2025/03
Hardware fundamental for spin-edge computing

Offer Organization: JST：Japan Science and Technology Agency

System: CREST: Core Research for Evolutional Science and Technology

Institution: Tohoku University

2019/10 - 2025/03
脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発

羽生貴弘, 夏井雅典, 米田友洋, 今井雅, 池田正二, 鬼沢直哉, 村口正和

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 基盤研究(S)

Institution: 東北大学

2016/05/31 - 2021/03/31

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一昨年度試作完了予定であったCMOS/MTJロジックLSIだが，地震などの自然災害を含めた様々なトラブルにより，昨年度末に11ヶ月遅れでチップ試作が終了した.そのため，チップ測定結果から得られた知見を元に，本来の計画であれば本年度実施予定であったCMOS等価回路のLSIチップの試作予定を変更し，シミュレーションによる提案回路の応用展開を加速させた．具体的には，共同研究者であるフランスCNRSのJ.-P. Diguet主任研究員のグループと共同で，脳型情報処理の一種である深層学習の推論処理の低消費電力を試みた．一般的に画像認識アプリケーションにおいては，深層学習ハードウェアの量子化がわずかな認識精度の低下で大幅な省電力化が実現されるに対して，音声認識等の他のアプリケーションにおいては，量子化により大幅な認識精度低下してしまう問題を見出した．そこで，提案のCMOS/MTJ回路に基づくMulti-Context Ternary Content-Addressable Memory(MC-TCAM)を考案し，高い認識精度を保ちつつ大幅な省電力化が可能なSelective Computing Architectureを提案した．この研究成果は，学術論文誌Journal of Applied Physics誌に採録されただけでなく，IEEE CAS Society Region 8のフラグシップカンファレンスである26th ICECSにおいてBest Young Professionals Paper Awardを受賞するに至った．
Study on Implementation for Greatly Reducing Power Dissipation of Serial Communication Mechanisms

YONEDA Tomohiro

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (A)

Institution: National Institute of Informatics

2015/04/01 - 2018/03/31

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This research project proposes a new serial communication scheme where the power consumption of the transmitter and the receiver are reduced to almost 0 for the period when no valid data is transmitted, unlike the conventional serial communication schemes where the embedded clock is always transmitted and the clock and data recovery circuit is continuously working. Since the proposed power reduction can be applied to every invalid word, it achieves a very fine grain power control. In order to evaluate the effectiveness of the proposed scheme, two 10Gbps serial communication circuits based on the proposed and the conventional schemes have been implemented using the same device technology. The experimental results based on the SPICE simulations of those circuits show that the power dissipation of the proposed scheme is greatly reduced compared to that of the conventional scheme when the ratio of the invalid words increases.
脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発

羽生貴弘, 米田友洋, 今井雅, 鬼沢直哉

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 基盤研究(A)

Institution: 東北大学

2016/04/01 - 2017/03/31

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脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術を開発するために，初年度であるH28年度は，ダーク・シリコン非同期基本論理ゲート構成とその小規模演算回路の設計，並びにCMOS等価回路による原理動作検証を計画していた．提案のダーク・シリコン非同期基本ゲートを検討し，いくつかの回路で動作シミュレーションを行った．シミュレーション環境としては，不揮発性素子であるMagnetic Tunnel Junction (MTJ)素子とCMOS回路を用いて，SPICEによるトランジスタレベルシミュレーションを行った．シミュレーションにより，基本的なパワーげティング動作までを確認した．また研究資料収集として，多値論理及びそのハードウェア実現に関する国際会議であるInternational Symposium on Multiple-Valued Logic (ISMVL)2016に出席をし，アルゴリズムからシステムレベルに至る脳型コンピューティグに関する知見を得た．上記の提案回路の検討中に，重複応募中の基盤研究（S)が採択となったため，本基盤研究（A)としての研究はその時点で終了となった．ただし，基盤研究（S)と本基盤研究（A)の課題として，共通に「脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術の開発」としていたため，本基盤研究（A)での研究進捗は，そのまま基盤研究（S)に引き継ぐ形となった．
Nonvolatile-device-based PVT-variation-resilient VLSI system

HANYU TAKAHIRO, NATSUI Masanori

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2010/04/01 - 2014/03/31

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The aim of this research is to develop a new paradigm VLSI design methodology which relaxes design margin and realizes high-performance VLSI with high-dependability. In this research, we developed a MOS/magnetic-tunnel-junction-hybrid logic-circuit style for realizing a PVT-variation-aware VLSI processor with higher performance capability. For applying the proposed method to large-scale circuit structures, an optimization algorithm of circuit parameters based on evolutionary computation technique was also examined.
Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer Technique

HANYU Takahiro, MOCHIZUKI Akira, MATSUMOTO Atsushi, NATSUI Masanori

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2006 - 2008
不揮発性デバイスに基づくクイックオンVLSIシステムの構成

羽生貴弘, 松本敦, 望月明

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 萌芽研究

Institution: 東北大学

2006 - 2007

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不揮発性ロジックに基づくクイックオン・超並列・動的再構成可能VLSIの基盤技術を確立するため,本年度は,不揮発性デバイスの1つTMR(Tunneling Magneto-Resistive)素子とMOSトランジスタの相対配置と回路のスイッチング特性について検討した.TMR素子はメモリ素子の1つであるが,その記憶状態に応じて抵抗値が変化する可変抵抗素子とみなせる.そのため,TMR素子とMOSトランジスタを直列接続した基本回路構成において,TMR素子を下側(グランド側)に配置すると,TMR素子に電流を流すとトランジスタのソース端子が電圧降下を起こすため,ゲート・ソース間電位が減少し,MOSトランジスタのスイッチングを弱めてしまう.通常,MRAMではこの影響を避けるため,TMR素子を上側(電源側)に,MOSトランジスタを下側(グランド側)にそれぞれ配置して直列接続するが,ロジック回路を構成する場合,TMR素子自体の抵抗値変化のみならず,この電圧降下によるMOSトランジスタへの影響も同時に活用することで,ON・OFF状態の抵抗差をより大きく取ることができ,高速スイッチングが可能となる.本研究の主な成果は,2007年8月開催のMWSCASに採択・発表すると共に,応用物理学会誌の解説論文(2007年12月号),2008年3月初旬の磁気学会と同年3月末の応用物理関係学会にてそれぞれ招待講演を依頼されるなど,MOSトランジスタと新機能デバイスを融合した,今後の新しい集積回路技術の1つとして国内外で評価された.
Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques

HANYU Takahiro, MOCHIZUKI Akira

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (C)

Institution: Tohoku University

2003 - 2005

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The trend in global interconnection delay such as clock distribution is becoming a significant problem in recent deep submicron VLSI. As CMOS technology scales from one generation to the next, the product of the interconnect resistance and load capacitance is not scaling with technology. One of the possible methods to solve the above interconnection problems is to use asynchronous circuit implementation. Dual-rail encoding is widely used as an encoding style of asynchronous data transfer, where every logical variable is encoded using two wires and timing information is also implicit in the code. Every asynchronous data transfer protocol is based on request-acknowledge handshaking : every transfer features a request action where the initiator starts a transfer, and an acknowledge action allowing the target to respond. In this way, the signals propagate round trip between the transmitter and the receiver, thus the cycle time of data transfer becomes large, which is the problem accompanying asynchronous data transfer essentially. If the above procedures are executed simultaneously, the cycle time of the asynchronous data transfer with dual-rail encoding becomes much faster than that of the conventional methods. In this research, a new asynchronous data-transfer protocol, called 2-color "1-pbase" dual-rail encoding, is proposed for high-speed asynchronous data transfer. The 2-color 1-phase encoding has two colors which mean two kinds of data definition "ODD" and "EVEN", and different valid data is detected by transferring codewords which have different color alternately. In this protocol, the receiver as well as the transmitter sends the color information as the request signal, then the data transfer is performed by detecting whether the mutual color information is same or not. Because the both request signals can be sent simultaneously, overlap communication can be done. Since data and color information must be bundled on the same wires in the asynchronous data transfer, it is important to detect valid data from the mixed dual-rail code of data and color information. The use of the proposed encoding makes it easy to merge and detect data and color information by calculating the sum of the codewords. In multiple-valued bidirectional current-mode circuits, since current-mode linear summation can be implemented by wiring without any active devices, the proposed asynchronous circuit becomes simple. Moreover, current signals from both sides can be superposed on the same wires, which is an important characteristic of multiple-valued current-mode logic to realize a control signal multiplexing scheme. The use of comparators with sense amplifier makes it easy to detect the sum of components of the codewords quickly. In fact, it is evaluated in a 0.18um CMOS technology that the data transfer cycle of the proposed asynchronous data-transfer scheme using the multiple-valued current-mode logic circuit is about 1.5-times faster than that of the corresponding binary CMOS implementation under the normalized power dissipation.
Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application

HANYU Takahiro, KAMEYAMA Michitaka, MOCHIZUKI Akira, KIMURA Hiromitsu

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2001 - 2004

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Dramatic advances in technology scaling give us the capability to realize a giga-scaled system-on-a-chip, while rapid increases in the wiring complexity and the global wiring delay has led to serious data-transfer bottleneck between separated logic modules and memories in current deep-submicron VLSI. Logic-in-memory structures, where storage functions are distributed over a logic-circuit plane, provide a key architecture for ensuring highly effective use of internal memory bandwidth. However, usual logic-in-memory VLSI becomes generally complicated, because of the hardware overhead involved in distributing storage elements. In this research, I have presented ferroelectric-based (FE-based) functional logic gates for highly parallel VLSI systems. In FE-based logic gates, since both non-volatile storage and switching functions are performed simultaneously in FE capacitors, chip size and a leakage current can be reduced. As a typical application of this circuit technology, a 54x54-bit pipelined multiplier is implemented and its superior performance is demonstrated. Furthermore, I have also developed the improved ferroelectric-based logic circuit, called a "Complementary-Ferroelectric-Capacitor (CFC)" logic for low-power logic-in-memory VLSI. Using two FE capacitors where a pair of complementary data representations is stored, the voltage swing generated by capacitive coupling effect becomes large enough to perform the switching operation at the low supply voltage. Degradation of the non-volatile charge caused by the switching operation becomes small because the bias voltage appeared across the FE capacitor is always lower than its coercive voltage. As a typical example, a 32-bit content-addressable memory (CAM) is also implemented and its superior performance is demonstrated. Finally, a tunneling magnetoresistive (TMR)-based logic-in-memory circuit has been also proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability any logic functions between external inputs and stored inputs can be performed by using the TMR based resistor/transistor network The combination of a dynamic current-mode logic circuit and a TMR-based network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of a full adder is discussed, and its advantages are demonstrated.
多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用

羽生貴弘, 米田友洋, 川人祥二, 亀山充隆

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 基盤研究(C)

Institution: 東北大学

2002 - 2002

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本研究課題では、米国等で先行している高速データ転送技術を、この分野で著名な国際会議への参加や著名な研究者を交えた国際研究討論会を自ら開催することで習得すると共に、この技術を活用したより高性能な高速データ転送技術の開発を目的としている。この観点から本年度の研究成果の概要を以下に列挙する: (1)国際会議「VLSI回路シンポジウム」への参加(平成14年6月):VLSI Circuit Symposiumは回路技術に関する国際会議であり、最先端回路技術に関する最も権威のある国際会議の1つである。本研究代表者らはこの国際会議に出席し、最新の高速データ転送技術動向を調査した。昨年までRambus社等の米国企業が主流だった高速データ転送技術は、平成14年度になりアジア地区や国内大手企業も積極的に研究がなされていることが伺えた。また、高速データ転送技術と演算機能を一体化したCommunnication Processorと呼ばれるマルチメディア応用プロセッサの発表も盛んに行われた。本研究者らのグループでも、高速データ転送を実現するため、演算機能と記憶機能を一体化する新しい回路技術をこの国際会議で発表し、研究者の興味を引いた。 (2)国際会議「ニューパラダイムVLSIコンピューティング」の開催(平成14年12月): 高速データ転送および高速演算機能も交えたVLSIコンピューティング全般をカバーする国際会議として、本研究者らのグループが中心となり、第1回ニューパラダイムコンピューティング国際会議を東北大学(仙台)で開催した。国外から招聘された研究者は約10数名、国内から約100名程度の研究者が集い、3日間に渡り研究発表を行った。国内外の研究者間で活発な討論が展開され、とても有意義な国際会議であった。 (3)国際会議ISSCC'03への参加(平成15年2月): 国際固体回路会議(ISSCC)も最先端回路技術に関する最も権威ある国際会議の1つである。この会議において、本研究者らのグループは、高速データ転送に関連する不揮発性ロジック回路と呼ぶ新しい回路技術を発表した。
Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities

HANYU Takahiro

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (C)

Institution: Tohoku University

2000 - 2002

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Low-power circuit design while maintaining a high-speed capability is needed not only for battery-powered portable applications but also to reduce the power dissipation of dedicated apecial-purpose VLSI processors, because the extra current density in interconnections causes temporal or permanent malfunction due to voltage drops or electromigrations. Multiple-valued current-mode (MVCM) integrated circuits have a potential advantage to reduce the wiring complexity and the nurnber of active devices in arithmetic large-scale-integration chips because the frequently used linear sum operation can be performed simply by wiring with no active devices. However, the switching speed in the MVCM circuit is relatively slow, and its power dissipation due to the steady current becomes high because current-sources in differential-pair circuits always flow a constant current in the active mode. In this project, a new MVCM circuit based on dual-rail differential logic has been proposed for high-speed, low-power, highly reliable arithmetic-oriented VLSI. A differential logic-style circuit has an attractive feature that its input voltage swing is small enough while maintaining a high currentdriving capability. The combination of the differential logic style and MVCM circuitry in arithmetic VLSI makes it possible to improve the switching speed compared with that of a corresponding binary CMOS implementation. Moreover, the use of a precharge-evaluate logic style abo makes the steady current flow cut off, which results in great reduction of dynamic power dissipation. A judicious combination of differential logic, MVCM logic and dynamic logic in the proposed circuit makes it possible to reduce the power dissipation together with device and interconnection counts while maintaining a high-speed switching capability. The use of dual-rail coding, which is used in differential logic-style circuit, is a widely used encoding style of asynchronous and self-checking circuit implementation. From this point of view, we have also proposed high-performance asynchronous and self-checking circuit using multiple-valued dual-rail complementary signals.
Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing

KAMEYAMA MICHITAKA, HANYU TAKAHIRO

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2000 - 2002

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The communication bottleneck between memories and logic modules is one of the most serious problems due to interconnection complexity in recent deep-submicron VLSI systems-on-a-chip. In the situation, high-performance and low-power VLSI circuit technologies suitable for multi-giga-hertz clock operations are expected to be developed. In this study, we proposed multiple-valued VLSI utilizing differential-pair circuit which has high-driving capability and ferroelectric-capacitor logic for low-power logic-in-memory VLSI. 1.Development of the highest performance multiple-valued VLSI A novel-source-coupled logic style using multiple-valued signals is proposed for high-speed-low-power VLSI system. All the differential-pair circuits are driven by dual-rail signals, which we call "full source-coupled logic". Design and implementation results show that the performance of the full-source coupled logic circuit is very superior to the conventional multiple-valued source-coupled logic circuit. It is a useful circuit technology for multi-gigahertz and low-voltage operations. 2.Ferroelectic Logic-in-Memory Architecture A functional pass gate and a nonvolatile logic-in-memory architecture are proposed for communication-bottleneck-free VLSI system. Transition of a remnant-polarization charge and capacitive coupling of a ferroelectric capacitor makes storage and switching functions which are merged into a ferroelectric capacitor. The use of ferroelectric-based non-volatile storage makes leakage currents cut off. Applying the ferroelectric based circuitry to CAM implementation results in about half dynamic power reduction and 1/22000 static power reduction in comparison with the equivalent CMOS implementation under 0.6μm ferroelecric/CMOS process.
Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application

HANYU Takahiro, KAMEYAMA Michitaka

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B).

Institution: Tohoku Univesity

1997 - 2000

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Communication bottleneck between memory and logic modules is one of the most serious problems in the multimedia VLSI systems on a chip. A logic-in-memory structure, in which logic-circuit elements are distributed over a memory-cell array, is a key technology to solve the above problem. A content-addressable memory (CAM) is one of the typical logic-in-memory VLSIs. However, CAMs have been more complex to build and had lower storage density than a normal memory such as RAMs because of the overhead involved in the storage and logic elements. In this project, a high-performance multiple-valued CAM based on floating-gate-MOS pass-transistor logic is proposed to perform highly parallel magnitude comparisons in a limited chip area. Multiple-valued stored data in the proposed CAM correspond to the threshold voltage of a floating-gate MOS transistor, so that the CAM cell circuit can be designed by using only a single MOS transistor. Moreover, a logic-in-memory VLSI architecture based on such a multiple-valued floating-gate-MOS pass-transistor network is also proposed to realize parallel arithmetic and logic circuits with multiple-valued inputs and binary outputs. The main results of this project are listed below : (1) Highly Parallel Magnitude-Comparison Hardware Algorithm for CAMs, (2) Logic-in-Memory VLSI Architecture Using Floating-Gate MOS-Based Multiple-Valued Pass-Transistor Network, (3) Functional Pass Gate Based on Ferroelectric Devices and Their Application, (4) Current/Voltage-Hybrid-Mode Multiple-Valued Integrated Circuits.
高速・低電力電流モード多値算術演算VLSI回路の試作

羽生貴弘

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 奨励研究(A)

Institution: 東北大学

1998 - 1999

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センサフィードバックが密な計測制御システムや知能ロボットシステム、情報通信システムなどのマルチメディア応用知能システムを実現するためには、処理の高速応答性はもちろん、移動体に高性能VLSIチップを内蔵させるため、実現するVLSIチップには低消費電力性が必要不可欠となる。本研究では上記の高速性と低消費電力性を同時に満たす回路方式の1つとして、2線式電流モード多値回路方式に着目し、具体的な多値基本回路の設計と試作を行う。また、これを算術演算回路へ応用した際について、その性能を評価することを目的とする。以下に、本年度の研究成果を取りまとめる: (1)チップ試作サービスによる高速・低電力電流モード多値基本回路の試作:前年までに考案した電流モード多値基本演算回路のネットリストを、フルカスタムVLSI試作サービスへ渡し、チップの試作を行った。 (2)試作チップの動作試験:テストボード上にて、試作チップの基本動作を確認した。また、回路シュミレーション結果と比較し、より高性能化達成のため提案回路構成の改良を行った。具体的には、複数の電源電圧を使用することにより、さらに高速性と低消費電力性の点で優れた電流モード多値回路が構成できることを明らかにした。 (3)2線式電流モード多値回路技術を活用した適用分野拡大に関する考察:提案の2線式電流モード多値回路方式は、高速化・低電力化を達成できる技術としてのみならず、セルフチェッキング回路や非同期制御回路等へ容易に拡張できることを見出した。今後はこれらの技術とも融合させて、算術演算システムのみならず、高性能VLSIシステム全般に幅広く活用できることが期待できる。なお以上の研究成果は、多値論理研究で世界で最も権威のある国際会議、IEEE Int.Symposium on Multiple-Valued Logicにて2000年5月末に発表予定である。
Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications

KAMEYAMA Michitaka, HARIYAMA Masanori, HANYU Takahiro

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: TOHOKU UNIVERSITY

1997 - 1999

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In this study, hardware algorithms for highly parallel arithmetic circuits, logic-in-memory VLSI architecture, and low-power, high-speed multiple-valued integrated circuits are considered in detail. The usefulness of the multiple-valued integrated circuits based on level multiplexing is established, and we can develop fundamental technology of a multiple-valued chip family. The major results of this research are shown below: 1. Design of highly-parallel multiple-valued arithmetic and logic circuits The following three method are proposed to find code assignment for ultimately parallel multiple-valued operation circuits. When a functional specification of a k-ary operation is given by mapping relationship between input and output symbols. (1) Reed-Muller expansion by a sparse matrix, (2) Partion theory, and (3) Hierarchical code assignment using hot codes etc. 2. Development of current-mode multiple-valued integrated circuits The use of a differential logic circuit with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage. The optimal circuit design is further considered to improve the performance with lower power dissipation. It is made clear that the use of two supply voltages is very useful for the improvement. Moreover, we developed asynchronous and self-checking design methods for the multiple-valued VLSI. As a result, we can obtain fundamental technology for the next-generation multiple-valued VLSI system. 3. Development of logic-in-memory multiple-valued VLSI system A new logic-in-memory VLSI architecture based on multiple-valued floating-gate-MOS pass logic is proposed to solve communication bottleneck between memory and logic modules. A multiple-valued sorted data is represented by a threshold voltage of the floating-gate-MOS transistor, so that a single floating-gate MOS transistor is effectively employed for merging a threshold-literal and a pass-switch function. As a typical example of the logic-in-memory VLSI, a fully parallel magnitude compartor is developed. The performance of the proposed VLSI is about 26 times higher than that of a corresponding binary implementation. Moreover, its effective chip area and power dissipation are reduced to about 42% and 20%, respectively.
High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System

KAMEYAMA Michitaka, HARIYAMA Masanori, HANYU Takahiro

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: TOHOKU UNIVERSITY

1997 - 1999

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Real-world applications need to achieve very quick response for dynamically changing real-world environment. As broad typical examples of the real-world applications, highly-safe systems, robot systems and multimedia systems are considered, and High-level synthesis for their VLSI processors are studied. An optimization problem such that an objective function corresponding to a certain physical factor is discussed under physical constraints in the high-level synthesis. Our approach for the high-level synthesis starts from concrete applications. They are a stereo vision VLSI processor, a collision detection VLSI processor and a path-planning VLSI processor. First, we considered a VLSI-oriented algorithm for each application. Then, optimal structure of arithmetic and logic blocks are derived from the view points of performances and chip areas. The major results are shown below: 1. To design high performance VLSI processors in deep-submicron age, it is required to find the architecture such that there is no effect on interconnection delay in parallel data transfer between memories and arithmetic modules. For the high-speed and efficient parallel data transfer, an optimal allocation method is developed, and it is applied to design of a stereo vision VLSI processor. The evaluation shows that the performance is greatly increased over the conventional architecture. 2. As a collision detection VLSI processor, we proposed a VLSI-oriented algorithm based on hierarchically iteration of coordinate transformation and matching operation. It is confirmed by implementation of the chip that Read-only content addressable memory and bit-serial pipeline architecture make the performance of the VLSI processor very high. 3. As an intelligent robot which works autonomously in unknown environment, we proposed a fast path planning algorithm to find a feasible collision-free path. One of the most promising configuration is selected according to a distance between every point in free space and the nearest obstacle. The configuration selection keeps a robot as far away as possible from obstacles, and reduces the number of configurations for collision detection. Moreover, a highly-parallel processor based on logic-in-memory architecture and redundancy of processing elements is proposed to overcome a transfer bottleneck between memory and processing elements.
MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEM

HANYU Takahiro, LIN H.C., NG Wai-Tung, GULAK Glenn, SMITH Kenneth C., KAMEYAMA Michitaka

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for international Scientific Research

Institution: TOHOKU UNIVERSITY

1997 - 1998

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Real-world applications need to achieve very quick response for dynamically changing real-world environment. Therefore, it is very important to develop a "Super Chip for Intelligent Integrated Systems." The emerging technologies of intelligent integrated systems for real-world applications rely increasingly on VLSI processors high degree of parallelism in various levels such as architectural, logic design, and circuit/device level. The following items are the themes discussed in this project : (1)Discussion about algorithm/system/architecture-level innovation : We have discussed about the efficiency of multiple-valued logic-in-memory VLSI as the development of fully parallel image processor for intelligent integrated systems. The basic idea of the multiple-valued logic-in-memory VLSI architecture is that the data which are frequently used in the communication between the processing element (PE) and the memory are stored into the local memory tightly connected to the PE.We also discussed about the efficiency of some concrete examples using such concept. (2)Discussion about logic-design/circuit-design-level innovation : We have presented a floating-gate-MOS pass-transistor network as a circuit-level logic-in-memory VLSI architecture. We have discussed about the usefulness of such a new pass-transistor network and about its application areas. While a floating-gate MOS transistor is used as a multiple-valued storage element in the present VLSI system, some logical functions such as a threshold function and a pass-switch function are merged into the multiple-valued memory plane. (3)Discussion about device/process-technology-level innovation : We have also discussed about the device technologies to realize the floating-gate-MOS pass-transistor network.
超並列多値連想メモリに関する研究

羽生貴弘

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 奨励研究(A)

Institution: 東北大学

1996 - 1996

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本研究ではまず、提案する多値連想メモリ(CAM)の仕様化を行った。すなわち、多値CAMで行う数値データ処理を分類し、知能情報処理に不可欠であると考えられる演算として「数値の大小比較演算」に特定し、これをできるだけ高速に実行できるCAMの構成を設計仕様とした。通常のCAMではマスク付き一致・不一致の検出は容易に高並列化可能であるが、数値の大小比較やソーティング等の演算は直列的に実行されているため、この演算をできるだけ高速に実行する新しい演算アルゴリズムと新しいハードウェア構成を検討することは極めて重要である。アルゴリズムレベルでの高性能化として、本研究では「情報の多値符号化表現」を活用することにより、大小比較すべきデータの桁数を減少させた。また、各CAMセルでの大小比較結果を適宜取りまとめることにより、n桁の多値データに対する大小比較演算をnステップで実行させることに成功した。ハードウェアレベルでの高性能化として、本研究では多値CAMをできるだけコンパクトに実現することで単位面積当たりの演算能力を高める方法を検討した。まず、コンパクトなCAMセルを実現するためにCAMセル自体の演算機能をできるだけ簡易なものにすることを考察した。具体的には、CAMセルアレー外部で共通に入力信号の変換を行うことにより、CAMセル内部では「単純なしきい演算機能」と「多値記憶機能」のみを実現すればよいことを見出した。さらに、フローティングゲートMOSトランジスタを活用することにより、CAMセルがこのトランジスタ1個のみで実現できることを明らかにした。なお、上記の研究成果は、最先端集積回路研究で最も権威のあるISSCC '97 (1997年2月)で発表されるなど、国内外の関連分野の研究者から高く評価された。
Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent Vehicle

KAMEYAMA Michitaka, XIAOWEI Deng, HANYU Takahiro

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

1995 - 1996

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For next-generation super chips, not only computer-worldapplications but also real-world applications will be important targets. In the real-world applicatins, thers is data flow passing through the real world, so that the real-world environment is changed to be the desired states by control actions. The typical applications are robotics, intelligent vehicle, factory automation, real-time instrumentation and control systems, and so on. In this reaearch project high-performance VLSI processors and their key technologies based on new multiple-valued integrated circuits have been developed an follows : (1)VLSI processors for high-speed collision detection and 3-Dimensional instrumentation In the collision-detection operation between a vehicle and obstacles, high-computational power is essentially required in not only coordinate transformation but also matching operation between vehicle and obstacle pixels. In the proposed VLSI processor for high-speed collision detection, a content-addressable memory is introduced to store vehicle pixel information, so that the matching operation is drastically accelerated. Since vehicle pixel information is predetermined and not changed, the high-performance CAM based on a ROM cell is proposed. A parallel and pipelined architecture for the high-speed coordinate transformation is also proposed based on two-dimensional vector rotations and matrix multiplications. On the other hand, a high-performance VLSI architecture with an efficient memory access scheme is proposed for high-speed 3-D instrumentation. Since pixels in candidate blocks overlap, these pixel values are used repetitively by a 2-D array of processing elements (PEs). By using the 2-D PE array, only local communications are required since the image block is a 2-D array of pixel values. Moreover, a new memory-interleave technique is also proposed to concurrently access the frame memory. (2)Low-Power Current-Mode Multiple-Valued Integrated Circuits A new current-source control technique is proposed to design a low-power high-speed multiple-valued current-mode (MVCM) integrated circuit in a low supply voltage. The use of a defferential logic circuit (DLC) with a pair of dual-rail complementary inputs makes an input signal-voltage swing small, which results in a high driving capability at a lower supply voltage while having large static power dessipation. In the proposed DLC using switched current control, the static power dissipation is greatly reduced because current sources in non-active circuit blocks are switched off. In the current control, no additional transistors are required to control the current sources because a current-control circuit is already used in the threshold detector. As a typical example of arithmetic circuits, a new 1.5V-supply 54*54-bit multiplier based on a standard 0.8-um CMOS technology is also designed. Its performance is about ^<1.3> times faster than of a binary fastest multiplier under the normalized powerdissipation. (3)High-Performance Multiple-Valued Content-Addressable Memory and Its Application A new high-density multiple-valued content-addressable memory (CAM) is proposed for highly parallel search operations. Multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. Since a single match line in a one-word circuit is used for performing a multi-input wired AND opearion, the magnitude comparison result between multi-digit data can be obtained simultaneously. As a result, a one-world magnitude comparison with n digits can be performed by just (n+1) steps in spite of a single-transistor cell circuit and single-match-line architecture, which makes the peripheral circuit of a CAM cell array small. Moreover, typical applications clearly demonstrate that theproposed non-volatile CAM is useful as a hardware accelerator for various real-world applications such as high-speed collision detection and highly parallel danger-detection rule matching. Moreover, a new special-purpose 4-valued CAM is also proposed for high-speed cellular logic image processing. A universal literal in CAM cell is used to compare a 4-valued input value with various template patterns simultaneously. The universal-literal cell circuit with 4-valued data storage capability can be implemented by just a few floating-gate MOS transistors, since the cell function is performed by simple threshold operations together with logic-value conversion. As a result, the effective cell area in the proposed CAM array is greatly reduced in comparison with that in a corresponding binary CAM-based implementation.
Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration

KAMEYAMA Michitaka, HANYU Takahiro

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University, Graduate School of Information Sciences

1994 - 1996

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Highly parallel hardware algorithms based on new data representation and circuit technology are key issues to develop VLSI processors in deep submicron geometry. Local computability and parallelism are one of the most important factors to reduce the critical delay path which determines processor performance. In this research project, multiple-valued redundant encoding method for parallel hardware algorithms were investigated together with the multiple-valued circuit technology. Our concept is that linearlity is fully utilized to make systematic design feasible. Linear combinational circuits are constructed by adders and coefficient multipliers over GF (p). Let us assume that the specifications are given by symbol-level operations. A linear circuit for a unary operation can be always transformed to a highly parallel circuit whose output depends on only 2 input-digits by the matrix transformation called the similar transformation. If all representation matrices are equal each other in k-ary operations, we can obtain consistent sparce matrices for K representation matrices. A symmetrical operation is such a class of operations. However, we cannot always linearize every k-ary specification. To solve the problem, we introduce multiplicated recundant symbols by assigning multiple-valued code vertices to one symbol. A sufficient condition for the symbol-level linearlity is derived to make the redundant multiple-valued code assignment. Extension of the above design method is also discussed in a class of non-linear combinational circuits based on Reed-Muller expansion. If we can obtain a matrix representation of a combinational circuit with a formulation of the product of a constant matrix and variable vectors, design of a highly parallel circuit can be attributed to find a sparce constant matrix. Such class of the combinational circuits is more general, so it will be very useful for the design of practical k-ary operations such as an adder and a multiplier. Another aspect of this research is low-power high performance multiple-valued integrated circuits. A new current-mode multiple-valued MOS integrated circuit is proposed with higher driving capability in comparison with the conventional binary and multiple-valued digital circuits. Moreover, an effective current-source control technique is found which leads to low-power high-speed multiple-valued threshold logic operations. This new circuit technology will be effectively employed for the highly parallel arithmetic and logic circuits developed in this project.
次世代デバイスに基づく高性能多値VLSIシステムの構成に関する研究

羽生貴弘

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 奨励研究(A)

Institution: 東北大学

1994 - 1994

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本研究では、次世代デバイスの1つである共鳴トンネリングトランジスタの特性を参考にすると共に、システム構築上で重要となる演算機能を整理することにより新しいデバイスモデルを定義し、そのモデルに基づき高性能な多値LSIシステムを系統的に構成する方法について研究を行った。まず、次世代デバイスとして共鳴トンネリングトランジスタに着目し、多値演算回路への応用とデバイス自体の実現可能性の両面とを念頭においてデバイスモデルの機能的仕様を決定した。また、上記のデバイスモデルに基づいて次世代集積回路実現に適合した多値基本演算子の定義を行うと共に、それに基づく多値演算システムの系統的合成方法の定式化を行った。具体的には、多値演算システムでは(1)多値信号を伝送するための「パスゲート機能」と(2)多レベル信号を検出するための「ユニバーサルリテラル機能」が重要であることを見いだすと共に、これら2つの機能を満たす基本ゲートが共鳴トランジスタを用いて極めて簡単に実現できることを示した。さらに、この機能デバイスを「ス-パパスゲート」と名付けて、その系統的設計方法について議論してきた。以上の研究成果により、英国電気学会誌(IEE)において2編のフルペーパー論文が採録されるに至った。このように、現在提案されているデバイスに基づいてシステム構成を行うのではなく、システム実現に本質的に重要となるデバイス機能をシステムアーキテクチャ側から提案するアプローチは、システムの究極的な最適設計法として従来の延長上にない極めて独創的なものであり、上述したように国際的にもその研究成果が認められてきているので、わが国の科学技術の発展に大いに寄与できたものと確信している。
ロボットビジョン用特徴抽出VLSIプロセッサシステムの構成に関する研究

羽生貴弘

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 奨励研究(A)

Institution: 東北大学

1993 - 1993

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未知環境下で自律的に作業を行う次世代知能ロボットシステムを構築するためには、視覚情報に基づき環境認識を行い、認識結果をフィードバックして自己の持つ環境モデルを逐次的に更新させながら制御していくことが重要となる。特に、実世界での応用を前提とした知能集積システムにおいては、上述した環境の変化を入力画像から迅速、かつ的確に検知することが必要不可欠であると考えられる。本研究では、画像認識を行う上で重要となる特徴量としてエッジ抽出に着目し、それを系統的かつ高速に処理するプロセッサシステムの構成について考察した。すなわち、濃淡階調を有する入力画像に対して単に論理微分処理を行っただけでは物体の輪郭線には複数の不連続な部分が生じてしまう。そこで、認識対象物体に関するモデルに基づいてトップダウン的に推論を施し、総合的に認識物体のエッジ抽出を行った。また高速処理に関しては、多値電流モード回路に基づく新しいスイッチング基本回路を考案し、高速演算回路の実現可能性をシミュレーションやレイアウト設計により実証してきた。上記の研究成果は、従来のソフトウェア中心で研究されてきたロボットビジョン研究に対して、ハードウェアによる実現可能性とその有効性を示す新しい試みであり、わが国の独創的研究の一つとして貢献できたと確信する。
Study on Post-Binary ULSI Sstems

KAMEYAMA Michitaka, BUTLER Jon T., SMITH Kenneth C., SASAO Tsutomu, HANYU Takahiro, HIGUCHI Tatsuo, SILIO Carles B.

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for international Scientific Research

Institution: Tohoku University, Graduate School of Information Sciences

1992 - 1993

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The present binary VLSI systems will be confronted with many serious problems in an ultimately fine geometry feature size. Some of them are listed below : (1) Interconnection delay is prominent limit on the performance in the deep submicron integrated circuits. (2) For low-voltage operations, noises caused inside a chip should be reduced. (3) Parallel procesing performance is limited by data communications between processing elements. (4) Large scale design is essential at various levels such as logic design, test, circuit design and physical design. (5) New phenomena such as tunnneling and quantum effects will be caused in microelectronics devices, which is usually assumed to be inconvenient effects for binary digital operations. Multiple-valued digital processing and its integration are expected to be one of the most effective solutions for the above problems. The objective of this research is to demonstrate theories, new developments and techniques in multiple-valued integrated circuits and their applications. Especially, the delay time due to global communications between functional modules is one of the most important factors to determine the total performance In ULSI Processors for the applications of intelligent integrated systems. Several concrete advantages of multiple-valued digital procssing technology have been established in deep submicron geometry. They are classified to the device and circuit level, the arithmetic and logic algortihm level, and the system application level. In the device and circuit level, we have demonstrated that the new area called device-model based electronics becomes very important to activate the new direction of the device development suitable for multiple-valued operations. In the alogorithm level, we have proposed a new design method for highly parallel operation circuits based on a linear concept. In the system application level, we have designed a new multiple-valued ULSI processor for digital control with spatially parallel structure. Further, we have proposed a universal super chip for intelligent integrated systems with very flexible network structure.
IMPLEMENTATION OF ULTRA-HIGH-SPEED INFERENCE HARDWARE ENGINE BASED ON 4-VALUED CMOS INTEGRATED CIRCUITS AND ITS APPLICATION

HIGUCHI Tatsuo, HANYU Takahiro, KAMEYAMA Michitaka

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Developmental Scientific Research (B)

Institution: TOHOKU UNIVERSITY

1991 - 1992

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This project presents a dynamically rule-programmable, ultra-high-speed inference accelerator VLSI ( called hardware engine ) based on fully parallel pattern matching. Rules and attributes in the processor are essentially independent of one another, so that pattern matching operations can be performed in parallel by rules and attributes. Because each attribute is directly encoded by a single multiple-valued digit, one-digit pattern matching can be easily described by only a 'programmable delta literal'. Moreover, a one-digit pattern matching cell can be simply implemented using a floating-gate MOS device, where threshold voltages correspond to the content of an attribute value. This property makes rule programming easily in such a pattern matching cell. The layout of the proposed inference accelerator VLSI is given by using a 2 mum double-poly double-metal design rule. The effective size of the accelerator chip is about 7.0 x 8.0 ( mm^2 ) including 256 rules, 144 attributes and two types of conflict resolution circuit. Because each block in the VLSI processor is executed in parallel, ultra-high-speed inference can be achieved. Using SPICE2 simulation, the inference time is estimated at about 300 ns, which is about 1700 times faster than that of the conventional software-based systems with 32-bit 100 MIPS workstation. 3-D objects are represented by graphs whose vertices and edges correspond to the apexes of objects and the line segments between apexes, respectively. In 3-D object recognition based on graph matching, one of the most important procedures is to find the best available sets ( called 'cliques') of mutually compatible assignments between two graphs, that is, 'clique finding'. As an application, a new highly parallel clique-finding VLSI processor for high-speed graph matching has been shown. The enhanced performance is attributed to the parallel search procedure operated in a digit pipelining and theuse of floating gate MOS devices. The proposed processor will be used in not only 3-D object recognition, but also several applications in fields that have structural data.
BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS

HIGUCHI Tatsuo, HANYU Takahiro, KAMEYAMA Michitaka

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for General Scientific Research (B)

Institution: TOHOKU UNIVERSITY

1989 - 1991

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In the conventional binary arithmetic circuits based on array structures, the operating speed is restricted by carry propagation. The carry propagation in the signed-digit (SD) number systems is always limited to one position to the left. However, the SD number systems have not been studied from the point of view of integrated circuit implementation. This project begins with implementation of the multiple-valued bidirectional current-mode circuits composed of current source, current mirrors, threshold detector, and bidirectional current input. Using the bidirectional currentmode circuits, the SD full adder is realized. The layout of the SD full adder is given with 2-mum CMOS technology. The module is constructed by an adder, a partial-product generator, a quotient digit generator, a sign invertor, two encoders and four wiring blocks. Using the modules thus obtained, any arithmetic operations based on addition, subtraction, multiplication and division can be realized by appropriately specifying the interconnection among the modules. This modular realization is very useful for semicustom VLSI as gate array. The comparison between the proposed SD multiplier and the fastest binary multiplier is carried out. The SD multiply time is comparable to that of the fastest binary multiplier. From the point of view of reduction in design complexity, however, the SD multiplier is much more superior to the binary multiplier. Lastly, it is demonstrated that these advantages of the multiple-valued technology are useful for implementation of the multiple-valued super chip for intelligent robots. The high-performance of the chip is also evaluated in detail.

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スピントロニクス技術を用いた不揮発性集積回路の試作に成功－磁石と半導体を組み合わせて待機電力をゼロにする新しい集積回路－

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