TOHOKU UNIVERSITY Researchers

Details of the Researcher

Home

日本語 English

Hiroe Iwasaki

Section

Tough Cyberphysical AI Research Center

Job title

Specially Appointed Professor(Research)

Degree

博士（工学）（筑波大学）

researchmap

https://researchmap.jp/HiroeIwasaki

J-GLOBAL ID

202101017261394468

e-Rad No.

60902179

ORCID

https://orcid.org/0009-0007-1223-1139

Research History 7

2022/08 - Present

Tohoku University　Tough Cyberphysical AI Research Center
2022/04 - Present

Tokyo University of Agriculture and Technology　Institute of Engineering
2020/07 - 2022/03

Tohoku University　Tough Cyberphysical AI Research Center
2020/07 - 2022/03

NTTエレクトロニクス　映像コンポーネント事業本部
2013/04 - 2020/07

日本電信電話株式会社　メディアインテリジェンス研究所
2011/04 - 2013/03

NTTエレクトロニクス
1991/04 - 2011/03

日本電信電話株式会社

Show all Show first 5

Education 1

University of Tsukuba

1987/04 - 1991/03

Committee Memberships 20

国立研究開発法人科学技術振興機構　国際青少年サイエンス交流事業選考委員会インド若手研究人材招へいプログラム分科会委員

2024/09 - Present
情報処理学会　システム・アーキテクチャ研究運営委員会幹事

2024/04 - Present
国立研究開発法人科学技術振興機構　先端国際共同事業推進事業アドバイザ

2023/08 - Present
電子情報通信学会　コンピュータシステム研究専門委員会専門委員

2023/06 - Present
電子情報通信学会　男女参画委員会委員

2022/06 - Present
電子情報通信学会　エレクトロニクスソサイエティアドホック幹事

2022/06 - Present
電子情報通信学会集積回路研究会　専門委員→幹事補佐→専門委員

2010/05 - 2022/06
CREST　ディペンダブル V LSI システムの基盤技術追跡評価委員

2020/08 - 2021/03
情報処理学会システムとLSIの設計技術研究会　幹事

2018/05 - 2020/05
Asia and South Pacific Desig n Automation Conference ASP DAC Designer s Forum　実行委員

2014/04 - 2019/01
画像電子学会　技術理事

2015/06 - 2017/05
情報処理学会計算機アーキテクチャ研究会　運営委員

2012/05 - 2015/05
戦略的創造研究推進事業における領域事後評価委員　委員

2015/03 - 2015/03
電子情報通信学会 Integrated Circuits and Devices in Vietnam(ICDV)　実行委員

2010/05 - 2012/08
電子情報通信学会集積回路研究会 LSI とシステムのワークショップ　実行委員

2010/07 - 2012/05
IEEE Symposium on Low Power and High Speed Chips Cool Chips　組織委員

2009/05 - 2011/03
電子情報通信学会英文論文誌 D分冊　編集委員

2006/05 - 2010/05
電子情報通信学会英文論文誌 C分冊　編集委員

2002/05 - 2006/05
情報処理学会計算機アーキテクチャ研究会　運営委員

2002/05 - 2006/04
情報処理学会システムソフトウェアとオペレーティング・システム研究会　運営委員

1998/05 - 2002/04

Show all ︎Show first 5

Research Interests 6

AI technology
FPGA
VLSI technology
Hardware implementation technology
Video Coding
Image processing

Research Areas 2

Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Communication and network engineering / Video coding LSI
Informatics / Intelligent informatics / Image processing hardware

Awards 10

Best Session Presentation Award

2025/01　ICCE 2025 Award　A Fast Block Partitioning Decision Method Using Luminance Textures for VVC Encoders
Outstanding paper award (The Twelfth International Symposium on Computing and Networking (CANDAR 2024))

2024/11　Adaptive Parallelization based on Frame-level and Tile-level Parallelisms for VVC Encoding
Best Paper Award

2022/12　The 23rd International Conference on Parallel and Distributed Computing, Applications and Technologies(PDCAT 2022)　A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders
Best Paper Award

2022/05　IEICE Communications Society　4K 120fps HEVC Encoder with Multi-Chip Configuration
Best Poster Award

2022/04　IEEE Coolchips　A Shared Cache Architecture for VVC Coding
文部科学大臣賞科学技術賞

2013/04
ハイビジョン・次世代テレビ技術賞

2012/05　映像情報メディア学会
第57回前島密賞

2012/03
第33回日本産業技術大賞内閣総理大臣賞

2004/04　日刊工業新聞社
DATE Design Contest Award

2003/03　IEEE

Show all ︎Show 5

Papers 56

Adaptive Parallelization based on Frame-level and Tile-level Parallelisms for VVC Encoding Peer-reviewed

Karin Onouchi, Masayuki Sato, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi

2024/11
An Ising-based Decision Method for Intra Prediction Mode in Video Coding Peer-reviewed

Takuto Momominami, Naoya Niwa, Masahito Kumagai, Kazuhito Komatsu, Hiroaki Kobayashi, Hiroe Iwasaki

2024/11
Picture Partitioning Design of Neural Network-Based Intra Coding For Video Coding For Machines

Keiichi Chono, Naoya Niwa, Hiroe Iwasaki

2024 IEEE International Conference on Image Processing (ICIP)　1929-1934　2024/10/27
Publisher: IEEE
DOI： 10.1109/icip51287.2024.10647747 　
ISP Parameter Optimization and FPGA Implementation for Object Detection in Low-Light Conditions

Kento Mishima, Naoya Niwa, Kazutoshi Wakabayashi, Hiroe Iwasaki

2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)　1-3　2024/04/17
Publisher: IEEE
DOI： 10.1109/coolchips61292.2024.10531181 　
VVCにおけるDCTを用いたCUブロック分割決定手法（ショートペーパー） Peer-reviewed

小嶋優輔, 岩崎裕江, 江川隆輔

画像電子学会誌　53　(2)　99-103　2024/04
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders Peer-reviewed

Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi

Parallel and Distributed Computing, Applications and Technologies　288-300　2023/04/08
Publisher: Springer Nature Switzerland
DOI： 10.1007/978-3-031-29927-8_23 　

ISSN： 0302-9743

eISSN： 1611-3349
A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming Peer-reviewed

KOBAYASHI Daisuke, NAKAMURA Ken, KITAHARA Masaki, OSAWA Tatsuya, OMORI Yuya, ONISHI Takayuki, IWASAKI Hiroe

IEICE Transactions on Information and Systems　E106.D　(1)　46-57　2023/01/01
Publisher: The Institute of Electronics, Information and Communication Engineers
DOI： 10.1587/transinf.2022edp7048 　

ISSN： 0916-8532

eISSN： 1745-1361

More details Close

This paper describes a novel low-latency 4K 60 fps HEVC (high efficiency video coding)/H.265 multi-channel encoding system with content-aware bitrate control for live streaming. Adaptive bitrate (ABR) streaming techniques, such as MPEG-DASH (dynamic adaptive streaming over HTTP) and HLS (HTTP live streaming), spread widely on Internet video streaming. Live content has increased with the expansion of streaming services, which has led to demands for traffic reduction and low latency. To reduce network traffic, we propose content-aware dynamic and seamless bitrate control that supports multi-channel real-time encoding for ABR, including 4K 60 fps video. Our method further supports chunked packaging transfer to provide low-latency streaming. We adopt a hybrid architecture consisting of hardware and software processing. The system consists of multiple 4K HEVC encoder LSIs that each LSI can encode 4K 60 fps or up to high-definition (HD) ×4 videos efficiently with the proposed bitrate control method. The software takes the packaging process according to the various streaming protocol. Experimental results indicate that our method reduces encoding bitrates obtained with constant bitrate encoding by as much as 56.7%, and the streaming latency over MPEG-DASH is 1.77 seconds.
An Efficient Reference Image Sharing Method for the Image-division Parallel Video Encoding Architecture Peer-reviewed

Nakamura Ken, Omori Yuya, Kobayashi Daisuke, Nitta Koyo, Sano Kimikazu, Sato Masayuki, Iwasaki Hiroe, Kobayashi Hiroaki

IEICE Transactions on Electronics　advpub　2022
Publisher: The Institute of Electronics, Information and Communication Engineers
DOI： 10.1587/transele.2022lhp0002 　

ISSN： 0916-8524

eISSN： 1745-1353

More details Close

This paper proposes an efficient reference image sharing method for the image-division parallel video encoding architecture. This method efficiently reduces the amount of data transfer by using pre-transfer with area prediction and on-demand transfer with a transfer management table. Experimental results show that the data transfer can be reduced to 19.8-35.3% of the conventional method on average without major degradation of coding performance. This makes it possible to reduce the required bandwidth of the inter-chip transfer interface by saving the amount of data transfer.
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization Peer-reviewed

Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano

2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022)　2022

DOI： 10.1109/MWSCAS54063.2022.9859281 　
4K 120fps HEVC Encoder with Multi-Chip Configuration Peer-reviewed

OMORI Yuya, NAKAMURA Ken, ONISHI Takayuki, KOBAYASHI Daisuke, OSAWA Tatsuya, IWASAKI Hiroe

IEICE Transactions on Communications　104　(7)　749-759　2021
Publisher: The Institute of Electronics, Information and Communication Engineers
DOI： 10.1587/transcom.2020CQP0004 　

ISSN： 0916-8516

eISSN： 1745-1345

More details Close

<p>This paper describes a novel 4K 120fps (frames per second) real-time HEVC (High Efficiency Video Coding) encoder for high-frame-rate video encoding and transmission. Motion portrayal problems such as motion blur and jerkiness may occur in video scenes containing fast-moving objects or quick camera panning. A high-frame-rate solves such problems and provides a more immersive viewing experience that can express even the fast-moving scenes without discomfort. It can also be used in remote operation for scenes with high motion, such as VAR (Video Assistant Referee) systems in sports. Real-time encoding of high-frame-rate videos with low latency and temporal scalability is required for providing such high-frame-rate video services. The proposed encoder achieves full 4K/120fps real-time encoding, which is twice the current 4K service frame rate of 60fps, by multichip configuration with two encoder LSI. Exchange of reference picture data near a spatially divided slice boundary provides cross-chip motion estimation, and maintains the coding efficiency. The encoder supports temporal-scalable coding mode, in which it output stream with temporal scalability transmitted over one or two transmission paths. The encoder also supports the other mode, low-delay coding mode, in which it achieves 21.8msec low-latency processing through motion vector restriction. Evaluation of the proposed encoder's multichip configuration shows that the BD-bitrate (the average rate of bitrate increase), compared to simple slice division without inter-chip transfer, is -2.86% at minimum and -2.41% on average in temporal-scalable coding mode. The proposed encoder system will open the door to the next generation of high-frame-rate UHDTV (ultra-high-definition television) services.</p>
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture Peer-reviewed

NAKAMURA Ken, KOBAYASHI Daisuke, OMORI Yuya, OSAWA Tatsuya, ONISHI Takayuki, NITTA Koyo, IWASAKI Hiroe

IEICE Transactions on Electronics　103　(3)　77-84　2020
Publisher: The Institute of Electronics, Information and Communication Engineers
DOI： 10.1587/transele.2019LHP0005 　

ISSN： 0916-8524

More details Close

<p>In this paper, we describe a novel low-delay 4K 120-fps real-time HEVC decoder with a parallel processing architecture that conforms to the HEVC main 4:2:2 10 profile. It supports the hierarchical temporal scalable streams required for Ultra High Definition high-frame-rate broadcasting and also supports low-delay and high-bitrate decoding for video transmission uses. To achieve this support, the decoding processes are parallelized and pipelined at the frame level, slice level, and coding tree unit row level. The proposed decoder was implemented on three FPGAs operated at 133 and 150 MHz, and it achieved 300-Mbps stream decoding and 37-msec end-to-end delay with our concurrently developed 4K 120-fps encoder.</p>
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture Peer-reviewed

Nakamura Ken, Omori Yuya, Kobayashi Daisuke, Osawa Tatsuya, Onishi Takayuki, Nitta Koyo, Iwasaki Hiroe, Shimizu Atsushi

IEEE Conference Proceedings　2019　(COOL CHIPS)　2019
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation Peer-reviewed

Onishi Takayuki, Omori Yuya, Nakamura Ken, Iwasaki Hiroe, Shimizu Atsushi

IEEE Conference Proceedings　2019　(ISCAS)　2019
4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay Peer-reviewed

Omori Yuya, Nakamura Ken, Onishi Takayuki, Kobayashi Daisuke, Osawa Tatsuya, Iwasaki Hiroe

IEEE Conference Proceedings　2019　(ICECS)　2019
A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control Peer-reviewed

Kobayashi Daisuke, Nakamura Ken, Osawa Tatsuya, Omori Yuya, Onishi Takayuki, Iwasaki Hiroe

IEEE Conference Proceedings　2019　(GLOBECOM)　2019
An HEVC real-time encoding system with high quality HDR color representations Peer-reviewed

Kobayashi Daisuke, Nakamura Ken, Onishi Takayuki, Nakajima Yasuyuki, Iwasaki Hiroe, Ikeda Mitsuo, Shimizu Atsushi

IEEE Conference Proceedings　2018　(ICCE)　2018
A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K Peer-reviewed

Omori Yuya, Onishi Takayuki, Iwasaki Hiroe, Shimizu Atsushi

IEEE Transactions on Multi-Scale Computing Systems　4　(4)　2018

ISSN： 2332-7766
A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations Peer-reviewed

Kobayashi Daisuke, Nakamura Ken, Onishi Takayuki, Iwasaki Hiroe, Shimizu Atsushi

IEEE Transactions on Consumer Electronics　64　(4)　2018

ISSN： 0098-3063
A Single-Chip 4K 60-fps 4:2:2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K Peer-reviewed

Onishi Takayuki, Sano Takashi, Nishida Yukikuni, Yokohari Kazuya, Nakamura Ken, Nitta Koyo, Kawashima Kimiko, Okamoto Jun, Ono Naoki, Sagata Atsushi, Iwasaki Hiroe, Ikeda Mitsuo, Shimizu Atsushi

IEEE Transactions on Very Large Scale Integration (VLSI) Systems　26　(10)　2018

ISSN： 1063-8210
A 120 fps high frame rate real-time video encoder

Omori, Y., Onishi, T., Iwasaki, H., Shimizu, A.

NTT Technical Review　15　(12)　2017

ISSN： 1348-3447
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K Peer-reviewed

Omori Yuya, Onishi Takayuki, Iwasaki Hiroe, Shimizu Atsushi

IEEE Conference Proceedings　2017　(COOL CHIPS)　2017
マルチチャンネルビデオエンコーダにおけるチャンネル間映像品質均一化によるビットレートの削減手法 Peer-reviewed

佐野卓, 大西隆之, 新田高庸, 新田高庸, 岩崎裕江, 池田充郎, 清水淳, 上倉一人, 上倉一人

電子情報通信学会論文誌 D(Web)　J100-D　(3)　2017

ISSN： 1881-0225
Professional H.264/AVC CODEC chip-set for high-quality HDTV broadcast infrastructure and high-end flexible CODEC systems Peer-reviewed

Mitsuo Ikeda, Hiroe Iwasaki, Koyo Nitta, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Mioru Inamori, Takeshi Yoshitome, Hiroaki Matsuda, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Jiro Naganuma

2007 IEEE Hot Chips 19 Symposium, HCS 2007　2016/05/31

DOI： 10.1109/HOTCHIPS.2007.7482498 　
HEVC映像符号化LSIのための8K拡張性をもつ参照画像バッファ構成 Peer-reviewed

西田享邦, 大西隆之, 岩崎裕江, 池田充郎, 清水淳

電子情報通信学会論文誌 D(Web)　J99-D　(12)　2016

ISSN： 1881-0225
Professional H.265/HEVC Encoder LSI Toward High Quality 4K/8K Broadcast Infrastructure Peer-reviewed

Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, T akashi Sano, Yukikuni, Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu

IEEE Hot Chips 27 Symposium　1-24　2015/08
Publisher: IEEE
DOI： 10.1109/HOTCHIPS.2015.7477464 　
Reference Picture Buffer Memory Architecture for 4K HEVC Encoders Peer-reviewed

Yukikuni Nishida, Tkayuki Onishi, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu

IEEE Symposium on Low Symposium on Low--PowPower and Higher and High--Speed Chips COOL Chips XVIII　2015/04
Single-chip 4K 60fps 4:2:2 HEVC Video Encoder LSI with 8K Scalability Peer-reviewed

ONISHI Takayuki, SANO Takashi, NISHIDA Yukikuni, YOKOHARI Kazuya, SU Jia, NAKAMURA Ken, NITTA Koyo, KAWASHIMA Kimiko, OKAMOTO Jun, ONO Naoki, KUSABA Ritsu, SAGATA Atsushi, IWASAKI Hiroe, IKEDA Mitsuo, SHIMIZU Atsushi

Symposium on VLSI Circuits　2015　2015

ISSN： 2158-5601
HEVC hardware encoder technology

Onishi, T., Sano, T., Yokohari, K., Su, J., Ikeda, M., Sagata, A., Iwasaki, H., Shimizu, A.

NTT Technical Review　12　(5)　2014

ISSN： 1348-3447
A Software-Based H.264/AVC HDTV Real-Time Interactive CODEC Architecture Using Parallel Processing Peer-reviewed

SANO Takashi, ONISHI Takayuki, IWASAKI Hiroe, KAMIKURA Kazuto, NAGANUMA Jiro

The IEICE transactions on information and systems (Japanese edition)　96　(10)　2562-2569　2013/10
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1880-4535
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures Peer-reviewed

Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma

IEICE TRANSACTIONS ON ELECTRONICS　E95C　(4)　432-440　2012/04

DOI： 10.1587/transele.E95.C.432 　

ISSN： 1745-1353
MVC real-time video encoder for full-HDTV 3D video Peer-reviewed

Ikeda, Mitsuo, Onishi, Takayuki, Sano, Takashi, Sagata, Atsushi, Iwasaki, Hiroe, Nakajima, Yasuyuki, Nitta, Koyo, Takahashi, Yasuko, Yokohari, Kazuya, Kobayashi, Daisuke, Kamikura, Kazuto, Jozawa, Hirohisa

Digest of Technical Papers - IEEE International Conference on Consumer Electronics　2012

ISSN： 0747-668X
A Motion Estimation and Motion Compensation Architecture for Professional H.264/AVC Encoder LSI Peer-reviewed

ONISHI Takayuki, NITTA Koyo, SANO Takashi, IWASAKI Hiroe, IKEDA Mitsuo, NAGANUMA Jiro, KAMIKURA Kazuto

The IEICE transactions on information and systems　93　(10)　2148-2155　2010/10/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1880-4535
A Software-based H.264/AVC HDTV real-time interactive codec architecture using parallel processing Peer-reviewed

Sano, Takashi, Ohnishi, Takayuki, Iwasaki, Hiroe, Kamikura, Kazuto, Naganuma, Jiro

ICCE 2010 - 2010 Digest of Technical Papers International Conference on Consumer Electronics　2010
H.264/AVC codec LSI configuration technology and application to IP retransmission services

Koyo Nitta, Hiroe Iwasaki, Jiro Naganuma

NTT Technical Review　7　(11)　2009/11

ISSN： 1348-3447
Professional H.264/AVC Decoder LSI for High-quality HDTV Broadcast Infrastructure Peer-reviewed

Hiroe Iwasaki, Mitsuo Ikeda, Koyo Nitta, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Takeshi Yoshitome, Hiroaki Matsuda, Jiro Naganuma

IEEE COOL Chips XI　287-293　2008/04
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures Peer-reviewed

NITTA Koyo, IKEDA Mitsuo, IWASAKI Hiroe, ONISHI Takayuki, SANO Takashi, SAGATA Atsushi, NAKAJIMA Yasuyuki, INAMORI Minoru, YOSHITOME Takeshi, MATSUDA Hiroaki, TANIDA Ryuichi, SHIMIZU Atsushi, NAKAMURA Ken, NAGANUMA Jiro

Digest of Technical Papers. Symposium on VLSI Circuits　2008　2008

ISSN： 2158-5601
Professional H.264/AVC CODEC chip-set for high-quality HDTV broadcast infrastructure and high-end flexible CODEC systems Peer-reviewed

Ikeda, Mitsuo, Iwasaki, Hiroe, Nitta, Koyo, Onishi, Takayuki, Sano, Takashi, Sagata, Atsushi, Nakajima, Yasuyuki, Inamori, Mioru, Yoshitome, Takeshi, Matsuda, Hiroaki, Tanida, Ryuichi, Shimizu, Atsushi, Nakamura, Ken, Naganuma, Jiro

2007 IEEE Hot Chips 19 Symposium, HCS 2007　2007
Single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond HDTV level Peer-reviewed

IWASAKI H, NAGANUMA J, NITTA K, NAKAMURA K, YOSHITOME T, OGURA M, NAKAJIMA Y, TASHIRO Y, ONISHI T, IKEDA M, MINAMI T, ENDO M, YASHIMA Y

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　15　(9)　2007

ISSN： 1063-8210
MPEG-2 real-time software CODEC for full-duplex transmission application over IP networks Peer-reviewed

Iwasaki, H., Naganuma, J., Endo, M., Yashima, Y.

Systems and Computers in Japan　36　(2)　2005

DOI： 10.1002/scj.20151 　

ISSN： 0882-1666
New Step-top Box for Interactive Visual Communication of Home Entertainment using MPEG-2 Full-duplex CODEC LSI Peer-reviewed

INAMORI Minoru, IWASAKI Hiroe, ONISHI Takayuki, IKEDA Mitsuo, NAGANUMA Jiro, YASHIMA Yoshiyuki

Digest of Technical Papers. IEEE International Conference on Consumer Electronics　2005　2005
New Set-top Box for Interactive Visual Communication of Home Entertainment using MPEG-2 Full-duplex CODEC LSI Peer-reviewed

INAMORI Minoru, IWASAKI Hiroe, ONISHI Takayuki, IKEDA Mitsuo, NAGANUMA Jiro, YASHIMA Yoshiyuki

IEEE Transactions on Consumer Electronics　51　(2)　2005

ISSN： 0098-3063
Improvements on SIMD Macroblock Processor in MPEG-2 Video Encoder LSI Peer-reviewed

NITTA Koyo, YOSHITOME Takeshi, KONDO Toshio, IWASAKI Hiroe, NAGANUMA Jiro

The Transactions of the Institute of Electronics, Information and Communication Engineers C　87　(4)　377-385　2004/04/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1345-2827
MPEG-2 Real-Time Software CODEC for Full-Duplex Transmission Application over IP Networks Peer-reviewed

IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto, YASHIMA Yoshiyuki

The Transactions of the Institute of Electronics,Information and Communication Engineers.　87　(1)　42-50　2004/01/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0915-1915
A 1.1W Single-Chip MPEG-2 HDTV CODEC LSI for Embedding in Consumer-oriented Mobile CODEC Systems. Peer-reviewed

IWASAKI H, NAGANUMA J, NAKAJIMA Y, TASHIRO Y, NAKAMURA K, YOSHITOME T, ONISHI T, IKEDA M, IZUOKA T

Proceedings of the IEEE Custom Integrated Circuits Conference　2003　2003

ISSN： 0886-5930
Single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond HDTV level Peer-reviewed

IWASAKI H, NAGANUMA J, NITTA K, NAKAMURA K, YOSHITOME T, OGURA M, NAKAJIMA Y, TASHIRO Y, ONISHI T, IKEDA M, ENDO M

DESIGNERS FORUM: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION　2003
Single chip MPEG 2 422P@HL CODEC LSI with Multi chip Configuration for Large Scale Processing beyond HDTV Level Peer-reviewed

Jiro Naganuma, Hiroe Iwasaki, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yayusuki Nakajima, Y utaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo

IEEE Hot chips 14　20002-20007　2002/08
Publisher: IEEE Computer Society
DOI： 10.1109/DATE.2003.10235 　
Advanced concurrent design environment for multimedia system LSIs

Iwasaki, H., Ochiai, K., Naganuma, J., Endo, M., Ogura, T.

Systems and Computers in Japan　33　(14)　2002

DOI： 10.1002/scj.10004 　

ISSN： 0882-1666
Advanced Concurrent Design Environment for Multimedia System LSIs Peer-reviewed

IWASAKI Hiroe, OCHIAI Katsuyuki, NAGANUMA Jiro, ENDO Makoto, OGURA Takeshi

The Transactions of the Institute of Electronics,Information and Communication Engineers.　84　(6)　548-557　2001/06/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0915-1915
On-Chip Multimedia Real-Time OS and Its MPEG-2 Applications. Peer-reviewed

IWASAKI H, NAGANUMA J, ENDO M, OGURA T

IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)　E84-D　(4)　2001

ISSN： 0916-8532
SuperENC: MPEG-2 video encoder chip.

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe 0005, Naoki Kobayashi 0002, Tsuneo Okubo, Ryota Kasai

IEEE Micro　19　(4)　56-65　1999

DOI： 10.1109/40.782568 　
Real Time Software MPEG 2 Video Encoder on Parallel and Distributed Computer Systems, Peer-reviewed

Hiroe Iwasaki, J iro Naganuma, M akoto Endo, T. Ogura

International Conference on Computer Communication 1999　2　362-369　1999
On Chip Multimedia Real Time OS and its MPEG 2 Applications Peer-reviewed

Hiroe Iwasaki, J iro Naganuma, M akoto Endo, T akeshi Ogura

6th International Conference on Real Time Computing Systems and Applications (RTCSA’99)　200-203　1999
High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability Peer-reviewed

OCHIAI K, IWASAKI H, NAGANUMA J, ENDO M, OGURA T

DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION 1999, PROCEEDINGS　1999
A single chip MPEG2 MP@ML video encoder with multi chip conf i guration for a single board MP@HL encoder Peer-reviewed

T oshihiro Minami, T oshio Kondo, K oyo Nitta, K azuhito Suguri, M itsuo Ikeda, T akeshi, Yoshitome, H iroshi, Wata n abe, H iroe Iwasaki, K, atsuyuki Ochiai, J iro Naganuma, Makoto Endo, E iichi Yamagishi, T akuro Takahashi, K oichi Tadaishi, Y utaka Tashiro, N aoki Kobayashi, Tuneo Okubo, Takeshi Ogura, R. Kasai

Hot Chips X　10　123-131　1998/08
A Study of Scheduling Methods for Switching Processing on a Tightly Coupled Multiprocessor Peer-reviewed

Hiroe Iwasa k i, Hiroyuki Nakamura, Kaoru Kosai, Shoji Kimura

IEEE International Conference on Communication Systems 3　30　(7)　1-7　1996
A Program Execution Control based on IROS for Achieving High Performance and Quick Service Provisioning Peer-reviewed

Kaoru Kosai, Hiroe Iwasaki , Hiroyuki Nakamura, and Shoji Kimura

IEEE International Conference on Communication Systems 3　25　(9)　1-6　1996

Show all ︎Show first 5

Misc. 77

滑らかな動きを表現する高フレームレート映像符号化技術 (特集高臨場UXサービスを支える技術)

大森優也, 大西隆之, 岩崎裕江, 清水淳

NTT技術ジャーナル　29　(10)　15-18　2017/10
Publisher: 電気通信協会
ISSN： 0915-2318
A 4K/60p HEVC Real-time Encoder with HDR Video

116　(496)　25-30　2017/03/06
Publisher: 電子情報通信学会
ISSN： 0913-5685
A Power-saving Method for Real-time HEVC Encoder LSIs

116　(335)　33-38　2016/11/29
Publisher: 電子情報通信学会
ISSN： 0913-5685
Development of 8K video encoder with HEVC realtime encoder LSIs

40　(35)　13-16　2016/10
Publisher: 映像情報メディア学会
ISSN： 1342-6893
Study of Efficient Motion Estimation Methods for High Frame Rate Video Encoders

116　(20)　53-58　2016/05/09
Publisher: 電子情報通信学会
ISSN： 0913-5685
C-12-26 A study of gradual low power ASIC design methodology

Kusaba Ritsu, Onishi Takayuki, Iwasaki Hiroe, Nishida Yukikuni, Ikeda Mitsuo, Sagata Atsushi, Shimizu Atsushi

Proceedings of the IEICE General Conference　2015　(2)　87-87　2015/02/24
Publisher: The Institute of Electronics, Information and Communication Engineers
C-12-32 The research of multi-chip architecture for high efficiency video multiplexing

Kusaba Ritsu, Onishi Takayuki, Ikeda Mitsuo, Iwasaki Hiroe, Sagata Atsushi, Shimizu Atsushi

Proceedings of the Society Conference of IEICE　2014　(2)　84-84　2014/09/09
Publisher: The Institute of Electronics, Information and Communication Engineers
B-11-26 Verification on coding method for ultra HD video services by subjective quality assessment

Kawashima Kimiko, Okamoto Jun, Sano Takashi, Onishi Takayuki, Sagata Atsushi, Nitta Koyo, Iwasaki Hiroe, Hayashi Takanori

Proceedings of the Society Conference of IEICE　2014　(2)　257-257　2014/09/09
Publisher: The Institute of Electronics, Information and Communication Engineers
I-033 Inter TU size early determination in HEVC for 8K video

Jia Su, Onishi Takayuki, Iwasaki Hiroe, Shimizu Atsushi

13　(3)　241-242　2014/08/19
Publisher: Forum on Information Technology

More details Close

The up-to-date video standard, High Efficiency Video Coding (HEVC) supports 8K UHD (4320p). It is a digital video format approved by the ITU-T and ISO/IEC. However, the complexity issues such as variable transform unit (TU) size in HEVC limit the development of both software and hardware video encoder engine. By considering the increasing difficulties for 8K UHD, this paper analyses the 8K video feature from residue and frequency aspects. Meanwhile, the performances differences are illustrated by comparing the proposed algorithm in inter TU size early determination for HEVC, which compared the same video contents in 8K with HD 10bit format. The conclusion is made from the experiment that image quality is guaranteed with the sacrifice of the computational complexity.
I-030 A Study of Mode Restriction Method for HEVC Intra Prediction Using Edge Information of Input Images

YOKOHARI Kazuya, SANO Takashi, ONISHI Takayuki, IWASAKI Hiroe, SHIMIZU Atsushi

13　(3)　235-236　2014/08/19
Publisher: Forum on Information Technology
I-031 A Study of Parallel Encoding Framework for UHDTV

ONISHI Takayuki, SANO Takashi, NISHIDA Yukikuni, KUSABA Ritsu, SAGATA Atsushi, IWASAKI Hiroe, IKEDA Mitsuo, SHIMIZU Atsushi

13　(3)　237-238　2014/08/19
Publisher: Forum on Information Technology
D-11-63 A CONSIDERATION ON MOTION ESTIMATION USING PREDICTIVE MOTION VECTOR FOR HEVC

Sano Takashi, Onishi Takayuki, Iwasaki Hiroe, Shimizu Atsushi

Proceedings of the IEICE General Conference　2014　(2)　63-63　2014/03/04
Publisher: The Institute of Electronics, Information and Communication Engineers
Hardware realization for H.265/HEVC

IWASAKI Hiroe

IEICE technical report. Image engineering　113　(468)　113-113　2014/02/27
Publisher: The Institute of Electronics, Information and Communication Engineers
An H.264/AVC video encoder LSI for broadcasting infrastructure and its applications

NITTA Koyo, IKEDA Mitsuo, IWASAKI Hiroe, KAMIKURA Kazuto, JOZAWA Hirohisa

IEICE technical report. Signal processing　111　(257)　19-24　2011/10/24
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

This paper describes our H.264/AVC video encoder LSI, "SARA", for broadcasting infrastructures and its applications. The SARA is the world first video encoder LSI that can support High422 profile specified by H.264/AVC standard. It has a lot of features required for broadcasting infrastructures. As for its applications, our MPEG2-to-H.264/AVC transcoder, which are utilized in a retransmission service of terrestrial digital TV broadcasts over IP, and our real-time 3D HDTV MVC encoder are presented with the technologies they uses.
Full HDTV Real-time 3D Video Encoder

2010　(6)　1-5　2011/04
Publisher: 情報処理学会
ISSN： 2186-2583
A Software-based H.264/AVC HDTV Real-time Interactive CODEC Architecture Using Parallel Processing

SANO TAKASHI, ONISHI TAKAYUKI, IWASAKI HIROE, KAMIKURA KAZUTO, NAGANUMA JIRO

68　(3)　C1-C5　2010/03/04
Publisher: 情報処理学会
ISSN： 0919-6072
D-11-8 STEREO IMAGE TRANSMISSION SYSTEM USING H.264 SOFTWARE-BASED HDTV CODEC

Sano Takashi, Ohnishi Takayuki, Iwasaki Hiroe, Kamikura Kazuto

Proceedings of the IEICE General Conference　2010　(2)　8-8　2010/03/02
Publisher: The Institute of Electronics, Information and Communication Engineers
D-11-9 Development of a 12-bit 4:2:2 AVC/H.264 HDTV Intra Encoder

Onishi Takayuki, Nitta Koyo, Iwasaki Hiroe, Kamikura Kazuto

Proceedings of the IEICE General Conference　2010　(2)　9-9　2010/03/02
Publisher: The Institute of Electronics, Information and Communication Engineers
NGNフォーカス座談会:NGN商品化から1年を振り返る

萬本正信, 石井晋司, 岩崎裕江

NTT技術ジャ-ナル　21　(10)　46-49　2009/10
Publisher: 電気通信協会
ISSN： 0915-2318
NGNフォーカス座談会:NGN商品化から1年を振り返る

萬本正信, 石井晋司, 岩崎裕江

NTT技術ジャ-ナル　21　(7)　26-29　2009/07
Publisher: 電気通信協会
ISSN： 0915-2318
D-11-9 Performance Evaluation of Low-delay FEC on H.264/AVC HDTV Real-time Communication Software CODEC

Onishi Takayuki, Sano Takashi, Iwasaki Hiroe, Naganuma Jiro

Proceedings of the IEICE General Conference　2009　(2)　9-9　2009/03/04
Publisher: The Institute of Electronics, Information and Communication Engineers
D-11-11 A Professional-use Transcoder for Retransmission of Digital Terrestrial TV Broadcast over IF : Functions for High-quality Transcoding

Sano Takashi, Ikeda Mitsuo, Iwasaki Hiroe, Nitta Koyo, Onishi Takayuki, Sagata Atsushi, Nakajima Yasuyuki, Inamori Minoru, Yoshitome Takeshi, Matsuda Hiroaki, Tanida Ryuichi, Shimizu Atsushi, Nakamura Ken, Naganuma Jiro

Proceedings of the IEICE General Conference　2009　(2)　11-11　2009/03/04
Publisher: The Institute of Electronics, Information and Communication Engineers
An H.264/AVC High422 profile and MPEG-2 422 profile encoder LSI for HDTV broadcasting infrastructures

NITTA Koyo, IKEDA Mitsuo, IWASAKI Hiroe, ONISHI Takayuki, SANO Takashi, SAGATA Atsushi, NAKAJIMA Yasuyuki, INAMORI Minoru, YOSHITOME Takeshi, MATSUDA Hiroaki, TANIDA Ryuuichi, SHIMIZU Atsushi, NAKAMURA Ken, NAGANUMA Jiro

IPSJ SIG Notes　2009　(1)　117-122　2009/01/13
Publisher: Information Processing Society of Japan (IPSJ)
ISSN： 0919-6072

More details Close

An H.264/AVC encoder LSI (named "SARA/E") that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains three motion estimation and compensation (ME/MC) engines with search ranges of -217.75 to +199.75(H)/-109.75 to +145.75(V), which can utilize almost all H.264/AVC ME/MC tools, multiple reference frame, variable block size, 0.25-pel prediction, macroblock adaptive field/frame prediction (MBAFF), temporal/spatial direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2dB to 1.7dB higher than the JM. It was successfully fabricated in a 90nm technology. It integrates 140 million transisters.
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures

NITTA Koyo, IKEDA Mitsuo, IWASAKI Hiroe, ONISHI Takayuki, SANO Takashi, SAGATA Atsushi, NAKAJIMA Yasuyuki, INAMORI Minoru, YOSHITOME Takeshi, MATSUDA Hiroaki, TANIDA Ryuuichi, SHIMIZU Atsushi, NAKAMURA Ken, NAGANUMA Jiro

IEICE technical report　108　(375)　117-122　2009/01/06
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

An H.264/AVC encoder LSI (named "SARA/E") that supports High422 profile, as well as 422 profile of MPEG-2, has been developed for HDTV broadcasting infrastructures. It contains three motion estimation and compensation (ME/MC) engines with search ranges of -217.75 to +199.75(H) / -109.75 to +145.75(V), which can utilize almost all H.264/AVC ME/MC tools, multiple reference frame, variable block size, 0.25-pel prediction, macroblock adaptive field/frame prediction (MBAFF), temporal/spatial direct mode, and weighted prediction. Our evaluations show that it can encode fast moving scenes with 1.2dB to 1.7dB higher than the JM. It was successfully fabricated in a 90nm technology. It integrates 140 million transisters.
H.264/AVC CODEC LSI構成技術とIP再送信サービスへの適用

新田高庸, 岩崎裕江, 長沼次郎

NTT技術ジャーナル　21　(3)　2009

ISSN： 0915-2318
H.264/AVC CODEC LSI構成技術とIP再送信サービスへの適用

新田高庸, 岩崎裕江, 長沼次郎

NTT技術ジャーナル　21　(10)　2009

ISSN： 0915-2318
D-11-10 A Professional-use Transcoder for Retransmission of Digital Terrestrial TV Broadcast over IP : Structure of MPRG-2/H.264 Transcoder

Sagata Atsushi, Ikeda Mitsuo, Iwasaki Hiroe, Nitta Koyo, Onishi Takayuki, Sano Takashi, Nakajima Yasuyuki, Inamori Minoru, Yoshitome Takeshi, Matsuda Hiroaki, Tanida Ryuichi, Shimizu Atsushi, Nakamura Ken, Naganuma Jiro

Proceedings of the IEICE General Conference　10-10　2009
Publisher: The Institute of Electronics, Information and Communication Engineers
D-11-110 SARA : A Professional H.264/AVC Encoder LSI for HDTV CODEC Systems : Design Concepts and Basic Architecture

Nitta Koyo, Ikeda Mitsuo, Iwasaki Hiroe, Onishi Takayuki, Sano Takashi, Sagata Atsushi, Nakajima Yasuyuki, Inamori Minoru, Yoshitome Takeshi, Matsuda Hiroaki, Tanida Ryuichi, Shimizu Atsushi, Nakamura Ken, Naganuma Jiro

Proceedings of the IEICE General Conference　2008　(2)　110-110　2008/03/05
Publisher: The Institute of Electronics, Information and Communication Engineers
D-11-112 SARA : A Professional H.264/AVC Encoder LSI for HDTV CODEC Systems : Search Module Configuration

Onishi Takayuki, Ikeda Mitsuo, Iwasaki Hiroe, Nitta Koyo, Sano Takashi, Sagata Atsushi, Nakajima Yasuyuki, Inamori Minoru, Yoshitome Takeshi, Matsuda Hiroaki, Tanida Ryuichi, Shimizu Atsushi, Nakamura Ken, Naganuma Jiro

Proceedings of the IEICE General Conference　2008　(2)　112-112　2008/03/05
Publisher: The Institute of Electronics, Information and Communication Engineers
D-11-113 SARA : A Professional H.264/AVC Encoder LSI for HDTV CODEC Systems : Architecture of Firmware for Video Quality Improvement

Sagata Atsushi, Ikeda Mitsuo, Iwasaki Hiroe, Nitta Koyo, Onishi Takayuki, Sano Takashi, Nakajima Yasuyuki, Inamori Minoru, Yoshitome Takeshi, Matsuda Hiroaki, Tanida Ryuichi, Shimizu Atsushi, Nakamura Ken, Naganuma Jiro

Proceedings of the IEICE General Conference　2008　(2)　113-113　2008/03/05
Publisher: The Institute of Electronics, Information and Communication Engineers
D-11-114 SARA/D : A Professional HDTV H.264/AVC Decoder LSI

Iwasaki Hiroe, Ikeda Mitsuo, Nitta Koyo, Onishi Takayuki, Sano Takashi, Sagata Atsushi, Nakajima Yasuyuki, Inamori Minoru, Yoshitome Takeshi, Matsuda Hiroaki, Tanida Ryuichi, Shimizu Atsushi, Nakamura Ken, Naganuma Jiro

Proceedings of the IEICE General Conference　2008　(2)　114-114　2008/03/05
Publisher: The Institute of Electronics, Information and Communication Engineers
放送プロ向けHDTV H.264/AVCデコーダLSI(SARA/D)

岩崎裕江, 池田充郎, 新田高庸, 大西隆之, 佐野卓, 嵯峨田淳, 中島靖之, 稲森稔, 吉留健, 松田宏朗, 谷田隆一, 清水淳, 中村健, 長沼次郎

電子情報通信学会大会講演論文集　2008　2008

ISSN： 1349-1369
D-11-15 H.264/AVC Real-time Parallel Software CODEC for Full-duplex Transmission with HDTV Scalability

Sano Takashi, Iwasaki Hiroe, Naganuma Jiro

Proceedings of the IEICE General Conference　2　15-15　2008
Publisher: The Institute of Electronics, Information and Communication Engineers
D-11-111 SARA : A Professional H.264/AVC Encoder LSI for HDTV CODEC Systems : Architecture of HDTV Encoder

Nakajima Yasuyuki, Ikeda Mitsuo, Iwasaki Hiroe, Nitta Koyo, Onishi Takayuki, Sano Takashi, Sagata Atsushi, Inamori Minoru, Yoshitome Takeshi, Matsuda Hiroaki, Tanida Ryuichi, Shimizu Atsushi, Nakamura Ken, Naganuma Jiro

Proceedings of the IEICE General Conference　111-111　2008
Publisher: The Institute of Electronics, Information and Communication Engineers
J_034 MPEG-2 to H.264 Low Delay HDTV Software Transcoder

Sano Takashi, Iwasaki Hiroe, Naganuma Jiro

5　(3)　265-266　2006/08/21
Publisher: Forum on Information Technology
Single-chip MPEG-2 422P@HL CODEC LSI and its applications

NAGANUMA Jiro, IWASAKI Hiroe, IKEDA Mitsuo, NAKAMURA Ken, YOSHITOME Takeshi, ONISHI Takayuki, NAKAJIMA Yasuyuki, TASHIRO Yutaka, NITTA Koyo, OGURA Mitsuo, MINAMI Toshihiro, ENDO Makoto, YASHIMA Yoshiyuki

ITE technical report　28　(49)　41-46　2004/09/10
Publisher: 映像情報メディア学会
ISSN： 1342-6893
Single-chip MPEG-2 422P@HL CODEC LSI and its applications

NAGANUMA Jiro, IWASAKI Hiroe, IKEDA Mitsuo, NAKAMURA Ken, YOSHITOME Takeshi, ONISHI Takayuki, NAKAJIMA Yasuyuki, TASHIRO Yutaka, NITTA Koyo, OGURA Mitsuo, MINAMI Toshihiro, ENDO Makoto, YASHIMA Yoshiyuki

Technical report of IEICE. ICD　104　(288)　41-46　2004/09/03
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multi-chip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. This architecture consists of triple encoding cores, a decoding core, a multiplexer/de-multiplexer core, and several dedicated application-specific hardware modules with a hierarchical flexible communication scheme for high-performance data transfer. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multi-chip configuration. The VASA implements MPEG-2 Video and system CODEC with generic audio CODEC interfaces. An LSI incorporating the architecture was successfully fabricated using the 0.13-^m eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multi-View/-angled live TV applications with a multi-chip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.
J-003 A study on low delay FEC for video communication using MPEG-2 software CODEC

Onishi Takayuki, Iwasaki Hiroe, Naganuma Jiro, Yashima Yoshiyuki

3　(3)　205-206　2004/08/20
Publisher: Forum on Information Technology
J-004 Low-delay MPEG-2 CODEC System for Interactive Visual Communication

Inamori Minoru, Onishi Takayuki, Iwasaki Hiroe, Ikeda Mitsuo, Naganuma Jiro

3　(3)　207-208　2004/08/20
Publisher: Forum on Information Technology
J-074 Parallel MPEG-2 HDTV Real-time Software Encoder

Iwasaki Hiroe, Naganuma Jiro

3　(3)　369-370　2004/08/20
Publisher: Forum on Information Technology
Server-less Implementation of Multi-point Video Conference Software : Architecture, Implementation, and Evaluation

IWASAKI Hiroe, ONISHI Takayuki, NAGANUMA Jiro, ENDO Makoto, YASHIMA Yoshiyuki

IEICE technical report. Signal processing　104　(31)　35-40　2004/04/16
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

This paper proposes a server-less implementation of multi-point video conference software on IP networks, and evaluates its performance and usefulness. The codec consists of a high-speed encoder, a decoder, an IP sender/receiver, an error recovery controller, and a total controller. The software provides multi-point video conference on a PC with at least 2.4 GHz CPU via IP networks. An encoder sends its bitstream to multi-point decoders, decoder processes receive bitstreams from multi-point encoders. The IP send/receive module controls error recovery each bitstream. This software with encoder/decoder direct IP transmission attains low delay of 99ms(M=1,N=1) to 165ms(M=3,N=:3) inculding input, encoding, transmitting, decoding, and output delays.
Single-chip High-quality MPEG-2 CODEC LSI(ISIL)

IWASAKI Hiroe, NAGANUMA Jiro, NAKAJIMA Yasuyuki, TASHIRO Yutaka, NAKAMURA Ken, YOSHITOME Takeshi, ONISHI Takayuki, IKEDA Mitsuo, IZUOKA Takaaki, ENDO Makoto, YASHIMA Yoshiyuki

111　(105)　25-30　2003/10/23
Publisher: Information Processing Society of Japan (IPSJ)
ISSN： 0919-6072

More details Close

This paper proposes single-chip high-quality MPEG-2 CODEC LSI (ISIL) for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multi-plexer/ de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 30.7 million transistors using the 0.13μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 10801 decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.
Single-chip High-quality MPEG-2 CODEC LSI (ISIL)

IWASAKI Hiroe, NAGANUMA Jiro, NAKAJIMA Yasuyuki, TASHIRO Yutaka, NAKAMURA Ken, YOSHITOME Takeshi, ONISHI Takayuki, IKEDA Mitsuo, IZUOKA Takaaki, ENDO Makoto, YASHIMA Yoshiyuki

Technical report of IEICE. ICD　103　(381)　25-30　2003/10/16
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

This paper proposes single-chip high-quality MPEG-2 CODEC LSI(ISIL) for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 10801 decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 30.7 million transistors using the 0.13-μm seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 10801 decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.
1チップHDTV MPEG-2 CODEC LSI構成技術--VASA (特集 HDTV映像伝送・配信システム)

長沼次郎, 岩崎裕江, 新田高庸

NTT技術ジャ-ナル　15　(9)　12-15　2003/09
Publisher: 電気通信協会
ISSN： 0915-2318
組込み用オールインワンHDTV全二重CODEC LSI構成技術--ISIL (特集 HDTV映像伝送・配信システム)

岩崎裕江, 長沼次郎, 中島靖之

NTT技術ジャ-ナル　15　(9)　16-20　2003/09
Publisher: 電気通信協会
ISSN： 0915-2318
1チップMPEG-2 422P@HL CODEC LSI(VASA) エンコーダ部と外部メモリIF部の構成

岩崎裕江, 長沼次郎, 新田高庸, 中村健, 吉留健, 小倉充雄, 中島靖之, 田代豊, 八島由幸

情報科学技術フォーラム　FIT 2003　2003
1チップMPEG-2 422P@HL CODEC LSI(VASA) 拡張エンコード/デコード機能

中村健, 吉留健, 長沼次郎, 岩崎裕江, 新田高庸, 小倉充雄, 中島靖之, 田代豊, 八島由幸

情報科学技術フォーラム　FIT 2003　2003
1チップMPEG-2 422P@HL CODEC LSI(VASA) デコーダ部と外部メモリIF部の構成

中島靖之, 田代豊, 小倉充雄, 長沼次郎, 岩崎裕江, 新田高庸, 中村健, 吉留健, 八島由幸

情報科学技術フォーラム　FIT 2003　2003
1チップMPEG-2 422P@HL CODEC LSI (VASA) 拡張可能なMUXの構成

大西隆之, 長沼次郎, 岩崎裕江, 新田高庸, 中村健, 吉留健, 小倉充雄, 中島靖之, 八島由幸

情報科学技術フォーラム　FIT 2003　2003
1チップMPEG-2 422P@HL CODEC LSI (VASA) ファームウェア構成

池田充郎, 長沼次郎, 岩崎裕江, 新田高庸, 中村健, 吉留健, 小倉充雄, 中島靖之, 八島由来

情報科学技術フォーラム　FIT 2003　2003
1チップMPEG-2 422P@HL CODEC LSI(VASA) 設計思想と基本アーキテクチャー

長沼次郎, 岩崎裕江, 新田高庸, 中村健, 吉留健, 小倉充雄, 中島靖之, 田代豊, 八島由幸

情報科学技術フォーラム　FIT 2003　2003
MPEG-2 real-time software CODEC for full-duplex transmission applications over IP networks

IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

IEICE technical report. Image engineering　102　(151)　13-18　2002/06/20
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

This paper proposes a real-time MPEG-2 software CODEC for full-duplex transmission applications, and evaluates its performance and usefulness. The CODEC consists of a high-speed encoder/decoder, an IP sender/receiver, and an error recovery controller. Each encoder/decoder is accelerated and optimized by exploiting fast algorithms and data-level parallelism. The IP sender/receiver combination achieves low delay owing to a direct translating of each elementary stream of video and audio into UDP/IP packets. The error recovery controller carries out simple but powerful error tolerance against packet loss over IP networks. This CODEC attains low delay of 99 ms(M=1,N=1) to 165 ms(M=3,N=3) including input, encoding, transmitting, decoding, and output delays, and maintains a normal frame rate of 30 fps (frames per second) and more than 20 fps even under a fairly heavy network load. It provides sufficiently good performance for use as a real-time full NTSC-size CODEC on a PC of at least 1.2GHz CPU.
リアルタイムMPEG-2 ソフトウェアコーデック

岩崎裕江, 長沼次郎

第63回全国大会講演論文集　2001　(1)　613-614　2001/09/26
Control structure of an MPEG-2 video encoder LSI for HDTV

NITTA Koyo, IWASAKI Hiroe, IKEDA Mitsuo, SUGURI Kazuhito, YOSHITOME Takeshi, KONDO Toshio

Technical report of IEICE. FTS　101　(3)　65-72　2001/04/13
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

We developed a single chip MPEG-2 encoder, called SuperENC. The structural feature is that the chip has a systolic array and an SIMD processor for motion estimation/compensation and a processor-type SDRAM interface unit, called SDIF, with prioritizing the transmission for external SDRAMs over the internal coding operation. The SPMD-type cooperation using the nine chips deals with HDTV encoding requiring for high operation capability more than 50 GOPS and high-speed data transmission of 2 GB/s. This SuperENC has high function and control flexibility obtained by adequate division of control work for a RISC controller, the SIMD and the SDIF on the chip.
A Study on an MPEG-2 Video Software Codec

OGURA Mitsuo, IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

Proceedings of the IEICE General Conference　2000　114-114　2000/03/07
Publisher: The Institute of Electronics, Information and Communication Engineers
Real-Time MPEG-2 Video Software Encoder with Video Capture

Iwasaki Hiroe, Naganuma Jiro, Endo Makoto

Proceedings of the IEICE General Conference　113-113　2000
Publisher: The Institute of Electronics, Information and Communication Engineers
27-4 Real-time MPEG-2 video software encoder on parallel computer systems

Iwasaki Hiroe, Naganuma Jiro, Endo Makoto

PROCEEDINGS OF THE ITE ANNUAL CONVENTION　2000　389-390　2000
Publisher: The Institute of Image Information and Television Engineers
DOI： 10.11485/iteac.2000.0_389 　

ISSN： 1343-1846

More details Close

This paper proposes a real-time MPEG-2 video software encoder on parallel computer systems and evaluates its performance. This parallel software encoder consists of a small number of high-speed encoding elements and a frame-synchronization controller with I/O. This encoder provides sufficient performance for real-time full NTSC-size encoding on a dual-PC.
Real-time MPEG-2 Video Software Encoder

IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

Proceedings of the Society Conference of IEICE　1999　130-130　1999/08/16
Publisher: The Institute of Electronics, Information and Communication Engineers
An On-Chip Real-time OS for Multimedia Applications

58　53-53　1999/03/09
MPEG-2 Video Software Encoder

OCHIAI Katsuyuki, IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

Proceedings of the IEICE General Conference　1999　151-151　1999/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
MPEG-2 Video Software Encoder

NAGANUMA Jiro, IWASAKI Hiroe, OCHIAI Katsuyuki, ENDO Makoto

Proceedings of the IEICE General Conference　149-149　1999
Publisher: The Institute of Electronics, Information and Communication Engineers
Concurrent Design Environment for System LSIs : A Single-chip MPEG-2 MP@ML Video Encoder LSI

OCHIAI Katsuyuki, IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

IEICE technical report. Computer systems　98　(291)　39-46　1998/09/22
Publisher: The Institute of Electronics, Information and Communication Engineers

More details Close

This paper proposes a new hardware and software concurrent design environment exploiting a software-platform for embedded system LSIs (system LSIs), and evaluates its benefits on a practical single-chip MPEG-2 MP@ML video encoder LSI disign. The software-platform consists of an instruction set level simulator of core CPU and a function level simulator of application-specific hardware. This design environment provides sufficient performance for simulating several to several ten millions cycles of a large embedded software without hardware description.
Concurrent Design Environment for Embedded System LSIs

OCHIAI Katsuyuki, IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

Proceedings of the Society Conference of IEICE　1998　49-49　1998/09/07
Publisher: The Institute of Electronics, Information and Communication Engineers
An MPEG2 video encoder LSI expandable into HDTV

KONDO Toshio, MINAMI Toshihiro, NITTA Koyo, SUGURI Kazuhito, IKEDA Mitsuo, IWASAKI Hiroe, OCHIAI Katsuyuki, WATANABE Hiroshi

Technical report of IEICE. ICD　98　(244)　37-43　1998/08/20
Publisher: The Institute of Electronics, Information and Communication Engineers

More details Close

We have developed a single chip MPEG2 MP@ML video encoder LSI expandable into MP@HL. Though this LSI consumes only 2.6 GOPS for the first motion estimation, it has wide search range of horizontal±211.5 pixels and vertical ±113.5 pixels. The reason is that both position and range for the search rea are adaptively controlled in the motion estimation. In addition to this wide search range, the LSI has an inter-LSI transfer interface, a programmable SDRAM interface and a SIMD processor for the second motion estimation and motion compensation, on the chip, so that series of the several LSIs offer high quality MP@HL coding capability. The die was fabricated by 0.25μm4-metal CMOS technology. The power consumption is 2W at 2.5V to internal circuits, 3.3V to I/O circuits and 81MHz operation frequency.
An on-chip real-time OS for an Embedded System LSI

IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

IPSJ SIG Notes　77　(15)　49-54　1998/02/26
Publisher: Information Processing Society of Japan (IPSJ)
ISSN： 0919-6072
Concurrent Design Environment for Embedded System LSIs

OCHIAI Katsuyuki, IWASAKI Hiroe, NAGANUMA Jiro, ENDO Makoto

Proceedings of the IEICE General Conference　104-104　1998
Publisher: The Institute of Electronics, Information and Communication Engineers
A Real-time OS on an Embedded System LSI

55　226-227　1997/09/24
I/O Buffer Modeling in A Virtual LSI for Firmware Development

ENDO Makoto, IWASAKI Hiroe, NAGANUMA Jiro

Proceedings of the IEICE General Conference　1997　125-125　1997/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers
High-Speed Simulation Environment for Embedded System LSIs

NAGANUMA Jiro, IWASAKI Hiroe, ENDO Makoto

Proceedings of the IEICE General Conference　1997　126-126　1997/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers
Design Experiences of MPEG2 MUX Firmware with Real-Time OS using A Virtual LSI

ENDO Makoto, IWASAKI Hiroe, NAGANUMA Jiro

Proceedings of the Society Conference of IEICE　64-64　1997
Publisher: The Institute of Electronics, Information and Communication Engineers
A Study on Failure Management of the OS-Kernel in Tightly Coupled Multiprocessor Systems

Kimura Shoji, Nakamura Hiroyuki, Iwasaki Hiroe, Kosai Shoji

Proceedings of the IEICE General Conference　1996　(2)　151-151　1996/03/11
Publisher: The Institute of Electronics, Information and Communication Engineers
A Real-time OS on a Chip for MPEG2 System Multiplexer/Demultiplexer LSI

Iwasaki Hiroe, Naganuma Jiro, Endo Makoto

Proceedings of the Society Conference of IEICE　158-158　1996
Publisher: The Institute of Electronics, Information and Communication Engineers
UNIX System Call in A Virtual LSI for Firmware Development

ENDO Makoto, IWASAKI Hiroe, NAGANUMA Jiro

Proceedings of the Society Conference of IEICE　157　157-157　1996
Publisher: The Institute of Electronics, Information and Communication Engineers
A Study of Scheduling methods for Switching Processing on a Tightly Coupled Multiprocessor

Iwasaki Hiroe, Nakamura Hiroyuki, Kosai Syoji

Proceedings of the IEICE General Conference　1995　(2)　140-140　1995/03/27
Publisher: The Institute of Electronics, Information and Communication Engineers
A study of interrupt control methods on Tightly Coupled Multiprocessors

Iwasaki Hiroe, Kosai Syoji, Matsuda Chikashi, Miki Shuji

Technical report of IEICE. SSE　94　(362)　25-30　1994/11/24
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

This paper introduces the reusable software environment,which makes the NOSES(Non-stop Service Enhansible Software)platform applicable to a wide range of communication systems having different hardware,application programs,and operational services. The reusable software environment is composed of software selection techniques,customized data tuning techniques and operational service creation techniques.Emphasis is placed on the functions of the MO management software components and the tools for supporting operational service creation techniques which make NOSES widely applicable to TMN based communication systems.
A study of a Mutual Exclusion for a Tightly Coupled Multiprocessor

Iwasaki Hiroe, Nakamura Hiroyuki, Kosai Shoji

Technical report of IEICE. SSE　93　(501)　87-92　1994/03/11
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

Mutual exclusion is important for the tightly coupled multiprocessing.This paper considers the methods of mutual exclusion for programs in switching systems,such as failure processing handlers,cyclic start procedures and tasks,which have shared resources implemented by the functions of IROS(Interface for Realtime Operating Systems).This paper also shows the effect of the consideration to the type of programs on the performance.
A study of scheduling methods for a switching processing on a tightly coupled multiprocessor

Iwasaki Hiroe, Watanabe Nobuyuki

Technical report of IEICE. SSE　93　(72)　49-54　1993/05/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

More details Close

The scheduling methods on the Tightly Coupled Multiprocessor are evaluated in terms of the communication switching systems.The two application models,which have an execution level control,are considered.Each model is applied three scheduling methods,and are evaluated by the CPU utilization and the Waiting time of programs. The characteristics for each scheduling method are studied.This paper indicates which scheduling mothod is applicable to certain application program.

Show all ︎Show first 5

Presentations 7

画像特徴量を用いたブロック分割による VVC イントラエンコーダの高速化

内山力太, 小野内花倫, 丹羽直也, 佐藤雅之, 岩崎裕江, 小林広明

情報処理学会システムアーキテクチャ研究会　2024/08/09
モバイルSINETを利用した同時複数映像ストリーム伝送

小浦陽, 丹羽直也, 岩崎裕江, 漆谷重雄

映像情報メディア学会 BCT研究会　2024/06/07
VVCの⾼速化のためのフレーム差分画像を⽤いたブロック分割に関する⼀検討

原田零生, 近藤嘉昭, 佐藤雅之, 岩崎裕江, 小松一彦, 小林広明

情報処理学会第86回全国大会
渋滞解消問題を用いたイジングマシンの評価

百南匠人, 丹羽直也, 小松一彦, 岩崎裕江, 小林広明

電子情報通信学会
階層的ブロック分散値評価に基づくブロック分割決定手法

小嶋優輔, 岩崎裕江, 江川隆輔

電子情報通信学会
VVC 映像符号化並列処理のための映像分割に関する一検討

小野内花倫, 近藤嘉昭, 佐藤雅之, 岩崎裕江, 小松一彦, 小林広明

情報処理学会第85回全国大会
A Shared Cache Architecture for VVC Coding

Yoshiaki Kondo, Masayuki Sato, Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Hiroe Iwasaki, Ryusuke Egawa, Kazuhiko Komatsu, Hiroaki Kobayashi

2022 IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOLChips25)　2022/04/22

Show all Show first 5

Research Projects 1

Real-time video coding technology using the latest coding VVC/H.266 and its applications

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tokyo University of Agriculture and Technology

2022/04/01 - 2025/03/31