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Naofumi Homma

Section

Research Institute of Electrical Communication

Job title

Professor

Degree

博士（情報科学）（東北大学）
修士（情報科学）（東北大学）

researchmap

https://researchmap.jp/read0191593

J-GLOBAL ID

200901076284963967

Committee Memberships 76

Area Chair

2025/01 - Present
IEEE Computer Society Technical Committee on MVL　Chair

2024/01 - Present
電子情報技術産業協会（JEITA）　ハードウェアセキュリティ技術分科会委員長

2017/04 - Present
Journal of Cryptographic Engineering Editorial Board　Associate Editor

2016/01 - Present
Conference on Cryptographic Hardware and Embedded Systems (CHES) Steering Committee　Steering Committee Member

2014/10 - Present
CRYPTREC暗号技術評価委員会　委員

2013/04 - Present
CRYPTREC暗号技術検討会　構成員

2011/09 - Present
IEEE Computer Society Technical Committee on MVL　Vice Chair

2020/01 - 2023/12
内閣サイバーセキュリティセンター　研究・産学官連携戦略WG委員

2020/07 - 2021/03
電子情報通信学会ハードウェアセキュリティ研究会　研究専門委員

2018/04 - Present
IEEE International Symposium on Multiple-Valued Logic Program Committee Chair

2022/07 - 2023/05
IEEE Sendai Section　Membership Development Committee Chair

2020/01 - 2021/12
The 40th Annual International Conference on the Theory and Applications of Cryptographic Techniques (EuroCrypt 2021), Program Committee Member

2020/07 - 2021/05
The 10th International Conference on Security, Privacy and Applied Cryptographic Engineering (SPACE 2020, Program Committee Member

2020/03 - 2020/12
Top Picks in Hardware and Embedded Security 2020, Technical and Program Committee Member

2020/08 - 2020/11
2020 IEEE International Symposium on Multiple-Valued Logic, Program Committee Co-Chair

2019/09 - 2020/11
2020 International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2020)　Program Committee Member

2019/08 - 2020/10
Workshop on Security Proofs for Embedded Systems 2020 (PROOFS 2020), Program Committee Member

2020/04 - 2020/09
多値論理研究会　委員長

2018/09 - 2020/09
IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), Editorial Board　Member

2017/07 - 2020/09
International Conference on Cryptographic Hardware and Embedded Systems (CHES) Program Committee　Member

2009/03 - 2020/09
IEEE Sendai Section Student Activity Committee　Chair

2018/01 - 2019/12
2019 IEEE International Symposium on Multiple-Valued Logic, Program Committee　Co-chair

2018/09 - 2019/05
2019 International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2019) Program Committee　Member

2018/07 - 2019/04
Workshop on Security Proofs for Embedded Systems 2018 (PROOFS 2018) Program Committee　Member

2018/01 - 2018/09
多値論理研究会　会計幹事

2016/09 - 2018/09
多値論理研究会　会計監事

2016/09 - 2018/09
多値論理研究会　会計監事

2016/09 - 2018/09
2018 IEEE International Symposium on Multiple-Valued Logic Program Committee　Member

2017/09 - 2018/05
International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2018) Program Committee　Member

2017/08 - 2018/04
電子情報通信学会「Special Section on Multiple-Valued Logic and VLSI Computing」英文論文誌小特集号編集委員会　編集委員

2016/06 - 2017/08
電子情報通信学会「Special Section on Multiple-Valued Logic and VLSI Computing」英文論文誌小特集号編集委員会　編集委員

2016/06 - 2017/08
電子情報通信学会VLSI設計技術研究会　研究専門委員

2013/05 - 2017/05
電子情報通信学会VLSI設計技術研究会　研究専門委員

2013/05 - 2017/05
情報通信研究機構　専門委員

2014/04 - 2017/03
情報通信研究機構　専門委員

2014/04 - 2017/03
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2016/10 - 2017/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2016/10 - 2017/01
電子情報通信学会スマートインフォメディア研究会　運営委員

2010/05 - 2016/05
電子情報通信学会スマートインフォメディア研究会　運営委員

2010/05 - 2016/05
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2015/10 - 2016/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2015/10 - 2016/01
多値論理研究会　会計幹事

2013/09 - 2015/09
多値論理研究会　会計幹事

2013/09 - 2015/09
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2014/10 - 2015/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2014/10 - 2015/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2013/10 - 2014/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2013/10 - 2014/01
電子情報通信学会英文論文誌C 編集委員会　編集委員

2010/07 - 2013/05
電子情報通信学会英文論文誌C 編集委員会　編集委員

2010/07 - 2013/05
CRYPTREC暗号実装委員会　委員長

2009/08 - 2013/03
CRYPTRECサイドチャネル解析WG　主査

2009/08 - 2013/03
CRYPTREC暗号実装委員会　委員長

2009/08 - 2013/03
CRYPTRECサイドチャネル解析WG　主査

2009/08 - 2013/03
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2012/10 - 2013/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2012/10 - 2013/01
電子情報通信学会「暗号と情報セキュリティ実装技術」和文論文小特集編集委員会　編集幹事

2010/08 - 2012/05
電子情報通信学会「暗号と情報セキュリティ実装技術」和文論文小特集編集委員会　編集幹事

2010/08 - 2012/05
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2011/10 - 2012/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2011/10 - 2012/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2010/10 - 2012/01
電子情報通信学会「暗号と情報セキュリティ」英文論文小特集編集委員会　編集委員

2010/10 - 2012/01
多値論理研究会　技術幹事

2009/09 - 2011/09
多値論理研究会　技術幹事

2009/09 - 2011/09
情報処理学会　東北支部評議員

2009/06 - 2011/05
情報処理学会　東北支部評議員

2009/06 - 2011/05
CRYPTREC暗号モジュール委員会　電力解析実験WG委員

2006/11 - 2009/07
CRYPTREC暗号モジュール委員会　電力解析実験WG委員

2006/11 - 2009/07
情報処理学会　東北支部会計幹事

2007/05 - 2009/06
情報処理学会　東北支部会計幹事

2007/05 - 2009/06
電子情報通信学会「新デバイスアーキテクチャとシステムインテグレーション構築技術」英文論文小特集　編集委員

2005/12 - 2006/11
電子情報通信学会「新デバイスアーキテクチャとシステムインテグレーション構築技術」英文論文小特集　編集委員

2005/12 - 2006/11
IEEE Computer Society, Multiple-Valued Logic Technical Committee　Executive Sub-Committee Members at Large

2004/05 - 2006/05
IEEE Computer Society, Multiple-Valued Logic Technical Committee　Executive Sub-Committee Members at Large

2004/05 - 2006/05
科学技術振興機構戦略的創造研究推進事業さきがけ　「情報基盤と利用環境」領域研究者

2002/11 - 2006/03
科学技術振興機構戦略的創造研究推進事業さきがけ　「情報基盤と利用環境」領域研究者

2002/11 - 2006/03

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Professional Memberships 4

Information Processing Society of Japan
電子情報通信学会
IACR (International Association for Cryptologic Research)
IEEE (The Institute of Electrical and Electronics Engineers, Inc.)

Research Interests 4

Hardware security
Information Security
Electronic Design Automation
Hardware Algorithms

Research Areas 3

Informatics / Information theory /
Informatics / Information networks /
Informatics / Computer systems /

Awards 30

第21回ドコモ・モバイル・サイエンス賞先端技術部門優秀賞

2022/10　セキュリティハードウェア設計・検証理論の開拓とその応用
German Innovation Award 2018: Gottfried Wagener Prize 2018

2018/06　German Chamber of Commerce and Industry in Japan　Design Methodology for Lightweight Tamper-Resistant Cryptographic Hardware
The Ichimura Prize in Science for Distinguished Achievement

2018/04　Ichimura Foundation for New Technology　High-level Design Methodology for Hardware Algorithms and Its Applications
JSPS PRIZE

2018/02　Japan Society for the Promotion of Science　Theory of Hardware Algorithms for Computer Arithmetic and Its Application to Design of Cryptographic Hardware
SCIS 2014イノベーション論文賞

2015/01　電子情報通信学会
Best Paper Award at 16th International Conference on Cryptographic Hardware and Embedded Systems

2014/09　International Association for Cryptologic Research (IACR)
SCIS 2013イノベーション論文賞

2014/01　電子情報通信学会情報セキュリティ研究会
Best Symposium Paper Award 2013 IEEE International Symposium on Electromagnetic Compatibility

2013/08　IEEE EMC Society
The 37th Telecommunications Advancement Foundation Award

2022/03　Tackling Biased PUFs through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor
JMVL Contribution Award

2021/01
多値論理フォーラム奨励賞

2020/01　ブール多項式のZDD表現を用いたガロア体算術演算回路の形式的検証手法
多値論理フォーラム奨励賞

2019/01　スマートデバイスの電磁的な安全性評価に関する検討
多値論理フォーラム奨励賞

2017/01　多値論理研究会
LSIとシステムのワークショップ優秀ポスター賞

2015/05　電子情報通信学会
Letter of Appreciation for Collaboration and Technical Excellence

2015/02　National Institute of Standards and Technology (NIST)
みやぎ産業科学振興基金研究奨励賞

2013/06　みやぎ産業科学振興基金
多値論理フォーラム奨励賞

2013/01　多値論理研究会　正規基底表現されたガロア体上の算術演算回路の形式的設計に関する検討
RIEC Award

2012/11　東北大学電気通信研究所　VLSI向け算術アルゴリズムの高水準設計技術とその応用に関する研究
丸文学術賞

2012/03　丸文財団　算術演算LSIの高水準設計技術とその応用に関する研究
電子情報通信学会基礎・境界ソサイエティ編集活動感謝状

2011/09　電子情報通信学会
石田（實）記念財団研究奨励賞

2010/12　石田（實）記念財団
マルチメディア，分散，協調とモバイル (DICOMO2010) シンポジウム優秀論文賞

2010/08　マルチメディア，分散，協調とモバイル (DICOMO2010) シンポジウム
船井学術賞

2010/04　財団法人船井情報科学振興財団　ハードウェアアルゴリズムの高水準設計技術とその応用に関する研究
コンピュータセキュリティシンポジウム2009 優秀論文賞

2009/10　（社）情報処理学会　重回帰分析を用いたサイドチャネル攻撃の高精度化
トーキン科学技術振興財団研究奨励賞

2008/03　トーキン科学技術振興財団　２進数と非２進数を統合したVLSIシステムの高水準設計技術の開発
青葉工学振興会第13回研究奨励賞

2008/02　青葉工学振興会　2進数系と非2進数系を融合したハードウェアアルゴリズムの高水準設計技術に関する研究
Best Paper Award, the 14th Workshop on Synthesis And System Integration of Mixed Information technologies

2007/10　The 14th Workshop on Synthesis And System Integration of Mixed Information technologies　Formal representation and verification of arithmetic circuits using symbolic computer algebra
安藤博記念学術奨励賞

2006/06　財団法人安藤研究所　二進数系と非二進数系を統合したハードウェアアルゴリズムの高水準設計技術に関する研究
第７回LSI IPデザイン・アワード完成表彰部門 IP賞

2005/05　LSI IPデザイン・アワード運営委員会　算術アルゴリズム記述言語に基づく乗算器モジュールジェネレータ
電子情報通信学会東北支部学生員奨励賞

1997/03　電子情報通信学会

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Papers 252

Perceived Information Revisited II Information-Theoretical Analysis of Deep-Learning Based Side-Channel Attacks. Peer-reviewed

Akira Ito 0002, Rei Ueno, Naofumi Homma

IACR Trans. Cryptogr. Hardw. Embed. Syst.　2025　(1)　450-474　2025

DOI： 10.46586/tches.v2025.i1.450-474 　
Crystalor: Recoverable Memory Encryption Mechanism with Optimized Metadata Structure Peer-reviewed

Rei Ueno, Hiromichi Haneda, Naofumi Homma, Akiko Inoue, Kazuhiko Minematsu

Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security　228-242　2024/12/02
Publisher: ACM
DOI： 10.1145/3658644.3670273 　
Experimental Evaluation for Detecting Aging Effect on Microcontrollers based on Side-Channel Analysis Peer-reviewed

Yuki Kaneko, Yuichi Hayashi, Naofumi Homma

2024 14th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)　1-5　2024/10/07
Publisher: IEEE
DOI： 10.1109/emccompo61192.2024.10742051 　
Side-Channel Linearization Attack on Unrolled Trivium Hardware Peer-reviewed

Soichiro Kobayashi, Rei Ueno, Yosuke Todo, Naofumi Homma

IACR Communications in Cryptology　2024/10/07
Publisher: International Association for Cryptologic Research
DOI： 10.62056/angy11zn4 　

eISSN： 3006-5496

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This paper presents a new side-channel attack (SCA) on unrolled implementations of stream ciphers, with a particular focus on Trivium. Most conventional SCAs predominantly concentrate on leakage of some first rounds prior to the sufficient diffusion of the secret key and initial vector (IV). However, recently, unrolled hardware implementation has become common and practical, which achieves higher throughput and energy efficiency compared to a round-based hardware. The applicability of conventional SCAs to such unrolled hardware is unclear because the leakage of the first rounds from unrolled hardware is hardly observed. In this paper, focusing on Trivium, we propose a novel SCA on unrolled stream cipher hardware, which can exploit leakage of rounds latter than 80, while existing SCAs exploited intermediate values earlier than 80 rounds. We first analyze the algebraic equations representing the intermediate values of these rounds and present the recursive restricted linear decomposition (RRLD) strategy. This approach uses correlation power analysis (CPA) to estimate the intermediate values of latter rounds. Furthermore, we present a chosen-IV strategy for a successful key recovery through linearization. We experimentally demonstrate that the proposed SCA achieves the key recovery of a 288-round unrolled Trivium hardware implementation using 360,000 traces. Finally, we evaluate the performance of unrolled Trivium hardware implementations to clarify the trade-off between performance and SCA (in)security. The proposed SCA requires 34.5 M traces for a key recovery of 384-round unrolled Trivium implementation and is not applicable to 576-round unrolled hardware.
Comparative Analysis and Implementation of Jump Address Masking for Preventing TEE Bypassing Fault Attacks Peer-reviewed

Shoei Nashimoto, Rei Ueno, Naofumi Homma

Proceedings of the 19th International Conference on Availability, Reliability and Security　2024/07/30
Publisher: ACM
DOI： 10.1145/3664476.3664477 　
Fallen Sanctuary: A Higher-Order and Leakage-Resilient Rekeying Scheme Peer-reviewed

Rei Ueno, Naofumi Homma, Akiko Inoue, Kazuhiko Minematsu

IACR Transactions on Cryptographic Hardware and Embedded Systems　2024　(1)　264-308　2023/12/04
Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
DOI： 10.46586/tches.v2024.i1.264-308 　

eISSN： 2569-2925

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This paper presents a provably secure, higher-order, and leakage-resilient (LR) rekeying scheme named LR Rekeying with Random oracle Repetition (LR4), along with a quantitative security evaluation methodology. Many existing LR primitives are based on a concept of leveled implementation, which still essentially require a leak-free sanctuary (i.e., differential power analysis (DPA)-resistant component(s)) for some parts. In addition, although several LR pseudorandom functions (PRFs) based on only bounded DPA-resistant components have been developed, their validity and effectiveness for rekeying usage still need to be determined. In contrast, LR4 is formally proven under a leakage model that captures the practical goal of side-channel attack (SCA) protection (e.g., masking with a practical order) and assumes no unbounded DPA-resistant sanctuary. This proof suggests that LR4 resists exponential invocations (up to the birthday bound of key size) without using any unbounded leak-free component, which is the first of its kind. Moreover, we present a quantitative SCA success rate evaluation methodology for LR4 that combines the bounded leakage models for LR cryptography and a state-of-the-art information-theoretical SCA evaluation method. We validate its soundness and effectiveness as a DPA countermeasure through a numerical evaluation; that is, the number of secure calls of a symmetric primitive increases exponentially by increasing a security parameter under practical conditions.
Side-Channel Analysis Against SecOC-Compliant AES-CMAC Peer-reviewed

Katsumi Ebina, Rei Ueno, Naofumi Homma

IEEE Transactions on Circuits and Systems II: Express Briefs　70　(10)　3772-3776　2023/10
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tcsii.2023.3288278 　

ISSN： 1549-7747

eISSN： 1558-3791
Multiple-Valued Plaintext-Checking Side-Channel Attacks on Post-Quantum KEMs Peer-reviewed

Yutaro Tanaka, Rei Ueno, Keita Xagawa, Akira Ito, Junko Takahashi, Naofumi Homma

IACR Transactions on Cryptographic Hardware and Embedded Systems　473-503　2023/06/09
Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
DOI： 10.46586/tches.v2023.i3.473-503 　

eISSN： 2569-2925

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In this paper, we present a side-channel analysis (SCA) on key encapsulation mechanisms (KEMs) based on the Fujisaki–Okamoto (FO) transformation and its variants. Many post-quantum KEMs usually perform re-encryption during key decapsulation to achieve chosen-ciphertext attack (CCA) security. The side-channel leakage of re-encryption can be exploited to mount a key-recovery plaintext-checking attack (KR-PCA), even if the chosen-plaintext attack (CCA) secure decryption constructing the KEM is securely implemented. Herein, we propose an efficient side-channel-assisted KR-PCA on post-quantum KEMs, and achieve a key recovery with significantly fewer attack traces than existing ones in TCHES 2022 and 2023. The basic concept of the proposed attack is to introduce a new KR-PCA based on a multiple-valued (MV-)PC oracle and then implement a dedicated MV-PC oracle based on a multi-classification neural network (NN). The proposed attack is applicable to the NIST PQC selected algorithm Kyber and the similar lattice-based Saber, FrodoKEM and NTRU Prime, as well as SIKE. We also present how to realize a sufficiently reliable MV-PC oracle from NN model outputs that are not 100% accurate, and analyze the tradeoff between the key recovery success rate and the number of attack traces. We assess the feasibility of the proposed attack through attack experiments on three typical symmetric primitives to instantiate a random oracle (SHAKE, SHA3, and AES software). The proposed attack reduces the number of attack traces required for a reliable key recovery by up to 87% compared to the existing attacks against Kyber and other lattice-based KEMs, under the condition of 99.9999% success rate for key recovery. The proposed attack can also reduce the number of attack traces by 85% for SIKE.
How Secure is Exponent-blinded RSA–CRT with Sliding Window Exponentiation? Peer-reviewed

Rei Ueno, Naofumi Homma

IACR Transactions on Cryptographic Hardware and Embedded Systems　2023　(2)　241-269　2023/03/06
Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
DOI： 10.46586/tches.v2023.i2.241-269 　

eISSN： 2569-2925

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This paper presents the first security evaluation of exponent-blinded RSA–CRT implementation with sliding window exponentiation against cache attacks. Our main contributions are threefold. (1) We demonstrate an improved cache attack using Flush+Reload on RSA–CRT to estimate the squaring–multiplication operational sequence. The proposed method can estimate a correct squaring–multiplication sequence from one Flush+Reload trace, while the existing Flush+Reload attacks always contain errors in the sequence estimation. This is mandatory for the subsequent steps in the proposed attack. (2) We present a new and first partial key exposure attack on exponent-blinded RSA–CRT with a random-bit leak. The proposed attack first estimates a random mask for blinding exponent using a modification of the Schindler–Wiemers continued fraction attack, and then recovers the secret key using an extension of the Heninger–Shacham branch-and-prune attack. We experimentally show that the proposed attack on RSA–CRT using a practical window size of 5 with 16-, 32-, and 64-bit masks is carried out with complexity of 225.6, 267.7, and 2161, respectively. (3) We then investigate the tradeoffs between mask bit length and implementation performance. The computational cost of exponent-blinded RSA–CRT using a sliding window with a 32- and 64-bit mask are 15% and 10% faster than that with a 128-bit mask, respectively, as we confirmed that 32- and 64-bit masks are sufficient to defeat the proposed attack. Our source code used in the experiment is publicly available.
On the Success Rate of Side-Channel Attacks on Masked Implementations Peer-reviewed

Akira Ito, Rei Ueno, Naofumi Homma

Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security　1521-1535　2022/11/07
Publisher: ACM
DOI： 10.1145/3548606.3560579 　
AES S-Box Hardware With Efficiency Improvement Based on Linear Mapping Optimization Peer-reviewed

Ayano Nakashima, Rei Ueno, Naofumi Homma

IEEE Transactions on Circuits and Systems II: Express Briefs　69　(10)　3978-3982　2022/10
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tcsii.2022.3185632 　

ISSN： 1549-7747

eISSN： 1558-3791
Homomorphic encryption for stochastic computing Peer-reviewed

Ryusuke Koseki, Akira Ito, Rei Ueno, Mehdi Tibouchi, Naofumi Homma

Journal of Cryptographic Engineering　2022/09/17
Publisher: Springer Science and Business Media LLC
DOI： 10.1007/s13389-022-00299-6 　

ISSN： 2190-8508

eISSN： 2190-8516

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Abstract Homomorphic encryption (HE) method can be used to realize arithmetic operations on encrypted data. This method, however, is limited owing to its low efficiency in performing certain functions, especially those involving several multiplications. As a solution, this paper proposes a new HE-based secure computation scheme, termed as the HE for stochastic computing (HESC); this scheme can homomorphically evaluate both the stochastic addition and multiplication operations, without any bootstrapping. This HESC scheme is constructed based on additive/multiplicative HE, which only supports homomorphic addition/multiplication, and realizes the homomorphic evaluation of stochastic multiplication. The HESC employs the features of stochastic computing (SC) for homomorphic stochastic operations, where stochastic additions and multiplications are performed using random multiplexing and bit-parallel logic operations, respectively. This paper first presents a basic HESC scheme based on additive/multiplicative HE. It then presents an efficient HESC scheme that utilizes the parallelism of lattice-based cryptography (i.e., plaintext packing and vectorized homomorphic evaluation). A new stochastic addition operation is also introduced in this study, which can be used for the HESC instantiated by lattice-based cryptography. This new stochastic addition operation significantly improves the accuracy of the HESC, albeit with the trade-off of increased ciphertext size. Accordingly, this paper also proposes a technique that can reduce the size of ciphertexts, while maintaining the accuracy of the scheme. The basic performance of the HESC implemented with various HEs is demonstrated, along with its applications in polynomial functions and an oblivious inference with a neural network. Lastly, the results thus obtained indicate that the proposed scheme is more advantageous than the conventional schemes. This paper is concluded with some implications/research directions for HESC from perspectives of cryptography and HE implementations.
One Truth Prevails: A Deep-learning Based Single-Trace Power Analysis on RSA–CRT with Windowed Exponentiation Peer-reviewed

Kotaro Saito, Akira Ito, Rei Ueno, Naofumi Homma

IACR Transactions on Cryptographic Hardware and Embedded Systems　2022　(4)　490-526　2022/08/31
Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
DOI： 10.46586/tches.v2022.i4.490-526 　

eISSN： 2569-2925

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In this paper, a deep-learning based power/EM analysis attack on the state-of-the-art RSA–CRT software implementation is proposed. Our method is applied to a side-channel-aware implementation with the Gnu Multi-Precision (MP) Library, which is a typical open-source software library. Gnu MP employs a fixed-window exponentiation, which is the fastest in a constant time, and loads the entire precomputation table once to avoid side-channel leaks from multiplicands. To conduct an accurate estimation of secret exponents, our method focuses on the process of loading the entire precomputation table, which we call a dummy load scheme. It is particularly noteworthy that the dummy load scheme is implemented as a countermeasure against a simple power/EM analysis (SPA/SEMA). This type of vulnerability from a dummy load scheme also exists in other cryptographic libraries. We also propose a partial key exposure attack suitable for the distribution of errors inthe secret exponents recovered from the windowed exponentiation. We experimentally show that the proposed method consisting of the above power/EM analysis attack, as well as a partial key exposure attack, can be used to fully recover the secret key of the RSA–CRT from the side-channel information of a single decryption or a signature process.
Perceived Information Revisited Peer-reviewed

Akira Ito, Rei Ueno, Naofumi Homma

IACR Transactions on Cryptographic Hardware and Embedded Systems　2022　(4)　228-254　2022/08/31
Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
DOI： 10.46586/tches.v2022.i4.228-254 　

eISSN： 2569-2925

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In this study, we present new analytical metrics for evaluating the performance of side-channel attacks (SCAs) by revisiting the perceived information (PI), which is defined using cross-entropy (CE). PI represents the amount of information utilized by a probability distribution that determines a distinguishing rule in SCA. Our analysis partially solves an important open problem in the performance evaluation of deep-learning based SCAs (DL-SCAs) that the relationship between neural network (NN) model evaluation metrics (such as accuracy, loss, and recall) and guessing entropy (GE)/success rate (SR) is unclear. We first theoretically show that the conventional CE/PI is non-calibrated and insufficient for evaluating the SCA performance, as it contains uncertainty in terms of SR. More precisely, we show that an infinite number of probability distributions with different CE/PI can achieve an identical SR. With the above analysis result, we present a modification of CE/PI, named effective CE/PI (ECE/EPI), to eliminate the above uncertainty. The ECE/EPI can be easily calculated for a given probability distribution and dataset, which would be suitable for DL-SCA. Using the ECE/EPI, we can accurately evaluate the SR hrough the validation loss in the training phase, and can measure the generalization of the NN model in terms of SR in the attack phase. We then analyze and discuss the proposed metrics regarding their relationship to SR, conditions of successful attacks for a distinguishing rule with a probability distribution, a statistic/asymptotic aspect, and the order of key ranks in SCA. Finally, we validate the proposed metrics through experimental attacks on masked AES implementations using DL-SCA.
Efficient Modular Polynomial Multiplier for NTT Accelerator of Crystals-Kyber Peer-reviewed

Yuma Itabashi, Rei Ueno, Naofumi Homma

2022 25th Euromicro Conference on Digital System Design (DSD)　528-533　2022/08
Publisher: IEEE
DOI： 10.1109/dsd57027.2022.00076 　
SASIMI: Evaluation Board for EM Information Leakage from Large Scale Cryptographic Circuits Peer-reviewed

Daisuke Fujimoto, Youngwoo Kim, Yuichi Hayashi, Naofumi Homma, Masanori Hashimoto, Takashi Sato, Jean-Luc Danger

2022 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)　299　(302)　2022/08/01
Publisher: IEEE
DOI： 10.1109/emcsi39492.2022.9889445 　
ELM: A Low-Latency and Scalable Memory Encryption Scheme Peer-reviewed

Akiko Inoue, Kazuhiko Minematsu, Maya Oda, Rei Ueno, Naofumi Homma

IEEE Transactions on Information Forensics and Security　17　2628-2643　2022/06
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tifs.2022.3188146 　

ISSN： 1556-6013

eISSN： 1556-6021
High-Speed Hardware Architecture for Post-Quantum Diffie–Hellman Key Exchange Based on Residue Number System Peer-reviewed

Rei Ueno, Naofumi Homma

2022 IEEE International Symposium on Circuits and Systems (ISCAS)　2107-2111　2022/05/28
Publisher: IEEE
DOI： 10.1109/iscas48785.2022.9937804 　
Fault-Injection Attacks Against NIST’s Post-Quantum Cryptography Round 3 KEM Candidates Peer-reviewed

Keita Xagawa, Akira Ito, Rei Ueno, Junko Takahashi, Naofumi Homma

Lecture Notes in Computer Science　33-61　2021/12
Publisher: Springer International Publishing
DOI： 10.1007/978-3-030-92075-3_2 　

ISSN： 0302-9743

eISSN： 1611-3349
Curse of Re-encryption: A Generic Power/EM Analysis on Post-Quantum KEMs Peer-reviewed

Rei Ueno, Keita Xagawa, Yutaro Tanaka, Akira Ito, Junko Takahashi, Naofumi Homma

IACR Transactions on Cryptographic Hardware and Embedded Systems　296-322　2021/11/19
Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
DOI： 10.46586/tches.v2022.i1.296-322 　

eISSN： 2569-2925

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This paper presents a side-channel analysis (SCA) on key encapsulation mechanism (KEM) based on the Fujisaki–Okamoto (FO) transformation and its variants. The FO transformation has been widely used in actively securing KEMs from passively secure public key encryption (PKE), as it is employed in most of NIST post-quantum cryptography (PQC) candidates for KEM. The proposed attack exploits side-channel leakage during execution of a pseudorandom function (PRF) or pseudorandom number generator (PRG) in the re-encryption of KEM decapsulation as a plaintext-checking oracle that tells whether the PKE decryption result is equivalent to the reference plaintext. The generality and practicality of the plaintext-checking oracle allow the proposed attack to attain a full-key recovery of various KEMs when an active attack on the underlying PKE is known. This paper demonstrates that the proposed attack can be applied to most NIST PQC third-round KEM candidates, namely, Kyber, Saber, FrodoKEM, NTRU, NTRU Prime, HQC, BIKE, and SIKE (for BIKE, the proposed attack achieves a partial key recovery). The applicability to Classic McEliece is unclear because there is no known active attack on this cryptosystem. This paper also presents a side-channel distinguisher design based on deep learning (DL) for mounting the proposed attack on practical implementation without the use of a profiling device. The feasibility of the proposed attack is evaluated through experimental attacks on various PRF implementations (a SHAKE software, an AES software, an AES hardware, a bit-sliced masked AES software, and a masked AES hardware based on threshold implementation). Although it is difficult to implement the oracle using the leakage from the TI-based masked hardware, the success of the proposed attack against these implementations (even except for the masked hardware), which include masked software, confirms its practicality.
Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure Peer-reviewed

Shoei Nashimoto, Daisuke Suzuki, Rei Ueno, Naofumi Homma

IACR Transactions on Cryptographic Hardware and Embedded Systems　28-68　2021/11/19
Publisher: Universitatsbibliothek der Ruhr-Universitat Bochum
DOI： 10.46586/tches.v2022.i1.28-68 　

eISSN： 2569-2925

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RISC-V is equipped with physical memory protection (PMP) to prevent malicious software from accessing protected memory regions. PMP provides a trusted execution environment (TEE) that isolates secure and insecure applications. In this study, we propose a side-channel-assisted fault-injection attack to bypass isolation based on PMP. The proposed attack scheme involves extracting successful glitch parameters for fault injection from side-channel information under crossdevice conditions. A proof-of-concept TEE compatible with PMP in RISC-V was implemented, and the feasibility and effectiveness of the proposed attack scheme was validated through experiments in TEEs. The results indicate that an attacker can bypass the isolation of the TEE and read data from the protected memory region In addition, we experimentally demonstrate that the proposed attack applies to a real-world TEE, Keystone. Furthermore, we propose a software-based countermeasure that prevents the proposed attack.
Measurement and Analysis of Electromagnetic Information Leakage From Printed Circuit Board Power Delivery Network of Cryptographic Devices Peer-reviewed

Shinpei Wada, Yuichi Hayashi, Daisuke Fujimoto, Naofumi Homma, Youngwoo Kim

IEEE Transactions on Electromagnetic Compatibility　63　(5)　1322-1332　2021/10
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/temc.2021.3062417 　

ISSN： 0018-9375

eISSN： 1558-187X
An Algebraic Approach to Verifying Galois-Field Arithmetic Circuits with Multiple-Valued Characteristics Peer-reviewed

Akira ITO, Rei UENO, Naofumi HOMMA

IEICE Transactions on Information and Systems　E104.D　(8)　1083-1091　2021/08/01
Publisher: Institute of Electronics, Information and Communications Engineers (IEICE)
DOI： 10.1587/transinf.2020lop0004 　

ISSN： 0916-8532

eISSN： 1745-1361
Imbalanced Data Problems in Deep Learning-Based Side-Channel Attacks: Analysis and Solution Peer-reviewed

Akira Ito, Kotaro Saito, Rei Ueno, Naofumi Homma

IEEE Transactions on Information Forensics and Security　16　3790-3802　2021/06
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tifs.2021.3092050 　

ISSN： 1556-6013

eISSN： 1556-6021
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware Invited Peer-reviewed

Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki

IEEE Design & Test　38　(3)　84-92　2021/06
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/mdat.2021.3063337 　

ISSN： 2168-2356

eISSN： 2168-2364
Extraction of Binarized Neural Network Architecture and Secret Parameters Using Side-Channel Information Peer-reviewed

Ville Yli-Mayry, Akira Ito, Naofumi Homma, Shivam Bhasin, Dirmanto Jap

2021 IEEE International Symposium on Circuits and Systems (ISCAS)　2021/05
Publisher: IEEE
DOI： 10.1109/iscas51556.2021.9401626 　
Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials Peer-reviewed

Akira Ito, Rei Ueno, Naofumi Homma

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems　1-1　2021
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tcad.2021.3059924 　

ISSN： 0278-0070

eISSN： 1937-4151
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE Peer-reviewed

Ville Yli-Mayry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma

IEEE Transactions on Information Forensics and Security　16　1351-1364　2021
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tifs.2020.3033441 　

ISSN： 1556-6013

eISSN： 1556-6021
Machine Learning and Hardware security: Challenges and Opportunities Invited Peer-reviewed

Francesco Regazzoni, Shivam Bhasin, Amir Ali Pour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, Vincent Beroulle, Giorgio Di Natale, Paul Franzon, David Hely, Naofumi Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, Ilia Polian, Seetal Potluri, Rei Ueno, Elena-Ioana Vatajelu, Ville Yli-Mäyry

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)　2020/11
Unified Hardware for High-Throughput AES-Based Authenticated Encryptions Peer-reviewed

Shotaro Sawataishi, Rei Ueno, Naofumi Homma

IEEE Transactions on Circuits and Systems II: Express Briefs　67　(9)　1604-1608　2020/09
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tcsii.2020.3013415 　

ISSN： 1549-7747

eISSN： 1558-3791
Rejection Sampling Schemes for Extracting Uniform Distribution from Biased PUFs Peer-reviewed

Rei Ueno, Kohei Kazumori, Naofumi Homma

IACR Transactions on Cryptographic Hardware and Embedded Systems　2020　(4)　86-128　2020/08
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression Peer-reviewed

Rei Ueno, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma

IEEE Transactions on Computers　69　(4)　534-548　2020/04/01
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
DOI： 10.1109/tc.2019.2957355 　

ISSN： 0018-9340

eISSN： 2326-3814
A Formal Approach to Verifying GF(2^m) Sequential Multipliers for Cryptographic Hardware Peer-reviewed

Kazuho Sakoda, Yasuyoshi Uemura, Naofumi Homma

12th International Workshop on Security Proofs for Embedded Systems (PROOFS)　2024/09
Design Techniques toward IC-Chip Supply Chain Security Peer-reviewed

Makoto Nagata, Naofumi Homma, Yuichi Hayashi

21st International SoC Design Conference (ISOCC 2024)　CS1-CS4　2024/08
Hardware Supply Chain Security and EM Tricks Peer-reviewed

Makoto Nagata, Naofumi Homma, Yuichi Hayashi

2023 International Symposium on Electromagnetic Compatibility – EMC Europe　1-4　2023/09/04
Publisher: IEEE
DOI： 10.1109/emceurope57790.2023.10274179 　
Efficient DFA-Resistant AES Hardware Based on Concurrent Fault Detection Scheme Peer-reviewed

Rei Ueno, Yusuke Yagyu, Naofumi Homma

2023 IEEE 53rd International Symposium on Multiple-Valued Logic (ISMVL)　196-201　2023/05
Publisher: IEEE
DOI： 10.1109/ismvl57333.2023.00045 　
A Formal Approach to Identifying Hardware Trojans in Cryptographic Hardware

Akira Ito, Rei Ueno, Naofumi Homma

2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)　2021/05
Publisher: IEEE
DOI： 10.1109/ismvl51352.2021.00034 　
Effective Formal Verification for Galois-field Arithmetic Circuits with Multiple-Valued Characteristics Peer-reviewed

Akira Ito, Rei Ueno, Naofumi Homma

IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL)　46-51　2020/11
Publisher: IEEE
DOI： 10.1109/ismvl49045.2020.00-31 　
Debiasing Method for Efficient Ternary Fuzzy Extractors and Ternary Physically Unclonable Functions Peer-reviewed

Kohei Kazumori, Rei Ueno, Naofumi Homma

IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL)　52-57　2020/11
Publisher: IEEE
DOI： 10.1109/ismvl49045.2020.00-30 　
Single-Trace Side-Channel Analysis on Polynomial-based MAC Schemes Peer-reviewed

Rei Ueno, Kazuhide Fukushima, Yuto Nakano, Shinsaku Kiyomoto, Naofumi Homma

11th International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE)　2020/10
Practical Side-Channel Based Model Extraction Attack on Tree-Based Machine Learning Algorithm Peer-reviewed

Dirmanto Jap, Ville Yli-Mäyry, Akira Ito, Rei Ueno, Shivam Bhasin, Naofumi Homma

Applied Cryptography and Network Security Workshops, Lecture Notes in Computer Science　12418　93-105　2020/10
Publisher: Springer International Publishing
DOI： 10.1007/978-3-030-61638-0_6 　

ISSN： 0302-9743

eISSN： 1611-3349
PMAC++: Incremental MAC Scheme Adaptable to Lightweight Block Ciphers Peer-reviewed

Maya Oda, Rei Ueno, Akiko Inoue, Kazuhiko Minematsu, Naofumi Homma

2020 IEEE International Symposium on Circuits and Systems (ISCAS)　2020/10
Publisher: IEEE
DOI： 10.1109/iscas45731.2020.9180779 　
Efficient Electromagnetic Analysis Based on Side-channel Measurement Focusing on Physical Structures

Shinpei Wada, Youngwoo Kim, Daisuke Fujimoto, Yuichi Hayashi, Naofumi Homma

2020 IEEE International Symposium on Electromagnetic Compatibility and Signal/Power Integrity, EMCSI 2020　532-536　2020/07/01
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/EMCSI38923.2020.9191622 　
A method for constructing sliding windows leak from noisy cache timing information Peer-reviewed

Rei Ueno, Junko Takahashi, Yu-ichi Hayashi, Naofumi Homma

Journal of Cryptographic Engineering　11　(2)　161-170　2020/06/12
Publisher: Springer Science and Business Media LLC
DOI： 10.1007/s13389-020-00230-x 　

ISSN： 2190-8508

eISSN： 2190-8516
Designing Secure Cryptographic Circuits Invited Peer-reviewed

Naofumi Homma

2019 IEEE International Electron Devices Meeting (IEDM)　294-297　2019/12
Constructing Sliding Windows Leak from Noisy Cache Timing Information of OSS-RSA Peer-reviewed

Rei Ueno, Junko Takahashi, Yu-ichi Hayashi, Naofumi Homma

8th International Workshop on Security Proofs for Embedded Systems (PROOFS 2019)　1-14　2019/08
Publisher: EasyChair
DOI： 10.29007/ws8z 　
Statistical Test Methodology for Evaluating Electromagnetic Information Leakage from Mobile Touchscreen Devices Peer-reviewed

Ville Yli-Maeyry, Daisuke Miyata, Naofumi Homma, Yuichi Hayashi, Takafumi Aoki

IEEE Transactions on Electromagnetic Compatibility　61　(4)　1107-1114　2019/08
EM Information Security Threats Against RO-Based TRNGs: The Frequency Injection Attack Based on IEMI and EM Information Leakage Peer-reviewed

Saki Osuka, Daisuke Fujimoto, Yu-ichi Hayashi, Naofumi Homma, Arthur Beckers, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede

IEEE Transactions on Electromagnetic Compatibility　61　(4)　1122-1128　2019/08
Tackling Biased PUFs through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor Peer-reviewed

Rei Ueno, Manami Suzuki, Naofumi Homma

68　(7)　1091-1104　2019/07
Characterization of EM Faults on ATmega328p Peer-reviewed

Arthur Beckers, Josep Balasch, Benedikt Gierlichs, Saki Osuka, Daisuke Fujimoto, Naofumi Homma, Yuichi Hayashi, Ingrid Verbauwhede

Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sapporo" (EMC Sapporo & APEMC 2019)　820-823　2019/06
Highly Efficient GF(2^8) Inversion Circuit Based on Hybrid GF Representations Peer-reviewed

Rei Ueno, Naofumi Homma, Yasuyuki Nogami, Takafumi Aoki

Journal of Cryptographic Engineering　9　(2)　101-113　2019/06

DOI： 10.1007/s13389-018-0187-8 　
Collision-Based EM Analysis on ECDSA Hardware and a Countermeasure Peer-reviewed

Kosuke Koiwa, Rei Ueno, Daisuke Fujimoto, Yuichi Hayashi, Makoto Nagata, Makoto Ikeda, Tsutomu Matsumoto, Naofumi Homma

Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility (Joint IEEE EMC & APEMC 2019)　793-796　2019/05
High Throughput/Gate FN-Based Hardware Architectures for AES-OTR Peer-reviewed

Rei Ueno, Naofumi Homma, Tomonori Iida, Kazuhiko Minematsu

IEEE International Symposium on Circuits and Systems (ISCAS)　26-29　2019/05
A Ternary Fuzzy Extractor for Efficient Cryptographic Key Generation Peer-reviewed

Kohei Kazumori, Rei Ueno, Naofumi Homma

IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL)　49-54　2019/05
Introduction to Electromagnetic Information Security.

Yu-ichi Hayashi, Naofumi Homma

IEICE Transactions on Communications　102-B　(1)　40-50　2019

DOI： 10.1587/transcom.2018EBI0001 　
Characterizing Parallel Multipliers for Detecting Hardware Trojans Peer-reviewed

Akira Ito, Rei Ueno, Naofumi Homma, Takafumi Aoki

Journal of Applied Logics　5　(9)　1815-1831　2018/12

ISSN： 2055-3714
電磁情報セキュリティの最新動向～電磁的盗視とその対策～ Invited Peer-reviewed

本間尚文, 林優一

映像情報メディア学会誌　72　(6)　862-866　2018/10
Efficient Fuzzy Extractors Based on Ternary Debiasing Method for Biased Physically Unclonable Functions Peer-reviewed

Manami Suzuki, Rei Ueno, Naofumi Homma, Takafumi Aoki

IEEE Transactions on Circuits and Systems I: Regular Papers　66　(2)　2018/09
数論変換に基づくRing-LWE暗号ハードウェアの高効率実装に関する検討

遠藤空, 上野嶺, 青木孝文, 本間尚文

ハードウェアセキュリティ研究会　118　(272)　31-34　2018/09
楕円曲線署名ハードウェアに対するサイドチャネル攻撃とその対策

小岩航介, 上野嶺, 藤本大介, 林優一, 永田真, 池田誠, 松本勉, 本間尚文

第41回多値論理フォーラム　41　(8)　2018/09
スマートデバイスの電磁的な安全性評価に関する検討

宮田大輔, ヴィッレウリマウル, 林優一, 本間尚文

第41回多値論理フォーラム　41　(7)　2018/09
3値PUFを用いた暗号鍵生成に関する検討,” 第41回多値論理フォーラム

数森康平, 上野嶺, 本間尚文

第41回多値論理フォーラム　41　(9)　2018/09
楕円点の差分表現に基づく耐量子計算機暗号の高効率実装

船越秀隼, 本間尚文

平成 30 年度電気関係学会東北支部連合大会　(2H17)　2018/09
ガロア体演算の共有に基づく統合認証暗号ハードウェアの設計

澤田石尚太郎, 上野嶺, 本間尚文

平成 30 年度電気関係学会東北支部連合大会　(2G19)　2018/09
PUFによる軽量かつ安全なハードウェアID生成システムの設計と評価

数森康平, 上野嶺, 本間尚文

平成 30 年度電気関係学会東北支部連合大会　(2G17)　2018/09
パス遅延故障に基づくハードウェアトロイの系統的挿入法とその評価

伊東燦, 上野嶺, 本間尚文, 青木孝文

夏のセキュリティワークショップ2018　349-356　2018/07
OSS-RSAからのキャッシュリークの取得容易性評価

森隼人, 上野嶺, 高橋順子, 林優一, 本間尚文

ハードウェアセキュリティ研究会　118　(272)　35-40　2018/05
スマートデバイスの電磁的画面情報漏えいに対する統計的安全性評価手法

宮田大輔, ヴィッレウリマウル, 林優一, 本間尚文

LSIとシステムのワークショップ2018　(ポスターNo.50)　2018/05
耐量子計算機鍵共有方式の組込み機器向け実装に関する検討

船越秀隼, 本間尚文

LSIとシステムのワークショップ2018　(ポスターNo.52)　2018/05
AES-OTRハードウェアアーキテクチャとその評価

上野嶺, 本間尚文, 飯田伴則, 峯松一彦

ハードウェアセキュリティ研究会　17-22　2018/04
Highly Efficient GF(2^8) Inversion Circuit Based on Hybrid GF Representations Peer-reviewed

Rei Ueno, Naofumi Homma, Yasuyuki Nogami, Takafumi Aoki

Journal of Cryptographic Engineering　2018/03
Statistical Test Methodology for Evaluating Electromagnetic Information Leakage from Mobile Touchscreen Devices Peer-reviewed

Ville Yli-Maeyry, Daisuke Miyata, Naofumi Homma, Yuichi Hayashi, Takafumi Aoki

IEEE Transactions on Electromagnetic Compatibility　2018
A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor Peer-reviewed

Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Ville Yli-Mayry, Naofumi Homma, Yves Mathieu, Tarik Graba, Jean-Luc Danger

IEEE Symposium on VLSI Circuits, Digest of Technical Papers　C266-C267　2017/08/10
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.23919/VLSIC.2017.8008502 　
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks Peer-reviewed

Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata

JOURNAL OF CRYPTOLOGY　30　(2)　373-391　2017/04

DOI： 10.1007/s00145-015-9223-3 　

ISSN： 0933-2790

eISSN： 1432-1378
Formal Approach for Verifying Galois Field Arithmetic Circuits of Higher Degrees Peer-reviewed

Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Takafumi Aoki

IEEE TRANSACTIONS ON COMPUTERS　66　(3)　431-442　2017/03

DOI： 10.1109/TC.2016.2603979 　

ISSN： 0018-9340

eISSN： 1557-9956
Remote Visualization of Screen Images Using a Pseudo-Antenna That Blends Into the Mobile Environment Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Yohei Toriumi, Kazuhiro Takaya, Takafumi Aoki

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY　59　(1)　24-33　2017/02

DOI： 10.1109/TEMC.2016.2594237 　

ISSN： 0018-9375

eISSN： 1558-187X
Automatic Generation of Formally-Proven Temper-Resistant Galois-Field Multipliers Based on Generalized Masking Scheme Peer-reviewed

Rei Ueno, Naofumi Homma, Sumio Morioka, Takafumi Aoki

PROCEEDINGS OF THE 2017 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)　978-983　2017

DOI： 10.23919/DATE.2017.7927133 　

ISSN： 1530-1591
Efficient Electromagnetic Analysis for Cryptographic Module on the Frequency Domain

Yu-Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

ELECTRONICS AND COMMUNICATIONS IN JAPAN　99　(10)　24-32　2016/10

DOI： 10.1002/ecj.11869 　

ISSN： 1942-9533

eISSN： 1942-9541
Fundamental Study on a Mechanism of Faulty Outputs from Cryptographic Modules Due to IEMI

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

ELECTRONICS AND COMMUNICATIONS IN JAPAN　99　(9)　72-78　2016/09

DOI： 10.1002/ecj.11855 　

ISSN： 1942-9533

eISSN： 1942-9541
Buffer Overflow Attack with Multiple Fault Injection and a Proven Countermeasure Invited Peer-reviewed

Shoei Nashimoto, Naofumi Homma, Yu-Ichi Hayashi, Junko Takahashi, Hitoshi Fuji, Takafumi Aoki

Journal of Cryptographic Engineering　(1)　1-16　2016/07
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation.

Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki

IACR Cryptology ePrint Archive　2016　595-595　2016
The front line of EM information security Peer-reviewed

Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Hideaki Sone

Journal of the Institute of Electronics, Information and Communication Engineers　99　(1)　60-65　2016/01

ISSN： 0913-5693
Improved Power Analysis on Unrolled Architecture and Its Application to PRINCE Block Cipher Peer-reviewed

Ville Yli-Maeyry, Naofumi Homma, Takafumi Aoki

LIGHTWEIGHT CRYPTOGRAPHY FOR SECURITY AND PRIVACY, LIGHTSEC 2015　9542　(9542)　148-163　2016

DOI： 10.1007/978-3-319-29078-2_9 　

ISSN： 0302-9743
電磁情報セキュリティ研究最前線 Invited Peer-reviewed

林優一, 本間尚文, 青木孝文, 曽根秀昭

電子情報通信学会誌　99　(1)　60-65　2016/01/01
A Formal Verification Method of Error Correction Code Processors Over Galois-Field Arithmetic Peer-reviewed

Rei Ueno, Naofumi Homma, Takafumi Aoki

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　26　(1-2)　55-73　2016

ISSN： 1542-3980

eISSN： 1542-3999
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation Peer-reviewed

Rei Ueno, Sumio Morioka, Naofumi Homma, Takafumi Aoki

CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2016　9813　(9813)　538-558　2016

DOI： 10.1007/978-3-662-53140-2_26 　

ISSN： 0302-9743
Detection method for overclocking by intentional electromagnetic interference Peer-reviewed

Atsushi Nagao, Yuichiro Okugawa, Kazhiro Takaya, Yu-Ichi Hayashi, Naofumi Homma, Takafumi Aoki

IEEE International Symposium on Electromagnetic Compatibility　2015-　241-245　2015/09/10
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/ISEMC.2015.7256166 　

ISSN： 2158-1118 1077-4076
Method for estimating fault injection time on cryptographic devices from em leakage Peer-reviewed

Ko Nakamura, Yu Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

IEEE International Symposium on Electromagnetic Compatibility　2015-Septmber　235-240　2015/09/10

DOI： 10.1109/ISEMC.2015.7256165 　

ISSN： 1077-4076

eISSN： 2158-1118
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation Peer-reviewed

Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　23　(8)　1429-1438　2015/08

DOI： 10.1109/TVLSI.2014.2339892 　

ISSN： 1063-8210

eISSN： 1557-9999
暗号LSIへの実装攻撃に対する反応型対策の高精度化に関する検討

石幡大輔, 本間尚文, 林優一, 三浦典之, 藤本大介, 永田真, 青木孝文

電気関係学会東北支部連合大会講演論文集　2015　129-129　2015
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2015.0_129 　
ストリーム暗号ソフトウェアに対する能動的物理攻撃の評価

河井航, 本間尚文, 福島和英, 清本晋作, 青木孝文

電気関係学会東北支部連合大会講演論文集　2015　89-89　2015
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2015.0_89 　
Fundamental Study on Fault Occurrence Mechanisms by Intentional Electromagnetic Interference Using Impulses Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC)　2015　(SS13-1.4)　585-588　2015

DOI： 10.1109/APEMC.2015.7175288 　

ISSN： 2162-7673
A Formal Approach to Designing Multiple-Valued Arithmetic Circuits Peer-reviewed

Kazuya Saito, Naofumi Homma, Takafumi Aoki

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　24　(1-4)　21-34　2015

ISSN： 1542-3980

eISSN： 1542-3999
A DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor Peer-reviewed

Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata

2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC)　26-27　2015

DOI： 10.1109/ASPDAC.2015.7058929 　

ISSN： 2153-6961
Formal Design of Galois-Field Arithmetic Circuits Based on Polynomial Ring Representation Peer-reviewed

Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Takafumi Aoki

2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　48-53　2015

DOI： 10.1109/ISMVL.2015.16 　

ISSN： 0195-623X
System for Automatic Generation of Parallel Multipliers over Galois Fields Peer-reviewed

Yukihiro Sugawara, Rei Ueno, Naofumi Homma, Takafumi Aoki

2015 IEEE 45TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　54-59　2015

DOI： 10.1109/ISMVL.2015.15 　

ISSN： 0195-623X
EM Attack Sensor: Concept, Circuit, and Design-Automation Methodology Invited Peer-reviewed

Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yuichi Hayashi, Takafumi Aoki

2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)　(176)　1-6　2015

DOI： 10.1145/2744769.2747923 　

ISSN： 0738-100X
Method for Estimating Fault Injection Time on Cryptographic Devices from EM Leakage Peer-reviewed

Ko Nakamura, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

2015 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　235-240　2015

DOI： 10.1109/ISEMC.2015.7256165 　

ISSN： 2158-110X
Detection Method for Overclocking by Intentional Electromagnetic Interference Peer-reviewed

Atsushi Nagao, Yuichiro Okugawa, Kazhiro Takaya, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki

2015 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　241-245　2015

DOI： 10.1109/ISEMC.2015.7256166 　

ISSN： 2158-110X
Highly Efficient GF(2(8)) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design Peer-reviewed

Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Yasuyuki Nogami, Takafumi Aoki

CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2015　9293　(9293)　63-80　2015

DOI： 10.1007/978-3-662-48324-4_4 　

ISSN： 0302-9743

eISSN： 1611-3349
Chosen-message electromagnetic analysis against cryptographic software on embedded OS

Hajime Uno, Sho Endo, Yu-Ich Hayashi, Naofumi Homma, Takafumi Aoki

IEEE International Symposium on Electromagnetic Compatibility　2014-　314-317　2014/12/23
Publisher: Institute of Electrical and Electronics Engineers Inc.
ISSN： 2158-1118 1077-4076
Correlation power analysis using bit-level biased activity plaintexts against AES cores with countermeasures

Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger

IEEE International Symposium on Electromagnetic Compatibility　2014-　306-309　2014/12/23
Publisher: Institute of Electrical and Electronics Engineers Inc.
ISSN： 2158-1118 1077-4076
Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic Peer-reviewed

Naofumi Homma, Kazuya Saito, Takafumi Aoki

IEEE TRANSACTIONS ON COMPUTERS　63　(10)　2604-2613　2014/10

DOI： 10.1109/TC.2013.131 　

ISSN： 0018-9340

eISSN： 1557-9956
Integrated-circuit countermeasures against information leakage through em radiation Peer-reviewed

Noriyuki Miura, Daisuke Fujimoto, Yu-Ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata

IEEE International Symposium on Electromagnetic Compatibility　2014-　(September)　748-751　2014/09/15
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/ISEMC.2014.6899068 　

ISSN： 2158-1118 1077-4076
Precisely timed IEMI fault injection synchronized with em information leakage Peer-reviewed

Yu Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

IEEE International Symposium on Electromagnetic Compatibility　2014-September　(September)　738-742　2014/09/15

DOI： 10.1109/ISEMC.2014.6899066 　

ISSN： 1077-4076

eISSN： 2158-1118
Development of human resources in hardware security through practical information technology education program Peer-reviewed

Naofumi Homma, Yu Ichi Hayashi, Toshihiro Katashita, Hideaki Sone

IEEE International Symposium on Electromagnetic Compatibility　2014-September　(September)　764-767　2014/09/15

DOI： 10.1109/ISEMC.2014.6899071 　

ISSN： 1077-4076

eISSN： 2158-1118
A Multiple-Fault Injection Attack by Adaptive Timing Control Under Black-Box Conditions and a Countermeasure Peer-reviewed

Sho Endo, Naofumi Homma, Yu-ichi Hayashi, Junko Takahashi, Hitoshi Fuji, Takafumi Aoki

CONSTRUCTIVE SIDE-CHANNEL ANALYSIS AND SECURE DESIGN　8622　(8622)　214-228　2014

DOI： 10.1007/978-3-319-10175-0_15 　

ISSN： 0302-9743
Side-Channel Leakage on Silicon Substrate of CMOS Cryptographic Chip Peer-reviewed

Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger

2014 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE-ORIENTED SECURITY AND TRUST (HOST)　32-37　2014

DOI： 10.1109/HST.2014.6855564 　
A Hierarchical Formal Approach to Verifying Side-channel Resistant Cryptographic Processors Peer-reviewed

Kotaro Okamoto, Naofumi Homma, Takafumi Aoki, Sumio Morioka

2014 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE-ORIENTED SECURITY AND TRUST (HOST)　76-79　2014

DOI： 10.1109/HST.2014.6855572 　
An Efficient Approach to Verifying Galois-Field Arithmetic Circuits of Higher Degrees and Its Application to ECC Decoders Peer-reviewed

Rei Ueno, Kotaro Okamoto, Naofumi Homma, Takafumi Aoki

2014 IEEE 44TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2014)　144-149　2014

DOI： 10.1109/ISMVL.2014.33 　

ISSN： 0195-623X
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor Peer-reviewed

Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-Ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata

IEEE Symposium on VLSI Circuits, Digest of Technical Papers　172-173　2014
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/VLSIC.2014.6858423 　
Precisely Timed IEMI Fault Injection Synchronized with EM Information Leakage Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　738-742　2014

DOI： 10.1109/ISEMC.2014.6899066 　

ISSN： 2158-110X
Integrated-Circuit Countermeasures Against Information Leakage Through EM Radiation Peer-reviewed

Noriyuki Miura, Daisuke Fujimoto, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata

2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　748-751　2014

DOI： 10.1109/ISEMC.2014.6899068 　

ISSN： 2158-110X
Development of Human Resources in Hardware Security through Practical Information Technology Education Program Peer-reviewed

Naofumi Homma, Yu-ichi Hayashi, Toshihiro Katashita, Hideaki Sone

2014 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　764-767　2014

DOI： 10.1109/ISEMC.2014.6899071 　

ISSN： 2158-110X
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor Peer-reviewed

Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki

CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2014　8731　1-16　2014

ISSN： 0302-9743
A Threat for Tablet PCs in Public Space: Remote Visualization of Screen Images Using EM Emanation Peer-reviewed

Yuichi Hayashi, Naofumi Homma, Mamoru Miura, Takafumi Aoki, Hideaki Sone

CCS'14: PROCEEDINGS OF THE 21ST ACM CONFERENCE ON COMPUTER AND COMMUNICATIONS SECURITY　954-965　2014

DOI： 10.1145/2660267.2660292 　
On-chip power noise measurements of cryptographic VLSI circuits and interpretation for side-channel analysis Peer-reviewed

Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger

EMC Europe 2013　405-410　2013/09
A hierarchical graph-based approach to generating formally-proofed Galois-field multipliers Peer-reviewed

Kotaro Okamoto, Naofumi Homma, Takafumi Aoki

Proceedings of 2013 Security Proofs for Embedded Systems Workshop　98-109　2013/08
Introduction to the Special Section on Electromagnetic Information Security Peer-reviewed

Yu-Ichi Hayashi, Naofumi Homma, Takashi Watanabe, William O. Price, William A. Radasky

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY　55　(3)　539-546　2013/06

DOI： 10.1109/TEMC.2013.2255294 　

ISSN： 0018-9375
Efficient Evaluation of EM Radiation Associated With Information Leakage From Cryptographic Devices Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Haruki Shimada, Takafumi Aoki, Hideaki Sone, Laurent Sauvage, Jean-Luc Danger

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY　55　(3)　555-563　2013/06

DOI： 10.1109/TEMC.2012.2222890 　

ISSN： 0018-9375

eISSN： 1558-187X
Analysis of Electromagnetic Information Leakage From Cryptographic Devices With Different Physical Structures Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Laurent Sauvage, Jean-Luc Danger

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY　55　(3)　571-580　2013/06

DOI： 10.1109/TEMC.2012.2227486 　

ISSN： 0018-9375

eISSN： 1558-187X
Advanced Analysis of Faults Injected Through Conducted Intentional Electromagnetic Interferences Peer-reviewed

Laurent Sauvage, Jean-Luc Danger, Sylvain Guilley, Naofumi Homma, Yu-Ichi Hayashi

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY　55　(3)　589-596　2013/06

DOI： 10.1109/TEMC.2013.2254715 　

ISSN： 0018-9375
Introduction to Recent Research on EM Information Leakage Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Laurent Sauvage, Jean-Luc Danger

The 2013 Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility　233-236　2013/05
Transient IEMI Threats for Cryptographic Devices Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY　55　(1)　140-148　2013/02

DOI： 10.1109/TEMC.2012.2206393 　

ISSN： 0018-9375

eISSN： 1558-187X
Electromagnetic information leakage from cryptographic devices

Naofumi Homma, Yu-Ichi Hayashi, Takafumi Aoki

IEEE International Symposium on Electromagnetic Compatibility　401-404　2013

ISSN： 1077-4076 2158-1118
Security evaluation of cryptographic modules against profiling attacks Peer-reviewed

Yongdae Kim, Naofumi Homma, Takafumi Aoki, Heebong Choi

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)　7839　(7839)　383-394　2013

DOI： 10.1007/978-3-642-37682-5_27 　

ISSN： 0302-9743 1611-3349
Chosen-IV correlation power analysis on KCipher-2 and a countermeasure Peer-reviewed

Takafumi Hibiki, Naofumi Homma, Yuto Nakano, Kazuhide Fukushima, Shinsaku Kiyomoto, Yutaka Miyake, Takafumi Aoki

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)　7864　(7864)　169-183　2013

DOI： 10.1007/978-3-642-40026-1-11 　

ISSN： 0302-9743 1611-3349
Exploring the relations between fault sensitivity and power consumption Peer-reviewed

Yang Li, Sho Endo, Nicolas Debande, Naofumi Homma, Takafumi Aoki, Thanh-Ha Le, Jean-Luc Danger, Kazuo Ohta, Kazuo Sakiyama

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)　7864　(7864)　137-153　2013

DOI： 10.1007/978-3-642-40026-1-9 　

ISSN： 0302-9743 1611-3349
A graph-based approach to designing parallel multipliers over Galois fields based on normal basis representations Peer-reviewed

Kotaro Okamoto, Naofumi Homma, Takafumi Aoki

2013 IEEE 43RD INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2013)　158-163　2013

DOI： 10.1109/ISMVL.2013.5 　

ISSN： 0195-623X
Map-based Analysis of IEMI Fault Injection into Cryptographic Devices Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

2013 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　829-833　2013

DOI： 10.1109/ISEMC.2013.6670525 　

ISSN： 2158-110X
Effective Data Processing and Protection Techniques for Community Network Nodes Peer-reviewed

Naofumi Homma, Takafumi Aoki

Proceedings of the 15th International Symposium on Wireless Personal Multimedia Communications　571-572　2012/09
A Threat of EM Information Leakage against Cryptographic Devices Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

2012 Korea-Japan EMT/EMC/BE Joint Conference (KJJC-2012)　(2A-4)　2012/05/19
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates Peer-reviewed

Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Uenal Kocabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　20　(5)　827-840　2012/05

DOI： 10.1109/TVLSI.2011.2128353 　

ISSN： 1063-8210
A Formal Approach to Designing Cryptographic Processors Based on GF(2(m)) Arithmetic Circuits Peer-reviewed

Naofumi Homma, Kazuya Saito, Takafumi Aoki

IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY　7　(1)　3-13　2012/02

DOI： 10.1109/TIFS.2011.2157687 　

ISSN： 1556-6013

eISSN： 1556-6021
ガロア体上の算術演算回路の自動生成システムの構築

岡本広太郎, 本間尚文, 青木孝文

電気関係学会東北支部連合大会講演論文集　2012　232-232　2012
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2012.0_232 　
A fault model for conducted intentional electromagnetic interferences Peer-reviewed

Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Naofumi Homma, Yu-Ichi Hayashi

IEEE International Symposium on Electromagnetic Compatibility　788-793　2012

DOI： 10.1109/ISEMC.2012.6351664 　

ISSN： 1077-4076 2158-1118
Feasibility of fault analysis based on intentional electromagnetic interference Peer-reviewed

Junko Takahashi, Yu-Ichi Hayashi, Naofumi Homma, Hitoshi Fuji, Takafumi Aoki

IEEE International Symposium on Electromagnetic Compatibility　782-787　2012

DOI： 10.1109/ISEMC.2012.6351665 　

ISSN： 1077-4076 2158-1118
Efficient mapping of em radiation associated with information leakage for cryptographic devices Peer-reviewed

Haruki Shimada, Yu Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Laurent Sauvage, Jean Luc Danger

IEEE International Symposium on Electromagnetic Compatibility　794-799　2012

DOI： 10.1109/ISEMC.2012.6351663 　

ISSN： 1077-4076

eISSN： 2158-1118
An efficient method for estimating the area of information propagation through electromagnetic radiation Peer-reviewed

Yu Ichi Hayashi, Naofumi Homma, Taishi Ikematsu, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Jean Luc Danger

IEEE International Symposium on Electromagnetic Compatibility　800-805　2012

DOI： 10.1109/ISEMC.2012.6351662 　

ISSN： 1077-4076

eISSN： 2158-1118
A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments Peer-reviewed

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E95A　(1)　263-266　2012/01

DOI： 10.1587/transfun.E95.A.263 　

ISSN： 0916-8508

eISSN： 1745-1337
Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor Peer-reviewed

Naofumi Homma, Kazuya Saito, Takafumi Aoki

2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　110-115　2012

DOI： 10.1109/ISMVL.2012.24 　

ISSN： 0195-623X
Using selected-plaintext sets for efficient evaluation of EM information leakage from cryptographic devices Peer-reviewed

Haruki Shimada, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

2012 PROCEEDINGS OF SICE ANNUAL CONFERENCE (SICE)　2012　64-67　2012
Feasibility of Fault Analysis Based on Intentional Electromagnetic Interference Peer-reviewed

Junko Takahashi, Yu-ichi Hayashi, Naofumi Homma, Hitoshi Fuji, Takafumi Aoki

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　776-781　2012

DOI： 10.1109/ISEMC.2012.6351665 　

ISSN： 2158-110X
A Fault Model for Conducted Intentional ElectroMagnetic Interferences Peer-reviewed

Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Naofumi Homma, Yu-ichi Hayashi

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　788-793　2012

DOI： 10.1109/ISEMC.2012.6351664 　

ISSN： 2158-110X
Efficient mapping of EM radiation associated with information leakage for cryptographic devices Peer-reviewed

Haruki Shimada, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Laurent Sauvage, Jean-Luc Danger

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　(TH-PM-5-3)　794-799　2012

DOI： 10.1109/ISEMC.2012.6351663 　

ISSN： 2158-110X
An efficient method for estimating the area of information propagation through electromagnetic radiation Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Taishi Ikematsu, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Jean-Luc Danger

2012 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　(TH-PM-5-4)　800-805　2012

DOI： 10.1109/ISEMC.2012.6351662 　

ISSN： 2158-110X
An Efficient Countermeasure against Fault Sensitivity Analysis Using Configurable Delay Blocks Peer-reviewed

Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Takafumi Aoki

2012 WORKSHOP ON FAULT DIAGNOSIS AND TOLERANCE IN CRYPTOGRAPHY (FDTC)　95-102　2012

DOI： 10.1109/FDTC.2012.12 　
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers Peer-reviewed

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS　19　(7)　1136-1146　2011/07

DOI： 10.1109/TVLSI.2010.2049037 　

ISSN： 1063-8210

eISSN： 1557-9999
An On-Chip Glitchy-Clock Generator and its Application to Safe-Error Attack Peer-reviewed

Sho Endo, Naofumi Homma, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh

International Workshop on Constructive Side-Channel Analysis and Secure Design 2011　175-182　2011/02
ストリーム暗号KCipher-2のハードウェア実装評価

響崇史, 齋藤和也, 本間尚文, 青木孝文

電気関係学会東北支部連合大会講演論文集　2011　115-115　2011
Publisher: 電気関係学会東北支部連合大会実行委員会
DOI： 10.11528/tsjc.2011.0_115 　
Efficient countermeasure against fault injection attacks on modular exponentiation algorithms

Tohoku-Section Joint Convention Record of Institutes of Electrical and Information Engineers, Japan　2011　3-3　2011
Publisher: Organizing Committee of Tohoku-Section Joint Convention of Institutes of Electrical and Information Engineers, Japan
DOI： 10.11528/tsjc.2011.0_3 　
An on-chip glitchy-clock generator for testing fault injection attacks Peer-reviewed

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Journal of Cryptographic Engineering　1　(4)　265-270　2011

DOI： 10.1007/s13389-011-0022-y 　

ISSN： 2190-8508 2190-8516
Practical results of em cartography on a FPGA-based RSA hardware implementation Peer-reviewed

Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Naofumi Homma, Yu-Ichi Hayashi

IEEE International Symposium on Electromagnetic Compatibility　768-772　2011

DOI： 10.1109/ISEMC.2011.6038412 　

ISSN： 1077-4076
Identification of information leakage spots on a cryptographic device with an RSA processor Peer-reviewed

Olivier Meynard, Yu-Ichi Hayashi, Naofumi Homma, Sylvain Guilley, Jean-Luc Danger

IEEE International Symposium on Electromagnetic Compatibility　773-778　2011

DOI： 10.1109/ISEMC.2011.6038413 　

ISSN： 1077-4076
Non-invasive EMI-based fault injection attack against cryptographic modules Peer-reviewed

Yu Ichi Hayashi, Naofumi Homma, Takeshi Sugawara, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

IEEE International Symposium on Electromagnetic Compatibility　763-767　2011

DOI： 10.1109/ISEMC.2011.6038411 　

ISSN： 1077-4076
Enhancement of Simple Electro-Magnetic Attacks by Pre-characterization in Frequency Domain and Demodulation Techniques Peer-reviewed

Olivier Meynard, Denis Real, Florent Flament, Sylvain Guilley, Naofumi Homma, Jean-Luc Danger

2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE)　1004-1009　2011

ISSN： 1530-1591
A Graph-Based Approach to Designing Multiple-Valued Arithmetic Algorithms Peer-reviewed

Kazuya Saito, Naofumi Homma, Takafumi Aoki

2011 41ST IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL)　27-32　2011

DOI： 10.1109/ISMVL.2011.44 　

ISSN： 0195-623X
Non-Invasive EMI-Based Fault Injection Attack against Cryptographic Modules Peer-reviewed

Yu-ichi Hayashi, Naofumi Homma, Takeshi Sugawara, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone

2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　763-767　2011

DOI： 10.1109/ISEMC.2011.6038411 　

ISSN： 2158-110X
Practical Results of EM Cartography on a FPGA-based RSA Hardware Implementation Peer-reviewed

Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Naofumi Homma, Yu-ichi Hayashi

2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　768-772　2011

DOI： 10.1109/ISEMC.2011.6038412 　

ISSN： 2158-110X
Identification of information leakage spots on a cryptographic device with an RSA processor Peer-reviewed

Olivier Meynard, Yu-ichi Hayashi, Naofumi Homma, Sylvain Guilley, Jean-Luc Danger

2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　773-778　2011

DOI： 10.1109/ISEMC.2011.6038413 　

ISSN： 2158-110X
Suppression of information leakage from electronic devices based on SNR Peer-reviewed

Taishi Ikematsu, Yu-ichi Hayashi, Takaaki Mizuki, Naofumi Homma, Takafumi Aoki, Hideaki Sone

2011 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC)　920-924　2011

DOI： 10.1109/ISEMC.2011.6038440 　

ISSN： 2158-110X
Comparative Power Analysis of Modular Exponentiation Algorithms Peer-reviewed

Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir

IEEE TRANSACTIONS ON COMPUTERS　59　(6)　795-807　2010/06

DOI： 10.1109/TC.2009.176 　

ISSN： 0018-9340
Biasing power traces to improve correlation in power analysis attacks Peer-reviewed

Yongdae Kim, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

International Workshop on Constructive Side-Channel Analysis and Secure Design 2010　77-80　2010/02
Side Channel Attack on Cryptographic Modules and Its Security Evaluation Invited Peer-reviewed

本間尚文, 青木孝文, 佐藤証

IEICE Transactions A　J93-A　(2)　42-51　2010/02/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5707
Electromagnetic information leakage for side-channel analysis of cryptographic modules Peer-reviewed

Naofumi Homma, Takafumi Aoki, Akashi Satoh

IEEE International Symposium on Electromagnetic Compatibility　97-102　2010

DOI： 10.1109/ISEMC.2010.5711254 　

ISSN： 1077-4076
Information leakage from cryptographic hardware via common-mode current Peer-reviewed

Yu Ichi Hayashi, Takeshi Sugawara, Yoshiki Kayano, Naofumi Homma, Takaaki Mizuki, Akashi Satoh, Takafumi Aoki, Shigeki Minegishi, Hideaki Sone, Hiroshi Inoue

IEEE International Symposium on Electromagnetic Compatibility　109-114　2010

DOI： 10.1109/ISEMC.2010.5711256 　

ISSN： 1077-4076
Design of tamper-resistant registers for multiple-valued cryptographic processors Peer-reviewed

Yuichi Baba, Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki

40TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC ISMVL 2010　67-72　2010

DOI： 10.1109/ISMVL.2010.20 　

ISSN： 0195-623X
Hardware implementations of hash function Luffa Peer-reviewed

Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010　130-134　2010

DOI： 10.1109/HST.2010.5513102 　
Electromagnetic Information Leakage for Side-Channel Analysis of Cryptographic Modules Invited Peer-reviewed

Naofumi Homma, Takafumi Aoki, Akashi Satoh

2010 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC 2010)　97-102　2010

DOI： 10.1109/ISEMC.2010.5711254 　

ISSN： 2158-110X
Development of an on-chip micro shielded-loop probe to evaluate performance of magnetic film to protect a cryptographic LSI from electromagnetic analysis Invited Peer-reviewed

Masahiro Yamaguchi, Hideki Toriduka, Shoichi Kobayashi, Takeshi Sugawara, Naofumi Homma, Akashi Satoh, Takafumi Aoki

2010 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC 2010)　103-108　2010

DOI： 10.1109/ISEMC.2010.5711255 　

ISSN： 2158-110X
Information Leakage from Cryptographic Hardware via Common-Mode Current Invited Peer-reviewed

Yu-ichi Hayashi, Takeshi Sugawara, Yoshiki Kayano, Naofumi Homma, Takaaki Mizuki, Akashi Satoh, Takafumi Aoki, Shigeki Minegishi, Hideaki Sone, Hiroshi Inoue

2010 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC 2010)　109-114　2010

DOI： 10.1109/ISEMC.2010.5711256 　

ISSN： 2158-110X
Evaluation of Chosen-Message SPA Attacks against FPGA Implementations of RSA Processors Peer-reviewed

宮本篤志, 本間尚文, 青木孝文, 佐藤証

IEICE Transactions D　J92-D　(12)　2168-2180　2009/12/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 1880-4535
High Scalable Circuit Architectures of the Hash Function Whirlpool Peer-reviewed

菅原健, 本間尚文, 青木孝文, 佐藤証

IPSJ Journal　50　(11)　2618-2632　2009/11/01
Publisher:
ISSN： 1882-7837
Side Channel Attack to Magnetic Near Field of Cryptographic LSI and Its Protection by Magnetic Thin Film Peer-reviewed

Masahiro Yamaguchi, Hideki, Toriduka, Shoichi Kobayashi, Takeshi Sugawara, Naofumi Homma, Akashi Satoh, Takafumi Aoki

Soft Magnetic Materials　(19)　A3-11　2009/09
An Analysis of Information Leakage from a Cryptographic Hardware via Common-Mode Current Peer-reviewed

Yu-ichi Hayashi, Takeshi Sugawara, Yoshiki Kayano, Naofumi Homma, Takaaki Mizuki, Akashi Satoh, Takafumi Aoki, Shigeki Minegishi, Hideaki Sone, Hiroshi Inoue

Proceedings of the 2009 International Symposium on Electromagnetic Compatibility　17-20　2009/07
Spectrum Analysis on Cryptographic Modules to Counteract Side-Channel Attacks Peer-reviewed

Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh

Proceedings of the 2009 International Symposium on Electromagnetic Compatibility　21-24　2009/07
Magnetic Near Field Measurement of Cryptographic LSI using On-Chip Integrated Micro Magnetic Field Probe

TORIZUKA Hideki, YAMAGUCHI Masahiro, SUGAWARA Takeshi, HOMMA Naofumi, SATOH Akashi, AOKI Takafumi

ITE Technical Report　33　37-42　2009
Publisher: The Institute of Image Information and Television Engineers
DOI： 10.11485/itetr.33.15.0_37 　

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Increasingly a side channel attack which is to break a cryptographic key using the electromagnetic radiation and power consumption from the cryptographic module regard as a dangerous. In this paper, the magnetic near field of cryptographic LSI was measured using the on-chip integrated micro magnetic field probe with a shielded-loop coil. As a result, the high frequency current in cryptographic LSI was able to be shown as a distribution map. Moreover, when the cryptographic key was estimated by differential electromagnetic analysis, the time of the key presumption is earlier than a place away from the cryptographic IP core, and it has been found that the vulnerability of the cryptographic LSI is seen on the core. It was confirmed that the magnetic near field was able to be suppressed by putting a magnetic film on the cryptographic LSI, and it became a means to protect cryptographic LSI from side channel attack.
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool Peer-reviewed

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

INFORMATION SECURITY APPLICATIONS　5379　(5379)　28-+　2009

DOI： 10.1007/978-3-642-00306-6_3 　

ISSN： 0302-9743
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language Peer-reviewed

Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　15　(4)　329-340　2009

ISSN： 1542-3980
Multiple-Valued Constant-Power Adder for Cryptographic Processors Peer-reviewed

Yuichi Baba, Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki

ISMVL: 2009 39TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　239-244　2009

DOI： 10.1109/ISMVL.2009.9 　
Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation Peer-reviewed

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5　2918-+　2009

DOI： 10.1109/ISCAS.2009.5118413 　
Differential Power Analysis of AES ASIC Implementations with Various S-box Circuits Peer-reviewed

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2　395-+　2009

DOI： 10.1109/ECCTD.2009.5275004 　
Development of Side-Channel Attack Standard Evaluation Environment Peer-reviewed

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

2009 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1 AND 2　403-+　2009

DOI： 10.1109/ECCTD.2009.5275001 　
Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules Peer-reviewed

Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh

INFORMATION SECURITY APPLICATIONS　5932　(5932)　66-+　2009

DOI： 10.1007/978-3-642-10838-9_6 　

ISSN： 0302-9743
A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams Peer-reviewed

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

IEEE TRANSACTIONS ON COMPUTERS　57　(12)　1633-1646　2008/12

DOI： 10.1109/TC.2008.106 　

ISSN： 0018-9340

eISSN： 1557-9956
Power analysis of RSA processors with high-radix Montgomery multipliers Peer-reviewed

Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh

Proceedings of 17th International Workshop on Post-Binary ULSI Systems　21-24　2008/05/21
Arithmetic module generator with algorithm optimization capability Peer-reviewed

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proceedings - IEEE International Symposium on Circuits and Systems　1796-1799　2008

DOI： 10.1109/ISCAS.2008.4541788 　

ISSN： 0271-4310
High-performance ASIC implementations of the 128-bit block cipher CLEFIA Peer-reviewed

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings - IEEE International Symposium on Circuits and Systems　2925-2928　2008

DOI： 10.1109/ISCAS.2008.4542070 　

ISSN： 0271-4310
Enhanced power analysis attack using chosen message against RSA hardware implementations Peer-reviewed

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings - IEEE International Symposium on Circuits and Systems　3282-3285　2008

DOI： 10.1109/ISCAS.2008.4542159 　

ISSN： 0271-4310
A high-resolution phase-based waveform matching and its application to side-channel attacks Peer-reviewed

Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E91A　(1)　193-202　2008/01

DOI： 10.1093/ietfec/e9l-a.1.193 　

ISSN： 0916-8508

eISSN： 1745-1337
Arithmetic module generator with algorithm optimization capability Peer-reviewed

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10　1796-+　2008

DOI： 10.1109/ISCAS.2008.4541788 　

ISSN： 0271-4302
High-performance ASIC implementations of the 128-bit block cipher CLEFIA Peer-reviewed

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10　2925-+　2008

DOI： 10.1109/ISCAS.2008.4542070 　

ISSN： 0271-4302
Enhanced power analysis attack using chosen message against RSA hardware implementations Peer-reviewed

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10　3282-+　2008

DOI： 10.1109/ISCAS.2008.4542159 　

ISSN： 0271-4302
High-level design of multiple-valued arithmetic circuits based on arithmetic description language Peer-reviewed

Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of The International Symposium on Multiple-Valued Logic　(31)　112-117　2008

DOI： 10.1109/ISMVL.2008.39 　

ISSN： 0195-623X
Collision-based power analysis of modular exponentiation using chosen-message Pairs Peer-reviewed

Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir

CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2008, PROCEEDINGS　5154　(5154)　15-+　2008

DOI： 10.1007/978-3-540-85053-3_2 　

ISSN： 0302-9743
High-performance concurrent error detection scheme for AES hardware Peer-reviewed

Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2008, PROCEEDINGS　5154　(5154)　100-+　2008

DOI： 10.1007/978-3-540-85053-3_7 　

ISSN： 0302-9743
CHOSEN-MESSAGE SPA ATTACKS AGAINST FPGA-BASED RSA HARDWARE IMPLEMENTATIONS Peer-reviewed

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2　35-+　2008

DOI： 10.1109/FPL.2008.4629904 　

ISSN： 1946-1488
Systematic design of high-radix Montgomery multipliers for RSA processors Peer-reviewed

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

2008 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN　416-+　2008

DOI： 10.1109/ICCD.2008.4751894 　

ISSN： 1063-6404
Enhanced Correlation Power Analysis using key screening technique Peer-reviewed

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008　403-408　2008

DOI： 10.1109/ReConFig.2008.16 　
Formal representation and verification of arithmetic circuits using symbolic computer algebra Peer-reviewed

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 14th Workshop on Synthesis And System Integration of Mixed Information technologies　461-468　2007/10

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The Best Paper Award（最優秀論文賞）受賞
ASIC performance comparison for the ISO standard block ciphers Peer-reviewed

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the 2nd Joint Workshop on Information Security　485-498　2007/08
Synthesis of current mirrors based on evolutionary graph generation with transmigration capability Peer-reviewed

Masanori Natsui, Yoshiaki Tadokoro, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

IEICE ELECTRONICS EXPRESS　4　(3)　88-93　2007/02

DOI： 10.1587/elex.4.88 　

ISSN： 1349-2543
SPA against an FPGA-B ased RSA implementation with a high-radix montgomery multiplier

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings - IEEE International Symposium on Circuits and Systems　1847-1850　2007
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/iscas.2007.378274 　

ISSN： 0271-4310
DPA using phase-based waveform matching against random-delay countermeasure

Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh

Proceedings - IEEE International Symposium on Circuits and Systems　1807-1810　2007
Publisher: Institute of Electrical and Electronics Engineers Inc.
DOI： 10.1109/iscas.2007.378024 　

ISSN： 0271-4310
Algorithm-level optimization of multiple-valued arithmetic circuits using counter tree diagrams Peer-reviewed

Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Proceedings of The International Symposium on Multiple-Valued Logic　(31)　1-8　2007

DOI： 10.1109/ISMVL.2007.6 　

ISSN： 0195-623X
DPA using phase-based waveform matching against random-delay countermeasure Peer-reviewed

Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satcht

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11　1807-+　2007

ISSN： 0271-4302
SPA against an FPGA-based RSA implementation with a high-radix montgomery multiplier Peer-reviewed

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoht

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11　1847-+　2007

ISSN： 0271-4302
A high-performance ASIC implementation of the 64-bit block cipher CAST-128 Peer-reviewed

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11　1859-+　2007

ISSN： 0271-4302
Application of Symbolic Computer Algebra to Arithmetic Circuit Verification Peer-reviewed

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2　25-+　2007

DOI： 10.1109/ICCD.2007.4601876 　

ISSN： 1063-6404
Design of multiple-valued arithmetic circuits using counter tree diagrams Peer-reviewed

Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　13　(4-6)　487-502　2007

ISSN： 1542-3980

eISSN： 1542-3999
Formal design of arithmetic circuits based on arithmetic description language Peer-reviewed

Naofumi Homma, Yuki Watanabe, Takafumi Aoki, Tatsuo Higuchi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E89A　(12)　3500-3509　2006/12

DOI： 10.1093/ietfec/e89-a.12.3500 　

ISSN： 1745-1337
Systematic interpretation of redundant arithmetic adders in binary and multiple-valued logic Peer-reviewed

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

IEICE TRANSACTIONS ON ELECTRONICS　E89C　(11)　1645-1654　2006/11

DOI： 10.1093/ietele/e89-c.11.1645 　

ISSN： 1745-1353
Arithmetic module generator based on arithmetic description language Peer-reviewed

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 13th Synthesis And System Integration of Mixed Information technologies　153-160　2006/04/03
Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic Peer-reviewed

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

ISMVL 2006: 36TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC　11-+　2006

DOI： 10.1109/ISMVL.2006.10 　

ISSN： 0195-623X
High-resolution side-channel attack using phase-based waveform matching Peer-reviewed

Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh

CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2006, PROCEEDINGS　4249　(4249)　187-200　2006

ISSN： 0302-9743
Formal design of decimal arithmetic circuits using arithmetic description language Peer-reviewed

Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2　383-+　2006

DOI： 10.1109/ISPACS.2006.364918 　
A multiplier module generator based on arithmetic description language Peer-reviewed

Naofumi Homma, Yuki Watanabe, Kazuya Ishida, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the IP Based SoC Design Conference & Exhibition　207-212　2005/12
A graph-based representation for analyzing fast addition algorithms Peer-reviewed

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 7th International Symposium on Representations and Methodology of Future Computing Technologies　52-57　2005/09
Design of multiple-valued logic circuits using graph-based evolutionary synthesis Peer-reviewed

M Natsui, N Homma, T Aoki, T Higuchi

JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING　11　(5-6)　519-544　2005

ISSN： 1542-3980

eISSN： 1542-3999
Topology-Oriented Design of Current Mirrors Using Evolutionary Graph Generation System Peer-reviewed

Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 12th Synthesis And System Integration of Mixed Information technologies　78-84　2004/10
Arithmetic Description Language and Its Application to Parallel Multiplier Design Peer-reviewed

Naofumi Homma, Kazuya Ishida, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 12th Synthesis And System Integration of Mixed Information technologies　319-326　2004/10
Counter Tree Diagrams for Redundant Adder Design Peer-reviewed

Naofumi Homma, Taihei Wakamatsu, Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 2004 International Technical Conference on Circuits/Systems, Computers and Communications　6C3L-2-1-6C3L-2-4　2004/07
Evolutionary Graph Generation System with Transmigration Capability and Its Application to Current Mirror Circuit Synthesis Peer-reviewed

Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 2004 International Technical Conference on Circuits/Systems, Computers and Communications　8A2L-3-1-8A2L-3-4　2004/07
Graph-Based Approach for Synthesizing Arithmetic Circuits Invited

Naofumi Homma, Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi

Proceedings of 13th International Workshop on Post-Binary ULSI Systems　25　(32)　2004/05
Systematic Design of Redundant Adders Using Counter Tree Diagrams -- An Example of Redundant-Binary Adder Design -- Peer-reviewed

Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi

IPSJ Journal　45　(5)　1279-1288　2004/05
Publisher: Information Processing Society of Japan (IPSJ)
ISSN： 1882-7764

More details Close

This paper presents a design method of redundant adders based on a unified representation of fast addition algorithms called Counter Tree Diagrams (CTDs). An important feature of the CTD-based design is its capability to obtain possible constant-time addition algorithms in a systematic way without using specific knowledge about underlying arithmetic algorithms. We can derive high-performance redundant adders by mapping them onto physical logic devices. In this paper, we demonstrate the potential capability of CTD-based design through an experimental design of constant-time redundant-binary adders.
Design and verification of parallel multipliers using arithmetic description language: ARITH Peer-reviewed

K Ishida, N Homma, T Aoki, T Higuchi

34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS　334　(339)　334-339　2004

ISSN： 0195-623X
A systematic approach for analyzing fast addition algorithms using counter tree diagrams Peer-reviewed

N Homma, J Sakiyama, T Wakamatsu, T Aoki, T Higuchi

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5, PROCEEDINGS　V-197　(V-200)　197-200　2004
Multiplier block synthesis using evolutionary graph generation Peer-reviewed

N Homma, T Aoki, T Higuchi

2004 NASA/DOD CONFERENCE ON EVOLVABLE HARDWARE, PROCEEDINGS　79-82　2004

DOI： 10.1109/EH.2004.1310812 　
Topology-oriented design of analog circuits based on evolutionary graph generation Peer-reviewed

M Natsui, N Homma, T Aoki, T Higuchi

PARALLEL PROBLEM SOLVING FROM NATURE - PPSN VIII　3242　342-351　2004

ISSN： 0302-9743
Evolutionary Graph Generation System and Its Application MOS Current Mirror Synthesis Peer-reviewed

Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proceedings of the 2003 IEEE International Symposium on Intelligent Signal Processing and Communication Systems　747-752　2003/12
Counter tree diagrams: A unified framework for analyzing fast addition algorithms Peer-reviewed

J Sakiyama, N Homma, T Aoki, T Higuchi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E86A　(12)　3009-3019　2003/12

ISSN： 1745-1337
Evolutionary synthesis of arithmetic circuit structures Invited Peer-reviewed

T Aoki, N Homma, T Higuchi

ARTIFICIAL INTELLIGENCE REVIEW　20　(3-4)　199-232　2003/12

DOI： 10.1023/B:AIRE.0000006609.72718.dd 　

ISSN： 0269-2821

eISSN： 1573-7462
A framework of evolutionary graph generation system and its application to circuit synthesis Peer-reviewed

N Homma, T Aoki, M Motegi, T Higuchi

PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V　201-204　2003
VLSI circuit design using an object-oriented framework of evolutionary graph generation system Peer-reviewed

N Homma, M Natsui, T Aoki, T Higuchi

CEC: 2003 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1-4, PROCEEDINGS　115-122　2003

DOI： 10.1109/CEC.2003.1299564 　
Evolutionary Synthesis of Circuit Structures

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proc. of 2002 International Symposium on New Paradigm VLSI Computing　48-51　2002/12
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis Peer-reviewed

Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Parallel Problem Solving from Nature - PPSN VII, Lecture Notes in Computer Science　2439　831-840　2002/09
Evolutionary graph generation system with transmigration capability and its application to arithmetic circuit synthesis Peer-reviewed

N Homma, T Aoki, T Higuchi

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS　149　(2)　97-104　2002/04

DOI： 10.1039/ip-cds:20020261 　

ISSN： 1350-2409
Graph-based evolutionary design of arithmetic circuits Peer-reviewed

DJ Chen, T Aoki, N Homma, T Terasaki, T Higuchi

IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION　6　(1)　86-100　2002/02

DOI： 10.1109/4235.985694 　

ISSN： 1089-778X

eISSN： 1941-0026
Parallel evolutionary design of constant-coefficient multipliers Peer-reviewed

DJ Chen, T Aoki, N Homma, T Higuchi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E85A　(2)　508-512　2002/02

ISSN： 0916-8508

eISSN： 1745-1337
Graph-based individual representation for evolutionary synthesis of arithmetic circuits Peer-reviewed

N Homma, T Aoki, T Higuchi

CEC'02: PROCEEDINGS OF THE 2002 CONGRESS ON EVOLUTIONARY COMPUTATION, VOLS 1 AND 2　1　1492-1497　2002

DOI： 10.1109/CEC.2002.1004463 　
Pragmatic method for the design of fast constant-coefficient combinational multipliers Peer-reviewed

D Chen, T Aoki, N Homma, T Higuchi

IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES　148　(6)　196-206　2001/11

DOI： 10.1049/ip-cdt:20010725 　

ISSN： 1350-2387
Evolutionary graph generation system with transmigration capability for arithmetic circuit design Peer-reviewed

Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Proc. of The 2001 IEEE International Symposium on Circuits and Systems　5　(5)　171-174　2001/05
Evolutionary design for high-speed constant-coefficient multipliers Peer-reviewed

D Chen, T Aoki, N Homma, T Higuchi

ELECTRONICS LETTERS　37　(4)　256-258　2001/02

DOI： 10.1049/el:20010177 　

ISSN： 0013-5194
Distributed evolutionary design of constant-coefficient multipliers Peer-reviewed

D Chen, T Aoki, N Homma, T Higuchi

ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS　1　249-252　2001
Design of constant-coefficient multipliers Peer-reviewed

DJ Chen, T Aoki, N Homma, T Higuchi

2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS　1　416-419　2001
Evolutionary synthesis of fast constant-coefficient multipliers Peer-reviewed

N Homma, T Aoki, T Higuchi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E83A　(9)　1767-1777　2000/09

ISSN： 0916-8508

eISSN： 1745-1337
Evolutionary graph generation system with symbolic verification for arithmetic circuit design Peer-reviewed

N Homma, T Aoki, T Higuchi

ELECTRONICS LETTERS　36　(11)　937-939　2000/05

DOI： 10.1049/el:20000704 　

ISSN： 0013-5194
Evolutionary Generation of Constant-Coefficient Multipliers Peer-reviewed

N. Homma, T. Aoki, T. Higuchi

Proc. of 1999 IEEE Int. Symp. on Intelligent Signal Processing and Communication Systems　481-484　1999/12
A New Evolutionary Approach for Synthesizing Circuit Structures Peer-reviewed

N. Homma, T. Aoki, T. Higuchi

Proc. of 1999 Int. Symp. on Nonlinear Theory and its Applications　1　239-242　1999/11
Evolutionary design of arithmetic circuits Peer-reviewed

T Aoki, N Homma, T Higuchi

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES　E82A　(5)　798-806　1999/05

ISSN： 0916-8508

eISSN： 1745-1337
Evolutionary Graph Generation System for Arithmetic Circuit Design Peer-reviewed

N. Homma, T. Aoki, T. Higuchi

International Symposium on Future of Intellectual Integrated Electronics　355-364　1999/03
Design of Arithmetic Circuits Based on Evolutionary Graph Generation Peer-reviewed

N. Homma, T. Aoki, T. Higuchi

Proc. of the Workshop on Synthesis and Systems Integration of Mixed Technologies　31-38　1998/10

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電子情報通信学会総合大会　2025/03
Toom-Cook型多項式乗算に基づく高効率なQR-UOV署名ソフトウェア実装

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2025年暗号と情報セキュリティシンポジウム（SCIS2025)　3A1-2-1-3A1-2-6　2025/01
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2025年暗号と情報セキュリティシンポジウム（SCIS2025)　2E3-4-1-2E3-4-6　2025/01
格子ベース鍵カプセル化メカニズムに対する故障選択平文攻撃

上野嶺, Tasso Élise, 草川恵太, 本間尚文

2025年暗号と情報セキュリティシンポジウム（SCIS2025)　1A1-5-1-1A1-5-6　2025/01
サイドチャネル解析に基づく経年劣化デバイスの検出手法とその評価

金子雄輝, 本間尚文

2024ハードウェアセキュリティフォーラム　2024/12
A Non-Invasive Method for Detecting Aging of Microcontrollers Based on Side-Channel Analysis Peer-reviewed

Yuki Kaneko, Naofumi Homma

IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST)　2024/12
多標数ガロア体算術演算順序回路の形式的検証手法の検討

迫田一歩, 植村泰佳, 本間尚文

第47回多値論理フォーラム　2024/09
ストリーム暗号MUGIに対するSCA手法の提案

小熊頌太郎, 櫻井秀人, 小熊博, 本間尚文

電子情報通信学会ソサイエティ大会　2024/09
CRYSTALS-Kyber（FIPS203）のマイコンへの実装

松下礼, 小熊博, 本間尚文

電子情報通信学会ソサイエティ大会　2024/09
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金子雄輝, 本間尚文

電気関係学会東北支部連合大会　2I01　2024/08
完全準同型暗号に基づく確率的暗号化状態処理手法の検討

佐藤颯, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　124　(123)　278-283　2024/07
サイドチャネル情報を用いたマイクロコントローラの経年劣化判別手法の基礎検討

金子雄輝, 林優一, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　124　(123)　272-277　2024/07
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永田真, 門田和樹, 林優一, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　124　(392)　30-33　2024/04
GF(2m)上の算術演算順序回路の計算機代数に基づく形式検証に関する検討

迫田一歩, 植村泰佳, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　123　(391)　HWS2023-100-215-HWS2023-100-220　2024/03
耐量子計算機署名QR-UOVハードウェアに関する検討

天笠博, 上野嶺, 山越公洋, 金城皓羽, 秋山梨佳, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　123　(391)　HWS2023-93-178-HWS2023-93-183　2024/03
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上野嶺, 本間尚文, 井上明子, 峯松一彦

第37回多値論理とその応用研究会　MVL-9　(1)　58-64　2024/01
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天笠博, 上野嶺, 本間尚文

2024年暗号と情報セキュリティシンポジウム（SCIS2024)　(1A2-6)　2024/01
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上野嶺, 本間尚文, 井上明子, 峯松一彦

2024年暗号と情報セキュリティシンポジウム (SCIS2024)　(2G2-1)　2024/01
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東哲平, 上野嶺, 本間尚文

電子情報通信学会情報セキュリティ研究会　123　(245)　ISEC2023-69-98-ISEC2023-69-102　2023/11
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岩佐大将, 上野嶺, 福島和英, 本間尚文

電子情報通信学会情報セキュリティ研究会　123　(245)　ISEC2023-68-93-ISEC2023-68-97　2023/11
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田中陸真, 上野嶺, 伊東燦, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　123　(132)　HWS2023-16-13-HWS2023-16-18　2023/07
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小林蒼一朗, 上野嶺, 藤堂洋介, 本間尚文

電子情報通信学会情報セキュリティ研究会　123　(129)　ISEC2023-44-194-ISEC2023-44-201　2023/07
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羽田大倫, 上野嶺, 本間尚文, 井上明子, 峯松一彦

情報処理学会システム・アーキテクチャ研究発表会　2022-ARC-250　(15)　1-9　2023/03
部分鍵差分推測を用いたノンプロファイリング型深層学習サイドチャネル攻撃に関する検討

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2023年暗号と情報セキュリティシンポジウム(SCIS2023)　(3E1-2)　1-6　2023/01
TEEバイパス攻撃対策のRISC-V Keystone実装評価

梨本翔永, 上野嶺, 本間尚文

2023年暗号と情報セキュリティシンポジウム(SCIS2023)　(2E1-4)　1-6　2023/01
確率的暗号化状態処理ハードウェアの設計と評価

田村佑樹, 上野嶺, 本間尚文

多値論理とその応用研究会　MVL-23　(1)　60-69　2023/01
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田中裕太郎, 上野嶺, 草川恵太, 伊東燦, 高橋順子, 本間尚文

多値論理とその応用研究会　MVL-23　(1)　52-59　2023/01
耐ソフトエラー性浮動小数点数値表現の提案とその実機評価

森岡澄夫, 森琢磨, 天笠博, 上野嶺, 本間尚文

第66回宇宙科学技術連合講演会　(1N03)　2022/11
確率的秘匿演算ハードウェアの設計とプロトタイプ評価

田村佑樹, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　122　(227)　HWS2022-38-46-HWS2022-38-51　2022/10
AES-CTRに対するプロファイリングサイドチャネル解析の検討

蝦名克海, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　122　(227)　HWS2022-31-6-HWS2022-31-11　2022/10
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羽田大倫, 上野嶺, 本間尚文, 井上明子, 峯松一彦

情報処理学会システム・アーキテクチャ研究発表会　2022-ARC-250　(15)　1-9　2022/10
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田中裕太郎, 上野嶺, 草川恵太, 伊東燦, 高橋順子, 本間尚文

122　(125)　HWS2022-7-1-HWS2022-7-6　2022/07
Gem5を用いたメモリ暗号化認証スキームELMのシステムレベル性能評価

羽田大倫, 上野嶺, 本間尚文, 井上明子, 峯松一彦

LSIとシステムのワークショップ　2022/05
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伊東燦, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　122　(11)　HWS2022-1-HWS2022-6　2022/04
RISC-V Keystoneへの故障注入に基づく隔離実行バイパス攻撃

梨本翔永, 鈴木大輔, 上野嶺, 本間尚文

121　(413)　141-146　2022/03
アンロールド実装されたAESハードウェア特有のサイドチャネル情報漏洩の評価

中嶋彩乃, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　121　(413)　135-140　2022/03
確率的準同型暗号の高効率化とその性能評価

小関隆介, 上野嶺, 伊東燦, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　121　(413)　37-42　2022/03
マスキング対策実装に対するサイドチャネル攻撃成功確率の情報理論的解析

伊東燦, 上野嶺, 本間尚文

2022年暗号と情報セキュリティシンポジウム(SCIS2022)　4C1-3　1-8　2022/01
NIST PQC Round3候補の鍵カプセル化方式への故障注入攻撃

草川恵太, 伊東燦, 上野嶺, 高橋順子, 本間尚文

2022年暗号と情報セキュリティシンポジウム(SCIS2022)　2A2-1　1-8　2022/01
耐量子鍵カプセル化メカニズムに対する一般化サイドチャネル攻撃

上野嶺, 草川恵太, 田中裕太郎, 伊東燦, 高橋順子, 本間尚文

2022年暗号と情報セキュリティシンポジウム(SCIS2022)　1C1-1　1-8　2022/01
アンロールドアーキテクチャに基づく AESハードウェア特有のサイドチャネル情報漏洩の評価

中嶋彩乃, 上野嶺, 本間尚文

ハードウェアセキュリティフォーラム2021　P9　2021/12
軽量暗号GIMLI-AEADに対する深層学習を用いたサイドチャネル解析の検討

伊藤圭吾, 伊東燦, 上野嶺, 福島和英, 清本晋作, 本間尚文

電子情報通信学会情報セキュリティ研究会　121　(239)　20-25　2021/11
耐タンパー性を有するCRT-RSAソフトウェアに対する深層学習に基づく単一波形サイドチャネル攻撃

齋藤宏太郎, 伊東燦, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　121　(42)　7-12　2021/10
格子暗号向けKリダクションに基づく数論変換ハードウェアの検討

板橋由磨, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　121　(46)　26-31　2021/10
格子暗号向け数論変換ハードウェアの設計

板橋由磨, 上野嶺, 本間尚文

第44回多値論理フォーラム　3-1-3-8　2021/09
軽量暗号GIMLIに対するサイドチャネル解析の検討

伊藤圭吾, 上野嶺, 福島和英, 清本晋作, 本間尚文

回路とシステムワークショップ　290-291　2021/08
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小嶋健太, 伊東燦, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　121　(23)　80-85　2021/07
並列化Quotient Pipeliningモンゴメリ乗算に基づくFp2乗算器データパスの設計とその同種写像暗号への応用に関する検討

上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　121　(12)　14-19　2021/07
ガロア体に基づく暗号ハードウェアの形式的トロイ検知手法

伊東燦, 上野嶺, 本間尚文

LSIとシステムのワークショップ2021　18　2021/05
［招待講演］バイアスを有するPUFからの棄却サンプリングを用いた一様乱数の抽出法（CHES2020より） Invited

上野嶺, 数森康平, 本間尚文

ハードウェアセキュリティ研究会, 信学技報　121　(1, HWS2021-5)　25-25　2021/04
剰余数系を用いた同種写像暗号の高速ハードウェア実装

上野嶺, 本間尚文

ハードウェアセキュリティ研究会, 信学技報　121　(1, HWS2021-1)　1-6　2021/04
深層学習を用いたサイドチャネル攻撃の性能評価手法に関する検討

伊東燦, 上野嶺, 本間尚文

ハードウェアセキュリティ研究会, 信学技報　121　(1, HWS2021-8)　33-38　2021/04
Tweakableブロック暗号を用いた低遅延メモリ保護方式とそのハードウェア設計

小田麻矢, 上野嶺, 本間尚文, 井上明子, 峯松一彦

ハードウェアセキュリティ研究会, 信学技報　120　(401)　85-90　2021/03
線形写像の最適化による高効率AES S-Boxハードウェアの設計と評価

中嶋彩乃, 上野嶺, 本間尚文

ハードウェアセキュリティ研究会, 信学技報　120　(401)　91-96　2021/03
物理複製困難関数を用いたハードウェア認証技術

上野嶺, 本間尚文

月刊自動認識, Vol. 34, No. 2, pp. 36–43, 日本工業出版　34　(2)　36-43　2021/02
メモリ保護方式ELMのハードウェア設計とその評価

小田麻矢, 上野嶺, 本間尚文, 井上明子, 峯松一彦

2021年暗号と情報セキュリティシンポジウム (SCIS 2021), No. 4D1-2　2021/01
低遅延かつスケーラブルなメモリ保護方式ELMの提案

井上明子, 峯松一彦, 小田麻矢, 上野嶺, 本間尚文

2021年暗号と情報セキュリティシンポジウム (SCIS2021), No. 4D1-1　2021/01
深層学習を用いたサイドチャネル攻撃における不均衡データ問題の解析と解消法

伊東燦, 齋藤宏太郎, 上野嶺, 本間尚文

2021年暗号と情報セキュリティシンポジウム (SCIS 2021), No. 1D1-4　2021/01
非許容エラーの発生確率を抑える耐ソフトエラー数値表現の検討

藤井大輝, 上野嶺, 本間尚文, 森岡澄夫

第６４回宇宙科学技術連合講演会　(2L17)　2020/10
即時に故障検出可能な高効率AESハードウェアの検討

柳生佑介, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　120　(211)　36-41　2020/10
ハードウェアのネットリストに対するハードウェアトロイ検知手法

伊東燦, 上野嶺, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　120　(211)　77-82　2020/10
車載通信向けメッセージ認証コードに対するサイドチャネル解析

永戸謙成, ヴィッレウリマウル, 上野嶺, 遠山毅, 小熊寿, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　120　(115)　87-92　2020/07
ストカスティック演算を用いた確率的準同型暗号の構成に関する検討

小関隆介, 上野嶺, 本間尚文

電子情報通信学会情報セキュリティ研究会　120　(112)　61-67　2020/07
指数ブラインディングされたSliding Window法を用いたCRT-RSAに対するサイドチャネル攻撃に関する検討

大澤創紀, 上野嶺, 本間尚文

電子情報通信学会情報セキュリティ研究会　120　(112)　39-45　2020/07
FPGA向け二値化ニューラルネットワークへの電磁波解析攻撃の検討

Ville Yli-Mäyry, 伊東燦, 上野嶺, Shivam Bhasin, Dirmanto Jap, 本間尚文

電子情報通信学会ハードウェアセキュリティ研究会　120　(1)　25-28　2020/04
RISC-Vのプロセス分離への故障注入を用いたバイパス攻撃の検討

梨本翔永, 鈴木大輔, 上野嶺, 本間尚文

2020年暗号と情報セキュリティシンポジウム (SCIS 2020)　(3E4-2)　2020/01
PUFからの棄却サンプリングを用いた効率的な暗号鍵生成

数森康平, 上野嶺, 本間尚文

2020年暗号と情報セキュリティシンポジウム (SCIS 2020)　(3E1-5)　2020/01
暗号ハードウェアに対する形式的ハードウェアトロイ検出手法

伊東燦, 上野嶺, 本間尚文

2020年暗号と情報セキュリティシンポジウム (SCIS 2020)　(2E3-1)　2020/01
BBB安全なインクリメンタルMACスキームとそのハードウェア実装

小田麻矢, 上野嶺, 井上明子, 峯松一彦, 本間尚文

2020年暗号と情報セキュリティシンポジウム (SCIS 2020)　(2B3-5)　2020/01
ストカスティック計算に基づく確率的準同型暗号の構成に関する検討

上野嶺, 本間尚文

2020年暗号と情報セキュリティシンポジウム (SCIS 2020)　(1B1-1)　2020/01
多標数ガロア体算術演算回路の形式的検証手法

伊東燦, 上野嶺, 本間尚文

第33回多値論理とその応用研究会　(17)　107-112　2020/01
確率的計算手法を用いた秘密計算に関する検討

上野嶺, 本間尚文

第33回多値論理とその応用研究会　(9)　53-58　2020/01
剰余数系を用いた同種写像暗号ハードウェアアーキテクチャの設計に関する検討

船越秀隼, 上野嶺, 本間尚文

ハードウェアセキュリティ研究会　119　(260)　19-24　2019/11
ペアリング暗号ハードウェアの相関電磁波解析に関する検討

門脇悠真, 上野嶺, ヴィッレ・ウリマウル, 藤本大介, 林優一, 永田真, 池田誠, 松本勉, 本間尚文

ハードウェアセキュリティ研究会　119　(260)　13-18　2019/11
3値PUFに対する効率的なエントロピー抽出手法とその評価

数森康平, 上野嶺, 本間尚文

第42回多値論理フォーラム　42　(9)　2019/09
ブール多項式のZDD表現を用いたガロア体算術演算回路の形式的検証手法

伊東燦, 上野嶺, 本間尚文

第42回多値論理フォーラム　42　(8)　2019/09
メモリ完全性検証のための軽量かつ高速なMACハードウェアの設計

小田麻矢, 上野嶺, 井上明子, 峯松一彦, 本間尚文

2019年度電気関係学会東北支部連合大会　(1A01)　2019/08
自動車向けセキュリティ評価プラットフォームを考慮した漏洩電磁波によるサイドチャネル解析

永戸謙成, ヴィッレ・ウリマウル, 遠山毅, 吉田琢也, 小熊寿, 本間尚文

2019年度電気関係学会東北支部連合大会　(2J06)　2019/08
暗号ソフトウェアの高精度なキャッシュタイミング解析とその評価

大澤創紀, 上野嶺, 本間尚文

2019年度電気関係学会東北支部連合大会　(1G14)　2019/08
乗法的オフセットに基づく高効率AESハードウェアアーキテクチャの設計

上野嶺, 森岡澄夫, 三浦典之, 松田航平, 永田真, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, 本間尚文

セキュリティーサマーサミット2019　(B-5)　2019/07
ガロア体算術に基づく暗号ハードウェアの形式的トロイフリー検証

伊東燦, 上野嶺, 本間尚文

セキュリティサマーサミット2019　(B-2)　2019/07
ガロア体演算に基づく暗号ハードウェアにおけるHT検知技術

伊東燦, 上野嶺, 本間尚文, 青木孝文

LSIとシステムのワークショップ2019　(ポスターNo. 9)　2019/05
ガロア体演算に基づく認証暗号の統合ハードウェアの設計

澤田石尚太郎, 上野嶺, 本間尚文

ハードウェアセキュリティ研究会　119　(2)　13-18　2019/04
TRNG on-the-fly テストを実装したリングオシレータベースの乱数生成器への周波数注入攻撃

大須賀彩希, 藤本大介, 本間尚文, Arthur Beckers, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede, 林優一

2019年暗号と情報セキュリティシンポジウム (SCIS 2019)　(2D4-3)　2019/01
情報理論的安全性を有する鍵長可変MACハードウェアアーキテクチャの設計

上野嶺, 森岡澄夫, 本間尚文

2019年暗号と情報セキュリティシンポジウム (SCIS 2019)　(1D1-3)　2019/01
ガロア体ハードウェアアルゴリズムの形式的トロイフリー性検証手法

伊東燦, 上野嶺, 本間尚文, 青木孝文

2019年暗号と情報セキュリティシンポジウム (SCIS 2019)　(2D1-4)　2019/01
低遅延暗号における中間ラウンドからのサイドチャネル漏えいとそのRSMに基づく効率的な対策

Ville Yli-Mäyry, 上野嶺, 本間尚文, 青木孝文, 三浦典之, 松田航平, 永田真, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

2019年暗号と情報セキュリティシンポジウム (SCIS 2019)　(3D3-1)　2019/01
Poly1305への単一波形を用いたサイドチャネル攻撃とその実現可能性の評価

上野嶺, 福島和英, 仲野有登, 清本晋作, 本間尚文

2019年暗号と情報セキュリティシンポジウム (SCIS 2019)　(2D3-3)　2019/01
偏位マスキングの多値化PUFへの拡張とその暗号鍵生成への応用

上野嶺, 本間尚文

第32回多値論理とその応用研究会　(7)　49-57　2019/01
Q-RNS MR アルゴリズムのFPGA実装時における最適な基底選択と評価

郡義弘, 藤本大介, 林優一, 本間尚文

信学技報　118　(272)　25-30　2018/10
ガウス雑音を用いた暗号機器への意図的な電磁妨害に対する耐性評価手法

岡本拓実, 藤本大介, 林優一, 本間尚文, アーサーベッカーズ, ジョゼフバラスチ, ベネディクトゲーリッヒ, イングリッドヴェルバウヘーデ

信学技報　118　(153)　77-81　2018/07
サイドチャネル情報を用いた乱数生成器への非侵襲な周波数注入攻撃

大須賀彩希, 藤本大介, 林優一, 本間尚文, Arthur Beckers, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede

暗号と情報セキュリティシンポジウム　1D2-4　2018/01
A study on possibility of screen reconstruction by frequency analysis of electromagnetic emanation from mobile devices

115　(509)　5-9　2016/03/11
Publisher: 電子情報通信学会
ISSN： 0913-5685
A-7-12 A Multiple Fault Injection Attack against Software on Cortex-M0+ Processors and a Countermeasure

Nashimoto Shoei, Homma Naofumi, Hayashi Yu-ichi, Takahashi Junko, Fuji Hitoshi, Aoki Takafumi

Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference　2016　98-98　2016/03/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 2189-700X
B-4-60 A study on relationship between reconstructed screen images an AM-demodulated frequency characteristics of electromagnetic radiation from mobile devices

Itami Go, Toriumi Yohei, Goto Shinji, Takaya Kazuhiro, Hayashi Yu-ichi, Homma Naofumi, Aoki Takafumi

Proceedings of the IEICE General Conference　2016　(1)　380-380　2016/03/01
Publisher: The Institute of Electronics, Information and Communication Engineers
電磁波攻撃センサの設計と実証

本間尚文, 林優一, 三浦典之, 藤本大介, 永田真, 青木孝文

暗号と情報セキュリティシンポジウム　2F4-4　2016/01
電磁情報セキュリティ研究最前線

林優一, 本間尚文, 青木孝文, 曽根秀昭

電子情報通信学会学会誌　99　(1)　60-65　2016/01
Publisher: 電子情報通信学会
Tutorial : Side-channel Attack on Cryptographic Embedded Systems and Its Countermeasure

115　(208)　19-24　2015/09/03
Publisher: 電子情報通信学会
ISSN： 0913-5685
サイドチャネル近傍電磁波解析攻撃センサの提案とセキュリティ耐性評価

田中廉大, 三浦典之, 藤本大介, 本間尚文, 林優一, 青木孝文, 永田真

電子情報通信学会ソサイエティ大会　C-12-5　2015/09
Hardware Security for Mobile Devices in Public Spaces (情報通信システムセキュリティ)

林優一, 本間尚文, 青木孝文

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報　115　(81)　69-74　2015/06/11
Publisher: 電子情報通信学会
ISSN： 0913-5685
Hardware Security for Mobile Devices in Public Spaces (インターネットアーキテクチャ)

林優一, 本間尚文, 青木孝文

電子情報通信学会技術研究報告 = IEICE technical report : 信学技報　115　(80)　69-74　2015/06/11
Publisher: 電子情報通信学会
ISSN： 0913-5685
A Multiple-fault Injection Attack Against Cryptographic Software on Cortex-M0 Processor

IPSJ SIG Notes　2015　(15)　1-8　2015/02/26
Publisher: Information Processing Society of Japan (IPSJ)

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This paper presents a multiple-fault injection attack against the cryptographic software running on Cortex-M0 processor core. Multiple-fault injection attacks have been a problem on software running on embedded microcontroller equipped with countermeasures based on recalculation. The attacks can circumvent the countermeasure through an adaptive fault injection even when cryptographic program is unknown to the attackers. However, the possibility of the attack described above is unknown on the microcontrollers which have instructions with different execution cycles because the attackers cannot identify the execution timing of branch instruction. This paper shows a scanning method against the cryptographic software, which can be applied to the microcontroller described above. Validity of proposed attack is demonstrated through the experiment using AES program running on the Cortex-M0 core, which have been widely used for cryptographic modules.
Study on Detection Method for Clock Error due to Intentional Electromagnetic Interference

Nagao Atsushi, Okugawa Yuichiro, Takaya Kazuhiro, Hayashi Yu-ichi, Homma Naofumi, Aoki Takafumi

IEICE technical report. Electromagnetic compatibility　114　(398)　83-88　2015/01/22
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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Overclocking, which occurs because of the disruption of the clock frequency, causes LSI modules to malfunction. The Electromagnetic interference can also cause an LSI module to malfunction owing to overclocking. On the other hand, the clarification of malfunction factors is required to increase the immunity of LSI modules. With that, this paper proposes a method for detecting overclocking when electromagnetic interference is applied; the presence of overclocking is determined based on the output results from an evaluation circuit, which is installed in an LSI module. Further, experiments were conducted for a case in which glitches were introduced into the clock signal and another case where a continuous wave was applied, to examine the validity of the proposed method. As a result, we confirm that the evaluation circuit can correctly determine if overclocking is occurred or not. In addition, we confirm the outputs of the evaluation circuit that indicated the occurrence of overclocking when a continuous wave was injected. And, the change of the clock cycle was confirmed by fluctuation in voltage which is occurred by overlapping CW from observation of clock signal. Therefore, the evaluation circuit proposed in this paper was confirmed to be useful in detecting the overclocking.
Effect of Precisely Timed Intentional Electromagnetic Interference on Internal Operation in Cryptographic Device

KOBAYASHI Mizuki, HAYASHI Yu-ichi, HOMMA Naofumi, MIZUKI Takaaki, AOKI Takafumi, SONE Hideaki

IEICE technical report. Electromagnetic compatibility　114　(266)　11-15　2014/10/23
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a new intentional electromagnetic interference (IEMI) fault-injection method that can inject transient faults timely at a distance from cryptographic operations. Such IEMI fault injection could pose severe threats to many cryptographic devices assumed that attackers cannot access them directly since it can be used for performing fault analysis. The proposed IEMI fault-injection method injects a block (i.e., period) of continuous sinusoidal waves via cables attached to cryptographic devices instead of immediate electromagnetic pulse used in the conventional methods. The injected EM waves have a temporary impact in the cryptographic module, but not in other components on the device. Another important feature of the proposed method is to employ EM information leaked from the cryptographic operations for the trigger signal of the fault injection. In this paper, we demonstrate that the proposed method can inject faults timely into the final round of an AES hardware through an experiment.
Effect of Precisely Timed Intentional Electromagnetic Interference on Internal Operation in Cryptographic Device

KOBAYASHI Mizuki, HAYASHI Yu-ichi, HOMMA Naofumi, MIZUKI Takaaki, AOKI Takafumi, SONE Hideaki

114　(268)　11-15　2014/10/23
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a new intentional electromagnetic interference (IEMI) fault-injection method that can inject transient faults timely at a distance from cryptographic operations. Such IEMI fault injection could pose severe threats to many cryptographic devices assumed that attackers cannot access them directly since it can be used for performing fault analysis. The proposed IEMI fault-injection method injects a block (i.e., period) of continuous sinusoidal waves via cables attached to cryptographic devices instead of immediate electromagnetic pulse used in the conventional methods. The injected EM waves have a temporary impact in the cryptographic module, but not in other components on the device. Another important feature of the proposed method is to employ EM information leaked from the cryptographic operations for the trigger signal of the fault injection. In this paper, we demonstrate that the proposed method can inject faults timely into the final round of an AES hardware through an experiment.
Implementation and Evaluation of KCipher-2 Software for Smart Cards

2014　(2)　64-71　2014/10/15
Reduction Effect of Information Leakage from a Cryptographic LSI by a Magnetic Thin Film

OTOMO Makiko, ARAI Kaoru, ITO Tetsuo, ENDO Yasushi, YAMAGUCHI Masahiro, HAYASHI Yuichi, SONE Hideaki, HOMMA Naofumi, AOKI Takafumi

IEICE technical report. Electromagnetic compatibility　113　(494)　11-16　2014/03/14
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper describes the differential electromagnetic analysis (DEMA) on a cryptographic LSI and the reduction effect of information leakage by a magnetic thin film. The correlation coefficients at two points near the cryptographic IP core become large as DEMA was performed at four points on the cryptographic LSI. Each correlation coefficient at these points decreased when the magnetic thin film put on the cryptographic LSI. On the basis of these results, it was verified that the danger of the information leakage exists near the cryptographic IP core. These results demonstrate that the danger of the information leakage can be reduced markedly as the magnetic thin film puts on the cryptographic LSI.
A Study on Correlation Electromagnetic Analysis against KCipher-2 Implemented on a Microcontroller for ZigBee Device

UNO Hajime, ENDO Sho, HOMMA Naofumi, AOKI Takafumi, NAKANO Yuto, KIYOMOTO Shinsaku, MIYAKE Yutaka

IEICE technical report. Information theory　113　(483)　35-40　2014/03/10
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a correlation electromagnetic analysis against the stream cipher KCipher-2 software. Side-channel attacks are often applied to stream ciphers, if attacker can observe or choose initial vectors. There is a report that we can reveal a part of secret keys in the initialization process of KCipher-2 by a chosen-vector attack. In this paper, we discuss the potential of the correlation electromagnetic analysis against a KCipher-2 software implemented on a microcontroller for ZigBee device.
チップ内外での電源電圧取得によるサイドチャネル漏洩情報の一考察

藤本大介, 田中大智, 三浦典之, 永田真, 林優一, 本間尚文, 青木孝文, 堀洋平, 片下敏広, 﨑山一男, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger

暗号と情報セキュリティシンポジウム　2A3-3　2014/01
Education for Practical Hardware Security Based on Information Security Education Program

HAYASHI Yu-ichi, HOMMA Naofumi, KATASHITA Toshihiro, SONE Hideaki

Technical report of IEICE. ISEC　113　(342)　33-37　2013/12/11
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper reports an education course for the development of human resources in hardware security in a practical education program called enPiT Security. The course "Hardware Security Fundamentals" in enPiT Security introduces the fundamentals of information leakage from computer hardware, such as ICT devices, and provides hands-on experiences for studying the importance of hardware security. The primary goal of this course is to learn the basic concept of side-channel analysis, which reveals secret information from cryptographic hardware by side-channel information generated during its operations, and its countermeasures through hands-on experience.
暗号モジュールから漏洩する情報を利用するサイドチャネル攻撃

本間尚文, 青木孝文

システム制御情報学会誌　57　(12)　504-509　2013/12

DOI： 10.11509/isciesci.57.12_505 　
Fundamental Study on a Mechanism of Non-invasive Fault-injection at Arbitrary Timing of Cryptographic Processing

Kobayashi Mizuki, Hayashi Yu-ichi, Homma Naofumi, Mizuki Takaaki, Aoki Takafumi, Sone Hideaki

IEICE technical report. Microwaves　113　(260)　175-179　2013/10/24
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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In this paper, we introduce a new type of intentional electromagnetic interference (IEMI) fault-injection method with timing control based on leaked information. We demonstrate the fault injection attack based on the above IEMI through experiments using an Advanced Encryption Standard (AES) module implemented on a standard evaluation board (SASEBO). The experimental results indicate that generating effective faults is feasible. This paper also investigates a mechanism of faulty outputs from cryptographic modules due to the proposal method. We show the mechanism of fault occurrence through experiments using faulty ciphertexts and a sinusoidal wave injection to the specific round. The experimental results indicate that faulty outputs from cryptographic modules are caused by the overclocking to the cryptographic module.
サイドチャネル攻撃の概要と最新研究動向

本間尚文, 林優一

月刊EMC　306　(6)　21-30　2013/10
Publisher: 科学情報出版
ISSN： 0916-2275
暗号モジュールを搭載する情報機器上での効率的な情報漏えい可視化手法

林優一, 本間尚文

月刊EMC　306　(6)　54-59　2013/10
Publisher: 科学情報出版
ISSN： 0916-2275
Non-invasive fault-injection at arbitrary timing of cryptographic processing using leaked EM information

Kobayashi Mizuki, Hayashi Yu-ichi, Homma Naofumi, Mizuki Takaaki, Aoki Takafumi, Sone Hideaki

Proceedings of the Society Conference of IEICE　2013　101-101　2013/09/03
Publisher: The Institute of Electronics, Information and Communication Engineers
Development of Human Resources in Electromagnetic Information Security through Practical Education Program

Homma Naofumi, Hayashi Yu-ichi, Sone Hideaki

Proceedings of the Society Conference of IEICE　2013　(1)　"SS-44"　2013/09/03
Publisher: The Institute of Electronics, Information and Communication Engineers
Fundamental Study on Visualization of Intentional Electromagnetic Interference Fault Injection on Cryptographic Device

HAYASHI Yu-ichi, HOMMA Naofumi, MIZUKI Takaaki, AOKI Takafumi, SONE Hideaki

IEICE technical report. Electromagnetic compatibility　113　(2)　43-47　2013/04/12
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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An IEMI-based fault injection is drawing much attention in the field of physical attacks on cryptographic devices due to its non-contact and non-invasive properties. This paper explores the relations between injection intensity and fault occurrence during IEMI-based fault injection. The basic idea is to generate a map of the effect of such fault injection for different frequencies. Through the map generated on an evaluation board, we demonstrate how an injected EM wave is propagated to the board depending on the intensity and frequency. We also demonstrate a detailed propagation of induced EM waves inside a target module (i.e., a cryptographic LSI chip) and other modules. Using the experimental map generation, we examine the condition that a transient fault available for attacks is generated in the cryptographic module. In addition, we discuss a possible countermeasure against IEMI-based fault injection.
ガロア体上の乗算器モジュールジェネレータの構築

岡本広太郎, 本間尚文, 青木孝文

第75回全国大会講演論文集　2013　(1)　135-136　2013/03/06

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本稿では，ガロア体上の算術演算回路を自動生成可能なシステムを提案する．提案するシステムは，任意の既約多項式（次数2～256）を入力すると，ガロア体上の乗算器の最適な構成の1つであるMastrovito乗算器のHDL記述を生成する．同システムは，その内部にガロア体算術演算回路グラフ(Galois-Field Arithmetic Circuit Graph: GF-ACG)と呼ばれるグラフ表現に基づく設計手法を用いることで，生成する乗算器の機能を形式的に検証することができる．本稿では，まず，GF-ACGによるMastrovito乗算器の記述について述べ，構築したシステムの構成を概説する．その上で，代表的な次数の既約多項式を用いた生成実験を通して，機能が完全に検証された乗算器が短時間で生成されることを示す．
LED暗号ハードウェアに対する相関電力解析とその対策

ヴィッレウリマウル, 遠藤翔, 本間尚文, 青木孝文

全国大会講演論文集　2013　(1)　533-535　2013/03/06
Publisher: 一般社団法人情報処理学会

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近年,従来のブロック暗号アルゴリズムより小さな面積で実装可能な軽量暗号アルゴリズムとしてLED暗号が提案されており,RFIDやセンサーネットワークなどへの応用が期待されている.一方,暗号ハードウェアの消費電力,電磁波,演算時間などを解析し秘密情報を抽出するサイドチャネル攻撃が問題となっており,従来のブロック暗号ハードウェアに対する攻撃が成功していることから,LED暗号においてもサイドチャネル攻撃の可能性が考えられる.本稿では,LED暗号への相関電力解析の適用について述べ,シミュレーション及び実験を通して,その手法により鍵推定が可能であることを示すとともに,本攻撃への対策法を提案する.
B-4-59 A Study on Visualization of Magnetic-field Distributions due to IEMI to Cryptographic Modules

Shimada Haruki, Hayashi Yu-ichi, Homma NaofUmi, Mizuki Takaaki, Aoki Takafumi, Sone Hideaki

Proceedings of the IEICE General Conference　2013　(1)　404-404　2013/03/05
Publisher: The Institute of Electronics, Information and Communication Engineers
Fundamental Study on a Mechanism of Faulty Outputs from Cryptographic Modules Due to IEMI

112　(257)　83-86　2012/10/25
Publisher: 電子情報通信学会
ISSN： 0913-5685
A countermeasure against power analysis attacks on KCipher-2 and its evaluation

2012　(3)　749-756　2012/10/23
An Investigation of a Mechanism of Intentional Electromagnetic Interference to a Cryptographic Module

112　(100)　23-27　2012/06/22
Publisher: 電子情報通信学会
ISSN： 0913-5685
Fundamental study on efficient electromagnetic analysis on the frequency domain

HAYASHI Yu-ichi, MIZUKI Takaaki, HOMMA Naofumi, SONE Hideaki, AOKI Takafumi

2012　(1)　13-17　2012/03/12
Recent Research Trends in Side Channel Attack on Cryptographic Modules and its Countermeasure

HAYASHI Yu-ichi, HOMMA Naofumi, MIZUKI Takaaki, AOKI Takafumi, SONE Hideaki

IEEJ Transactions on Fundamentals and Materials　132　(1)　9-12　2012/01/01
Publisher: The Institute of Electrical Engineers of Japan
DOI： 10.1541/ieejfms.132.9 　

ISSN： 0385-4205

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Cryptographic modules are now mounted on many commercial products for secure transactions and communications. On the other hand, a new class of physical attacks against cryptographic modules, which is called “side channel attack,” is drawing much attention due to the non-invasive nature and effectiveness. This paper presents an overview of the research trends in side-channel attack and the related activities to counteract such attacks and evaluate the security of cryptographic modules.
A prediction method of information acquisition on electromagnetic information leakage

IKEMATSU Taishi, HAYASHI Yu-ichi, MIZUKI Takaaki, HOMMA Naofumi, SONE Hideaki, AOKI Takafumi

2011　(28)　23-28　2011/12/09
Fundamental study on investigation of relationship between the intensity of EM radiation and that of EM information leakage on a cryptographic device

SHIMADA Haruki, HAYASHI Yu-ichi, MIZUKI Takaaki, HOMMA Naofumi, SONE Hideaki, AOKI Takafumi

2011　(19)　23-27　2011/10/28
Improved Side Channel Attack using Multivariate RegressionAnalysis

2009　1-6　2011/10/12
B-4-58 Study on Intentional Electromagnetic Interference against Cryptographic Modules

Hayashi Yu-ichi, Homma Naofumi, Mizuki Takaaki, Aoki Takafumi, Sone Hideaki

Proceedings of the Society Conference of IEICE　2011　(1)　371-371　2011/08/30
Publisher: The Institute of Electronics, Information and Communication Engineers
Fundamental Study on Fault Injection Analysis to Cryptographic Module Using Intentional Electromagnetic Interference

HAYASHI Yu-ichi, SUGAWARA Takeshi, MIZUKI Takaaki, HOMMA Naofumi, AOKI Takafumi, SONE Hideaki

2011　(7)　53-57　2011/06/24
Evaluation of information availability from electronic devices on the basis of SNR

HAYASHI Yu-ichi, IKEMATSU Taishi, MIZUKI Takaaki, HOMMA Naofumi, AOKI Takafumi, SONE Hideaki

2011　(1)　5-9　2011/03/24
サイドチャネル攻撃

本間尚文, 青木孝文

映像情報メディア学会誌　64　(11)　1576-1579　2010/11
Publisher: The Institute of Image Information and Television Engineers
DOI： 10.3169/itej.64.1576 　

ISSN： 1342-6907
楕円曲線暗号ハードウェアの電力解析による安全性評価

齋藤和也, 菅原健, 本間尚文, 青木孝文, 佐藤証

電気関係学会東北支部連合大会講演論文集　2010　2010
ハッシュ関数Luffaのハードウェア実装

佐藤証, 片下敏宏, 菅原健, 本間尚文, 青木孝文

情報処理学会シンポジウムシリーズ(CD-ROM)　2010　(1)　2010

ISSN： 1882-0840
An Analysis of Electromagnetic Information Leakage of Cryptographic Modules

HAYASHI Yu-ichi, SUGAWARA Takeshi, HOMMA Naofumi, MIZUKI Takaaki, AOKI Takafumi, SONE Hideaki, SATOH Akashi

2009　(9)　33-38　2009/11/27
L-008 Template Attack on AES Hardware Implementations

Kim Yongdae, Sugawara Takeshi, Homma Naofumi, Aoki Takafumi, Satoh Akashi

8　(4)　139-146　2009/08/20
Publisher: Forum on Information Technology
C-039 High-Bandwidth Signal Measurement Using Bandwidth Interleaving Technique

Pratama Fajar Mega, Miyazawa Kazuyuki, Homma Naofumi, Aoki Takafumi, Yamaguchi Takahiro J., Degawa Katsuhiko, Akita Takayuki

8　(1)　527-534　2009/08/20
Publisher: Forum on Information Technology
A Countermeasure of Side Channel Attack on a Cryptographic LSI by Means of Magnetic Thin Film and Its Experimental Verification

TORIZUKA Hideki, SANDEEP Dhungana, YAMAGUCHI Masahiro, SUGAWARA Takeshi, HOMMA Naofumi, AOKI Takafumi, SATOH Akashi

2009　(76)　33-38　2009/08/07
第11回情報セキュリティ・シンポジウム「偽造防止技術の新潮流：金融業務における人工物メトリクスの可能性」の模様

本間尚文

金融研究　28　(2)　109-217　2009/07
Publisher: 日本銀行
ISSN： 0287-5306
RFマイクロ磁界プローブによる暗号LSIへの差分電磁波解析とその抑制法

鳥塚英樹, DHUNGANA S., 山口正洋, 菅原健, 本間尚文, 青木孝文, 佐藤証

日本磁気学会学術講演概要集　33rd　2009

ISSN： 1882-2959
RSA暗号プロセッサジェネレータの設計と評価

馬場祐一, 宮本篤志, 本間尚文, 青木孝文, 佐藤証

情報科学技術フォーラム講演論文集　8th　2009
L-007 Power Analysis of Cryptographic Modules in Frequency Domain

Sugawara Takeshi, Homma Naofumi, Hayashi Yu-ichi, Mizuki Takaaki, Aoki Takafumi, Sone Hideaki, Satoh Akashi

135-138　2009
Publisher: Forum on Information Technology
Design of multiple-valued arithmetic circuits based on arithmetic description language

21　237-242　2008/04/21
Publisher: [電子情報通信学会]
高基数モンゴメリ乗算に基づくRSA暗号の高性能ハードウェア実装

馬場祐一, 宮本篤志, 本間尚文, 青木孝文, 佐藤証

電気関係学会東北支部連合大会講演論文集　2008　2008
High-performance Error Detection Hardware Architecture for Block Cipher AES

佐藤証, 菅原健, 本間尚文, 青木孝文

情報処理学会シンポジウムシリーズ(CD-ROM)　2008　(1)　2008

ISSN： 1882-0840
High-performance Hardware Architectures for the Hash Function Whirlpool Based on Shift-register Architecture

菅原健, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウムシリーズ(CD-ROM)　2008　(1)　2008

ISSN： 1882-0840
Differential Power Analysis Experiments using an ASIC on a Standard Evaluation Board

菅原健, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2008　(8)　2008

ISSN： 1344-0640
Enhanced CPA using Key Screening Techniques

片下敏宏, 佐藤証, 菅原健, 本間尚文, 青木孝文

情報処理学会シンポジウム論文集　2008　(8)　2008

ISSN： 1344-0640
Side-channel Attack by Using Leakage Information on Power Cables

林優一, 菅原健, 本間尚文, 水木敬明, 青木孝文, 曽根秀昭, 佐藤証

情報処理学会シンポジウム論文集　2008　(8)　2008

ISSN： 1344-0640
Experimental evaluation of chosen-message power analysis attacks against RSA implementations

宮本篤志, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウムシリーズ(CD-ROM)　2008　(1)　2008

ISSN： 1882-0840
RSA暗号に対する平文選択型電力解析攻撃の検討

本間尚文

2008年暗号と情報セキュリティシンポジウム予稿集　2008
位相情報に基づく画像マッチング技術とその応用展開 ―3Dビジョンからバイオメトリクスまで―

青木孝文, 伊藤康一, 本間尚文

電子情報通信学会誌　90　(8)　680-685　2007/08
Publisher: 電子情報通信学会
ISSN： 0913-5693
Arithmetic Module Generation Using Optimized Parallel Prefix Adders

WATANABE Yuki, HOMMA Naofumi, AOKI Takafumi, HIGUCHI Tatsuo

IEICE technical report　107　(103)　49-54　2007/06/15
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents an arithmetic module generator using parallel prefix adders. In the proposed system, parallel prefix adders in a generated module can be optimized using the signal arrival profile of input signals. The proposed generator first generates an arithmetic module according to the design specification, and then evaluates the performance of the generated module in terms of the internal signal delay. Using the evaluation result, the system re-generates the parallel prefix adder block so as to optimize the circuit delay. In this paper, we demonstrate that we can improve the total performance of multipliers, constant-coefficient multipliers and multiply-accumulators using the re-generated prefix adders.
Optimal design of multiple-valued arithmetic circuits using counter tree diagrams

20　361-366　2007/04/23
Publisher: [電子情報通信学会]
Performance Comparison of the ISO Standard Block Ciphers in ASICs

SUGAWARA Takeshi, HOMMA Naofumi, AOKI Takafumi, SATOH Akashi

IEICE technical report　106　(595)　111-118　2007/03/09
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents performance comparison of the ISO/IEC18033 standard block ciphers (AES, Camellia, SEED, TDEA, MISTY1, and CAST-128) in ASICs. Each algorithm was implemented with a loop architecture where one round function block is iteratively used. In some designs, we finely divided the round operation into a few stages to reduce the hardware resource. These designs were synthesized by using a 0.18-μm CMOS standard cell library, and performances in size and speed were evaluated.
ASIC Implementations of the 128-bit Block Cipher CLEFIA

菅原健, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2007　(10)　2007

ISSN： 1344-0640
Simple Power Analysis Using Steady Value Inputs against RSA Hardware Implementation

宮本篤志, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウムシリーズ(CD-ROM)　2007　(1)　2007

ISSN： 1882-0840
Enhanced Power Analysis on Cryptographic Modules Using Waveform Filtering

長嶋聖, 本間尚文, 菅原健, 青木孝文, 佐藤証

情報処理学会シンポジウムシリーズ(CD-ROM)　2007　(1)　2007

ISSN： 1882-0840
Experimental evaluation of chosen-message SPA attacks against RSA implementations

宮本篤志, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2007　(10)　2007

ISSN： 1344-0640
Power analysis experiments against cryptographic hardware on a side-channel attack standard evaluation FPGA board

菅原健, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウムシリーズ(CD-ROM)　2007　(1)　2007

ISSN： 1882-0840
Formal Verification Method for Arithmetic Circuits and Its Evaluation

WATANABE Yuki, HOMMA Naofumi, AOKI Takafumi, HIGUCHI Tatsuo

IEICE technical report　106　(387)　17-22　2006/11/28
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents the formal design of arithmetic circuits based on arithmetic description language called ARITH. By using ARITH, we can describe a wide variety of arithmetic algorithms including those using unconventional number systems. The functionality of arithmetic algorithms in ARITH can be formally verified using formula manipulation methods. In this paper, we compare the proposed formula-based method with the conventional *BMD-based method, and demonstrate that the combination of the two methods enables to verify arithmetic circuits in an efficient way.
Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic

HOMMA Naofumi, AOKI Takafumi, HIGUCHI Tatsuo

IEICE Trans. Electron., C　89　(11)　1645-1654　2006/11/01
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0916-8524

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This paper presents an algorithm-level interpretation of fast adder structures in binary/multiple-valued logic. The key idea is to employ a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). The use of CTDs makes it possible to describe and analyze addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with multiple-valued logic devices, while a low-level CTD represents a network of primitive components directly mapped onto binary logic devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs. This paper demonstrates the interpretation of redundant arithmetic adders based on CTDs. We first introduce an extension of CTDs to represent possible redundant arithmetic adders with limited carry propagation. Using the extended version of CTDs, we can classify the conventional adder structures including those using emerging devices into three types in a systematic way.
A High-Resolution Waveform Analysis Based on Phase-Only Correlation and Its Application to Side-Channel Attacks

IMAI Yuichi, HOMMA Naofumi, NAGASHIMA Sei, AOKI Takafumi, SATOH Akashi

IEICE technical report　105　(665)　97-103　2006/03/16
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a high-resolution waveform alignment method using a Phase-Only Correlation (POC) technique and its application to side-channel attacks against cryptosystems. In general, power analysis attacks, such as SPA and DPA, require a statistical analysis of power waveforms to reduce noise and to retrieve secret information. However, the waveform data often include displacement errors in the measurement. The use of phase components in discrete Fourier transforms of waveforms makes it possible to estimate the displacements between signal waveforms with higher resolution than the sampling resolution. The effectiveness of power analysis attacks can be enhanced using the super-resolution alignment method. In this paper, we demonstrate the potential of the enhanced attacks through a set of experimental DPAs against DES software implementation on a Z80 processor.
High-Resolution Differential Power Analysis Using Waveform Matching Based on Phase-Only Correlation

今井裕一, 本間尚文, 長嶋聖, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2006　(11)　2006

ISSN： 1344-0640
A Compact ASIC Implementation of the 64-bit Block Cipher CAST-128

菅原健, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2006　(11)　2006

ISSN： 1344-0640
Experimental Evaluation of RSA Circuit against SPA on an FPGA Platform

宮本篤志, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2006　(11)　2006

ISSN： 1344-0640
High-Resolution Differential Power Analysis Using Waveform Matching Based on Phase-Only Correlation

今井裕一, 本間尚文, 長嶋聖, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2006

ISSN： 1344-0640
A Compact ASIC Implementation of the 64-bit Block Cipher CAST-128

菅原健, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2006

ISSN： 1344-0640
漏洩電磁波による共通鍵暗号処理ハードウェアの動作解析

菅原健, 本間尚文, 青木孝文, 佐藤証

電気関係学会東北支部連合大会講演論文集　2006　2006
Experimental Evaluation of RSA Circuit against SPA on an FPGA Platform

宮本篤志, 本間尚文, 青木孝文, 佐藤証

情報処理学会シンポジウム論文集　2006

ISSN： 1344-0640
Formal Design of Arithmetic Circuits with Arithmetic Description Language: ARITH

WATANABE Yuuki, HOMMA Nofumi, AOKI Takahumi, HIGUCHI Tatsuo

Technical report of IEICE. VLD　105　(148)　37-42　2005/06/21
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a design of parallel multipliers based on arithmetic description language called ARITH. The multiplication algorithms in ARITH can be verified formally by formula manipulations. In this paper, we also present an application of ARITH to a multiplier module generator. The proposed system generates 352 types of parallel multipliers including those using unconventional number systems such as redundant number systems.
Optimal Design of Fast Adders Based on Redundant Number Systems

HOMMA Naofumi, AOKI Takahumi, HIGUCHI Tatsuo

Technical report of IEICE. VLD　105　(148)　31-36　2005/06/21
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a unified representation of fast addition algorithms called Counter Tree Diagrams (CTDs) and its application to the optimal design of redundant arithmetic adders. By using CTDs, we can obtain possible constant-time redundant adders in a systematic way without using specific knowledge about underlying addition algorithms. The potential of the proposed approach is demonstrated through an experimental design of the optimal RB adders. The result shows that the obtained RB adder achieves about 30-40% higher performance in terms of power-delay product compared with the conventional designs.
RC-003 Design and Evaluation of RSA Processor Generator

Baba Yuichi, Miyamoto Atsushi, Homma Naofumi, Aoki Takafumi, Satoh Akashi

8　(1)　129-135　2005
Publisher: Forum on Information Technology
Development of a Multiplier Module Generator Using Arithmetic Description Language

ISHIDA Kazuya, HOMMA Naofumi, AOKI Takafumi, HIGUCHI Tatsuo

2004　(122)　239-244　2004/12/02
Publisher: Information Processing Society of Japan (IPSJ)
ISSN： 0919-6072

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This paper presents a design method for arithmetic circuits using an arithmetic description language: ARITH. The use of ARITH makes possible (i) formal description of arithmetic algorithms, (ii) formal verification of described arithmetic algorithms, and (iii) translation of arithmetic algorithms to equivalent HDL codes. This paper also presents an application of ARITH to a multiplier module generator. The developed generator can handle over 250 types of multiplication algorithms, and produce the multiplier modules whose functions are. completely verified at the algorithmic level.
Development of a Multiplier Module Generator Using Arithmetic Description Language

ISHIDA Kazuya, HOMMA Naofumi, AOKI Takafumi, HIGUCHI Tatsuo

IEICE technical report. Dependable computing　103　(482)　169-174　2004/12/02
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a design method for arithmetic circuits using an arithmetic description language: ARITH. The use of ARITH makes possible (i) formal description of arithmetic algorithms, (ii) formal verification of described arithmetic, algorithms, and (iii) translation of arithmetic algorithms to equivalent HDL codes. This paper also presents an application of ARITH to a multiplier module generator. The developed generator can handle over 250 types of multiplication algorithms, and produce the multiplier modules whose functions are completely verified at the algorithmic level.
A-3-10 Design of Redundant Binary Adders Using Counter Tree Diagrams

Wakamatsu Taihei, Homma Naofumi, Sakiyama Jun, Aoki Takafumi, Higuchi Tatsuo

Proceedings of the IEICE General Conference　2004　77-77　2004/03/08
Publisher: The Institute of Electronics, Information and Communication Engineers
Evolutionary Generation of Arithmetic Circuit Structures

HOMMA Naofumi, AOKI Takafumi, HIGUCHI Tatsuo

Technical report of IEICE. DSP　98　(144)　61-68　1998/06/26
Publisher: The Institute of Electronics, Information and Communication Engineers
ISSN： 0913-5685

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This paper presents a new approach to designing arithmetic circuits by using a graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG).The key idea of the proposed method is to introduce a higher level of abstraction for arithmetic algorithms, in which arithmetic circuit structures are modeled as data-flow graphs associated with specific number representation systems.When evaluating a data-flow graph, an edge and a node are interpreted as a set of active digits and a set of digit operations under the specified number system.The EGG system employs evolutionary operations to transform the structure of the graphs directly, which makes it possible to generate the optimum structure in the search space efficiently.The potential capability of EGG is demonstrated through an experiment of generating constant-coefficient multipliers.
Design of Arithmetic Algorithms Based on Evolutionary Graph Generation System

HOMMA Naofumi, AOKI Takafumi, HIGUCHI Tatsuo

Proceedings of the IEICE General Conference　1998　101-101　1998/03/06
Publisher: The Institute of Electronics, Information and Communication Engineers

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Books and Other Publications 9

Constructive Side-Channel Analysis and Secure Design: 15th International Workshop, COSADE 2024, Gardanne, France, April 9–10, 2024, Proceedings (Lecture Notes in Computer Science, 14595)

Naofumi Homma, Romain Wacquez

2024/04/17

ISBN: 3031575423
Special Issue on CHES 2017, Journal of Cryptographic Engineering, Vol. 8, Issue 2.

Wieland Fischer, Naofumi Homma

Springer　2018/06
Journal of Cryptographic Engineering

HOMMA Naofumi

Springer　2017/11
19th Conference on Cryptographic Hardware and Embedded Systems - CHES 2017

Wieland Fischer, Naofumi Homma

Springer　2017/09
Special Issue on Emerging Topics in Multiple-Valued Logic and Applications

Vincent Gaudet, Jon T. Butler, Robert Wille, Naofumi Homma

2016/03
14th Smart Card Research and Advanced Application Conference - CARDIS 2015

Naofumi Homma, Marcel Medwed

Springer　2016/02
2015 Workshop on Fault Diagnosis and Tolerance in Cryptography

Naofumi Homma, Victor Lomné

IEEE Computer Society　2015/09
Electromagnetic Radiation

Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Yu-Ichi Hayashi, Naofumi Homma

2012/06

ISBN: 9789535106395
Artificial Intelligence in Logic Design

SVETLANA N. YANUSHKEVICH 他

Kluwer Academic Publishers　2004/08/31

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Presentations 63

Secure Computing in the Quantum Computer Era Invited

Naofumi Homma

JST International Symposium on Computing Revolution for Society 5.0　2024/09/12
Beyond 5G/6G時代の次世代暗号に対する物理攻撃耐性評価基盤 Invited

藤本大介, 林優一, 本間尚文

電子情報通信学会ソサイエティ大会　2024/09/11
軽量暗号に対するサイドチャネル攻撃 Invited

本間尚文

CRYPTRECシンポジウム2024　2024/09/02
Trust of Information in Digital Age Invited

Naofumi Homma

The 20th Science and Technology in Society Forum (STSForum)　2023/10/01
耐量子計算機暗号ハードウェア設計の基礎 Invited

本間尚文

応用物理学会超集積エレクトロニクス産学連携委員会「夏の学校」　2023/08/25
ポスト5G, 6G時代を支えるデバイス・ハードウェアセキュリティ技術動向 Invited

本間尚文

JEITA先端電子材料・デバイス技術フォーラム　2023/07/18
量子コンピュータ時代のハードウェアセキュリティ技術 Invited

本間尚文

IMPULSEコンソーシアム　2023/03/30
ハードウェアトロイフリーを実現するLSIシステム設計技術 Invited

本間尚文

電子情報通信学会総合大会　2023/03/10
耐量子計算機暗号の耐タンパー実装技術の最新動向 Invited

本間尚文

SecurityDays 2023 Spring　2023/03/08
AI Security from Hardware Perspective Invited

Naofumi Homma

The 6th Tohoku Uni-NTU Symposium on Interdisciplinary AI and Human Studies　2023/02/26
Post-Quantum Cryptography - The Way Forward Invited

Naofumi Homma

Asian HOST　2022/12/15
耐量子計算機暗号の耐タンパー実装技術の最新動向 Invited

本間尚文

Security Days 2022 Fall　2022/10/07
耐量子計算機性秘匿計算に基づくセキュア情報処理基盤 Invited

本間尚文

Society5.0を支える革新的コンピューティング技術公開シンポジウム　2022/09/11
耐量子計算機暗号に対するサイドチャネル攻撃 Invited

本間尚文

2022年電子情報通信学会総合大会　2022/03/16
耐量子計算機暗号ソフトウェア・ハードウェアの耐タンパー実装技術の最新動向 Invited

本間尚文

Security Days 2022 Spring　2022/03/11
Secure Cryptographic Circuit Design against Side-Channel Attacks Invited

Naofumi Homma

IEEE 47th European Solid-State Circuits Conference (ESSCIRC 2021)　2021/09/24
耐量子計算機性秘匿計算に基づくセキュア情報処理基盤 Invited

本間尚文

第20回情報科学技術フォーラム（FIT2021）　2021/08/27
CASE時代における自動車ハードウェアのセキュリティ技術 Invited

本間尚文

第346回科学技術展望懇談会　2021/03/24
Society5.0を支えるセキュア情報処理基盤技術の開拓 Invited

本間尚文

2020 ハードウェアセキュリティフォーラム　2020/12/11
Designing Secure Cryptographic Circuits International-presentation Invited

Naofumi Homma

2019 IEEE International Electron Devices Meeting (IEDM)　2019/12/10
CHES Invited

本間尚文

2019ハードウェアセキュリティフォーラム　2019/12/06
ハードウェアセキュリティ技術とその展望 Invited

本間尚文

第110回ニューパラダイムコンピューティング研究会　2019/11/23
Circuit Design Resistant to Side Channel Attacks International-presentation Invited

Naofumi Homma

2019 Symposium on VLSI Circuits　2019/06/10
情報セキュリティを支える暗号技術 Invited

本間尚文

寺子屋仙台　2018/12/18
ハードウェアセキュリティ技術とその展望 Invited

本間尚文

東北大学電気・情報仙台フォーラム 2018　2018/11/29
Hardware Security: Research Field Expanding in IoT Era International-presentation Invited

Naofumi Homma

14th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2018)　2018/11/26
Hardware Security: Emerging Research Field in IoT Era International-presentation Invited

Naofumi Homma

The 13th International Workshop on Security　2018/09/03
耐タンパー性暗号LSIの設計技術, LSIとシステムのワークショップ Invited

本間尚文

LSIとシステムのワークショップ2018　2018/05/14
Side-Channel-Aware LSI Design International-presentation Invited

Naofumi Homma

2018 International Symposium on VLSI-Design, Automation and Test　2018/04/18
Recent Topics on Cryptographic Hardware Design International-presentation Invited

Naofumi Homma

National Tsing Hua University Seminar　2018/04/18
CHESの紹介と日本からの発表 Invited

第1回ハードウェアセキュリティフォーラム　2016/12/02
Environmentally Conscious AES Hardware Design International-presentation Invited

2016 STMicroelectronics workshop on hardware security　2016/09/27
Detection and Prevention of Side-Channel Attacks International-presentation Invited

2016 Dagstuhl Seminar on Foundations of Secure Scaling　2016/08/24
Education for Practical Hardware Security Technology International-presentation Invited

2016 IEEE International Symposium on Electromagnetic Compatibility　2016/07/25
Side-Channel-Aware Circuit Design: Prevention and Detection of Side-Channel Attacks International-presentation Invited

2016 IEEE International Solid-State Circuits Conference (ISSCC) Forum　2016/01/31
Hardware security - A New Challenge of Microelectronics International-presentation Invited

2015 International Workshop on Emerging Technologies of Microelectronics and Their Application to IoT Paradigm　2015/12/11
Recent topics on hardware security International-presentation Invited

2nd International Workshop on Information and Communication Security　2015/12/09
暗号システムへのサイドチャネル攻撃とその対策 Invited

スマートインフォメディアシステム研究会　2015/09/03
Formally-proofed Cryptographic Processor Design International-presentation Invited

2014 NII Shonan Workshop　2014/09/16
実践的教育プログラムを通じた電磁情報セキュリティ人材の育成 Invited

2013 年電子情報通信学会通信ソサイエティ大会　2013/09/19
Electromagnetic Information Leakage from Cryptographic Devices International-presentation Invited

EMC Europe 2013　2013/09/04
Overview of Electromagnetic Information Leakage from Cryptographic Modules International-presentation Invited

IEEE Symposium on Electromagnetic Compatibility　2013/08/05
災害に強いネットワークノードを実現するための技術の研究開発 Invited

第75回情報処理学会全国大会　2013/03/08
Toward Efficient Data processing and Protection under Disaster Situations International-presentation Invited

2013 Taiwan-Japan Workshop on Disaster-Resilient Multilayered Network　2013/01/28
Security Evaluation of Cryptographic Systems against Physical Attacks International-presentation Invited

2012 Bilateral Workshop between Tohoku University and National Tsing Hua University　2012/12/12
Toward Formal Design of Cryptographic Processors Based on Galois Field Arithmetic International-presentation Invited

PROOFS (Security Proofs for Embedded Systems) Workshop　2012/09/13
Special Panel Session on Upcoming Advances in MVL International-presentation Invited

42nd International Symposium on Multiple-Valued Logic　2012/05/14
DPA Contest V3 and SASEBO-W for V4 International-presentation Invited

International Workshop on Constructive Side-Channel Analysis and Secure Design　2011/02
画像コンピューティングからセキュアLSIまで Invited

本間尚文, 青木孝文

みやぎ組込み産業振興協議会　2011/01/31
Electromagnetic Information Leakage for Side-Channel Analysis of Cryptographic Modules International-presentation Invited

IEEE International Symposium on Electromagnetic Compatibility　2010/07
暗号LSIの設計技術 Invited

日本学術振興会シリコン超集積化システム第165委員会　2010/04/16
Hardware Security for Embedded Cryptographic Modules International-presentation Invited

The 2nd Joint Workshop between Tohoku University and National Tsing Hua University　2009/03/27
偽造防止を目的とした暗号ハードウェアとその耐タンパー技術の動向 Invited

第11回情報セキュリティ・シンポジウム　2009/03/11
暗号モジュールに対するサイドチャネル攻撃とその対策 Invited

第5回マルチメディア情報ハイディング研究会　2008/11/06
Formal verification of VLSI circuits using Grobner bases International-presentation Invited

渡邉裕樹

Applications of Computer Algebra 2008　2008/07/27
暗号処理システムの高精度サイドチャネル解析技術の開発と応用 Invited

地域発技術シーズ発表会　2008/01/31
Chosen-message SPA attacks against RSA hardware and software on SASEBO International-presentation Invited

IPA Cryptography Workshop 2007 Winter　2007/12/13
アルゴリズムレベルでの高速演算回路設計 Invited

第24回STARC アドバンスト講座システムアーキテクチャセミナー　2007/07/27
The recent developments in cryptographic hardware International-presentation Invited

Rice University Colloquium　2007/05/30
SPA attacks on RSA hardware implementations using chosen messages International-presentation Invited

IPA Cryptography Workshop 2007 Spring　2007/04/05
安全かつ高性能なRSA暗号プロセッサの開発 Invited

第3回「組込みシステム向け情報セキュリティ技術」情報交換会　2007/02/19
暗号処理LSIの設計技術 Invited

IEEE EMC-S 仙台チャプタ・コロキウム　2006/07/07
Graph-based approach for synthesizing arithmetic circuits International-presentation Invited

13th International Workshop on Post-Binary ULSI Systems　2004/05

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Industrial Property Rights 3

安全性評価装置，安全性評価方法及びプログラム

伊東燦, 上野嶺, 本間尚文

Property Type: Patent
認証暗号化装置、認証復号装置、認証暗号システム、方法及びコンピュータ可読媒体低遅延認証暗号

峯松一彦, 向井明子, 本間尚文, 上野嶺

Property Type: Patent
メモリ処理装置、メモリ検証装置、メモリ更新装置、メモリ保護システム、方法及びコンピュータ可読媒体

峯松一彦, 向井明子, 本間尚文, 上野嶺

Property Type: Patent

Research Projects 37

AIハードウェアセキュリティ基盤技術の開発 Competitive

本間尚文

Offer Organization: 科学技術振興機構

System: 経済安全保障重要技術育成プログラム（K-Program）／人工知能（AI）が浸透するデータ駆動型の経済社会に必要なAIセキュリティ技術の確立

2024/12 - 2029/11
Development Framework of VLSI Circuits and Systems Free from Hardware Trojans

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (S)

Institution: Kobe University

2022/04/27 - 2027/03/31
高効率かつ頑健なセキュアアビオニクス設計技術の開拓

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 挑戦的研究(萌芽)

Institution: 東北大学

2023/06 - 2026/03
Advanced formal design and verification theory for security hardware

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)

Category: Grant-in-Aid for Scientific Research (A)

Institution: Tohoku University

2021/04 - 2026/03
耐量子計算機性秘匿計算に基づくセキュア情報処理基盤 Competitive

本間尚文

Offer Organization: 科学技術振興機構

System: 戦略的創造研究推進事業CREST

2019/10 - 2025/03
IoT社会に対応したサイバー・フィジカル・セキュリティ Competitive

ECSEC,AIST

Offer Organization: 新エネルギー・産業技術総合開発機構

System: 戦略的イノベーション創造プログラム（SIP）第2期

2018/10 - 2023/03
高安全・高信頼な情報通信のためのトロイフリーLSIシステム設計・検証技術の開発 Competitive

本間尚文

Offer Organization: セコム科学技術振興財団

System: 一般研究助成

2018/10 - 2022/09
Development and Applications of Extremely Accurate Correspondence Techniques for Multidimensional Signals Based on Phase Information

Aoki Takafumi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2018/04/01 - 2021/03/31

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In this study, we developed a set of general-purpose image correspondence algorithms based on "high-accuracy correspondence of multidimensional signals based on local phase features represented in multiple resolutions." Through strategic application researches on biometrics, multi-view stereo 3D reconstruction, radar grammetry, and medical image analysis, we have demonstrated the effectiveness of phase-based image correspondence algorithms.
冗長ガロア体算術に基づくセキュリティハードウェアの高水準設計技術の研究開発 Competitive

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費補助金基盤研究（A）

2017/04 - 2021/03
Sensor-to-Cloud Security ～ビッグデータを守る革新的IoTセキュリティ基盤技術の研究開発 Competitive

松本勉

Offer Organization: 新エネルギー・産業技術総合開発機構

System: IoT推進のための横断技術開発プロジェクト

2016/04 - 2021/03
IoT システムを構成する機器のためのセキュア暗号モジュールの開発 Competitive

ルネサスエレクトロニクス, ECSEC

Offer Organization: 新エネルギー・産業技術総合開発機構

System: 戦略的イノベーション創造プログラム（SIP第1期）

2016/04 - 2020/03
Development of Countermeasures against Remote Visualization of Screen Images Using EM Emanation from Smart Devices in Public Space

Hayashi Yuichi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

2016/04/01 - 2019/03/31

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In this research, we developed evaluation and simulation techniques and countermeasures against electromagnetic (EM) information leakage from smart devices in public spaces. We also investigated the mechanism of EM information leakage. Specifically, we developed leak evaluation methods and used these to visualize the leaked EM field emitted from the target device. Then, based on the results, we clarified the leakage mechanism. Moreover, based on this mechanism, we identified design patterns on PCB boards related to such leakage and developed predictive simulation techniques. Furthermore, based on the identified mechanism, we have effectively combined the associated wiring patterns and electrical elements to prevent leakage, thereby developing inexpensive countermeasures that can be easily installed onto the target equipment.
次世代IT社会に求められる新機能暗号とそのハードウェア実装技術の開発 Competitive

松本勉

Offer Organization: セコム科学技術振興財団

System: 一般研究助成

2015/10 - 2019/03
Development of High-Accuracy Image Matching Techniques Using Feature Descriptors Based on Local Phase Array

Aoki Takafumi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2015/04/01 - 2018/03/31

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This project developed a new feature descriptor called local phase array, which is defined by phase information of Fourier transform of given images, and its advanced techniques. We applied developed techniques to a wide range of applications such as robust matching of biometric images, multi-view stereo image measurement, fast and high-accuracy machine vision, image measurement for airborne SAR images and medical volume data analysis. We also implemented developed methods on GPUs and FPGAs. We demonstrated the effectiveness of local phase array through its practical applications.
Development of formal design methodology for VLSI datapaths based on Galois-field arithmetic operations(Fostering Joint International Research) Competitive

Homma Naofumi, Danger Jean-Luc

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Fund for the Promotion of Joint International Research (Fostering Joint International Research)

Institution: Tohoku University

2016/07 - 2018/03

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This research has developed a formal description and verification method of tamper resistant cryptographic processors with attack countermeasures described as arithmetic operations on the Galois field in order to establish a formal design methodology of tamper resistant cryptographic processors. In addition, we have designed and developed highly efficient tamper resistant cryptographic processors as its application. In particular, since the threat of side-channel attack which directly accesses cryptographic processors to retrieve secret information is rapidly increasing, we focused on countermeasures against side-channel attacks and formally designed cryptographic processors resistant to that kind of attacks, and also performed the prototyping and evaluation of designed cryptographic processors.
Development of Side-Channel Attack Sensing Techniques and Prototyping toward Electromagnetic Security of Cryptographic VLSI Circuits

Nagata Makoto, Danger Jean-Luc

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (A)

Institution: Kobe University

2014/04/01 - 2017/03/31

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Cryptographic VLSI techniques have been established for assuring electromagnetic security with remarkably high tamper resistance against side-channel attacks. Three research items include: (1) On-chip detection of the proximate placement and approach of electromagnetic micro probes as the side-channel attack sensing technique, (2) integrated simulation techniques of electromagnetic coupling between the electromagnetic micro probe and on-chip side-channel sensors and also circuit operations, (3) positive usage of side-channel information for the authentication of cryptographic cores. These research items have been successfully completed and demonstrated with the fabricated integrated-circuit (IC) chips and prototype systems.
Development of formal design methodology for VLSI datapaths based on Galois-field arithmetic operations

Homma Naofumi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (A)

Category: Grant-in-Aid for Scientific Research (A)

Institution: Tohoku University

2013/04/01 - 2017/03/31

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This research project developed a formal design methodology for VLSI datapaths consisting of arithmetic operations on Galois fields. First, we provided (1) a formal description for Galois-field arithmetic circuits based on polynomial basis and normal basis which are frequently used for cryptography and error-correction code, and then developed (2) a formal verification method, which is applicable to the circuit description, using computer algebra. In addition, (3) we applied the design and verification methods to a cryptographic processor. More precisely, we designed a processor datapath for AES, which is one of the ISO/IEC international standard block ciphers, by the developed method. Furthermore, we developed an automatic generator for generating a variety of Galois-field arithmetic circuits depending on various design specification.
組込みシステムへのサイバー・フィジカル協調型攻撃を防ぐ命令シーケンス構成法の開拓 Competitive

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費補助金挑戦的萌芽研究

2016/04 - 2017/03
Development of formal design methodology for VLSI datapaths based on Galois-field arithmetic operations(Fostering Joint International Research) Competitive

Homma Naofumi, Danger Jean-Luc

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Fund for the Promotion of Joint International Research (Fostering Joint International Research)

Institution: Tohoku University

2013/04 - 2017/03

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This research has developed a formal description and verification method of tamper resistant cryptographic processors with attack countermeasures described as arithmetic operations on the Galois field in order to establish a formal design methodology of tamper resistant cryptographic processors. In addition, we have designed and developed highly efficient tamper resistant cryptographic processors as its application. In particular, since the threat of side-channel attack which directly accesses cryptographic processors to retrieve secret information is rapidly increasing, we focused on countermeasures against side-channel attacks and formally designed cryptographic processors resistant to that kind of attacks, and also performed the prototyping and evaluation of designed cryptographic processors.
Development of High-Accuracy Image Matching Technology Using Phase Information and Its Applications

AOKI Takafumi, HOMMA Naofumi, ITO Koichi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2012/04/01 - 2015/03/31

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This project developed fundamental and advanced techniques of Phase-Only Correlation (POC), which is a high-accuracy image matching technique using phase information of Fourier Transform of given images. We applied the developed POC techniques to a wide range of applications, including 3D measurement, video/image processing, machine vision, biometrics and medical image analysis. We also considered the implementation of their algorithms using the state-of-the-art GPUs toward the practical use of the developed techniques. We demonstrated effectiveness of the developed techniques through their practical applications.
組込みシステムにおける暗号プロセッサの物理攻撃に対する安全性評価 Competitive

本間尚文

Offer Organization: 科学技術振興機構

System: 戦略的国際科学技術協力推進事業（共同研究型）

2010/05 - 2013/03
耐タンパー性を有する超高性能公開鍵暗号プロセッサの開発 Competitive

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費補助金若手研究（A）

2010/04 - 2013/03
Applications of High-Accuracy Image Matching Technology Breaking the Limit of Pixel Resolution

AOKI Takafumi, HOMMA Naofumi, ITO Koichi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2009 - 2011

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In this project, we have developed fundamental techniques of Phase-Only Correlation (POC)-a technique for high-accuracy registration of 1D, 2D and 3D signals using phase information of discrete Fourier transform. We have also applied the POC techniques to a wide range of applications, including smart image sensors, microscope image analysis, passive 3D vision, automotive image processing, image-based human interface, biometrics authentication, and medical image analysis.
計算機代数に基づく高性能VLSIデータパスの形式的設計技術の開発 Competitive

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費補助金若手研究（B）

2008/04 - 2010/03
暗号モジュールに対する高精度電磁波解析技術の開拓

青木孝文, 本間尚文, 伊藤康一

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 挑戦的萌芽研究

Institution: 東北大学

2009 - 2010

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本年度は,下記の2項目に関する研究開発を実施した. 1.マイクロ磁界プローブ・RFカレントプローブを用いた電磁波解析システムの構築マイクロ磁界プローブ・RFカレントプローブ,ディジタルオシロスコープおよび解析用PCを基本としたシステムを開発した.一般に,EMI測定を目的としたマイクロ磁界プローブやRFカレントプローブは,スペクトラムアナライザと組み合わせて使用されることが多いが,開発するシステムにおいてはディジタルオシロスコープを使用した.これは,電磁波解析において,LSI動作時の時間波形が必要とされるためである.また,得られた放射電磁波の情報(電圧に変換)を適切に解析用PCに送信するインタフェースソフトウェアを開発した.ここではディジタルオシロスコープ専用のライブラリ関数とLabVIEW環境を用いて開発を行った. 2.位相限定相関法に基づく電磁波解析向け信号処理パッケージの開発多次元信号の超高精度マッチング技術を応用した電磁波解析向け信号処理ソフトウェアを開発した.特に,マイクロ磁界プローブ・RFカレントプローブとディジタルオシロスコープにより取得された1次元の電磁界波形データの解析に位相限定相関法(POC)を適用し,測定系のサンプリングレートを越える分解能での信号マッチングを実現した.具体的には,LabVIEWおよびMATLAB&Simulink環境上で,(1)位相限定相関法に基づく超高精度波形マッチング・ジッタ解析ライブラリ,(2)高速フーリエ変換(FFT)および各種フィルタバンクによる取得波形のスペクトル分析用ライブラリ,(3)暗号の各種統計解析ライブラリを開発した.これにより,測定から解析までの一連の流れを,本解析システムで閉じた形で実現できる環境を構築した.
ハードウェアアルゴリズムの高水準設計技術の開拓 Competitive

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費補助金若手研究（B）

2006/04 - 2008/03
暗号ハードウェアの高精度サイドチャネル解析技術の開拓

青木孝文, 本間尚文, 伊藤康一

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 萌芽研究

Institution: 東北大学

2007 - 2008

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平成20年度は, 以下の2項目について研究・開発を実施した. 1. ソフトウェア実装された共通鍵暗号モジュールに対する解析精度を評価した. 特に, 位相限定相関法に基づく波形マッチング技術を用いることで, 波形取得のタイミング誤差を高精度に補正可能であることを実証した. 共通鍵暗号には現在のデファクトスタンダードであるDESを用い, 実験用の差分電力解析ソフトウェアには前年度に開発したソフトウェアと連動するため, MATLABを用いた. 解析を簡単化するため, DESのラウンド15の開始時にトリガ信号を発生させ, そのタイミングで波形取得を行った. 波形の取得は, サンプリング周波数100MHz〜1GHzで行い, 提案する波形マッチングよる解析精度を周波数ごとに評価した. また, マイクロ磁界プローブによる取得に加え, 従来の電圧プローブによる取得も行い, 取得されたサイドチャネル情報の精度を比較・評価した. 2. ハードウェア実装された公開鍵暗号モジュールに対する解析精度を評価した. 公開鍵暗号にはRSA暗号を用い, 実装するRSA暗号プロセッサには高基数モンゴメリ乗算器に基づくアーキテクチャを用いた. 波形の取得およびデータの解析には前年度開発したソフトウェアを利用した。本実験では, 演算器の自乗算と乗算時の消費電力の違いに着目し, さまざまな実装の安全性を評価した. また, FPGAに内蔵されるマクロ乗算器を利用した実装も合わせて評価した. マクロ乗算器の場合であっても単純電力解析が可能かどうか評価するとともに, FPGA上に安全に公開鍵暗号モジュールを実装するための対策方法を検討した.
Development of Image Processing Technology Breaking the Limit of Pixel Resolution

AOKI Takafumi, HOMMA Naofumi, ITO Koichi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2006 - 2008
System Integration of Beyond-Binary Computing

HIGUCHI Tatsuo, AOKI Takafumi, HOMMA Naofumi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku Institute of Technology

2005 - 2007

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The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. In order to overcome the performance bottlenecks, this research project investigates system integration based on a novel computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project : 1. A hardware description language called ARITH was developed for describing hardware algorithms in VLSI systems. By using ARUM, we developed an advanced library containing high-performance arithmetic algorithms using both binary and non-binary number systems. As an application, we used the proposed library to develop a practical module generator supporting various multiplier structures. The generator is available from our website, and is widely used all over the world. 2. A new high-level design method with ARITH was developed for designing high-performance beyond-binary arithmetic circuits. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. For the prototype design, we used voltage-mode and current-mode CMOS technologies for binary logic and multiple-valued logic, respectively. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. The capability of the proposed method was investigated through some arithmetic circuit designs. 3. A content-addressable memory circuits based on Single-Electron Transistors (SETs) was developed and evaluated for studying next-generation low-power LSI circuits. Also, a redox microarray for wire-free circuit integration using artificial catalyst devices was investigated experimentally. A prototype of redox microarray was demonstrated through an excitable reaction-diffusion dynamics, which was implemented by chemical reaction(e.g. B-Z reaction)waves. The visualization of the chemical waves was also investigated.
暗号処理システムの高精度サイドチャネル解析技術の開発と応用 Competitive

本間尚文

Offer Organization: 科学技術振興機構

System: 重点地域研究開発推進事業

2005/12 - 2006/03
冗長数系に基づく高性能データパスの自動合成システム Competitive

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費補助金若手研究（B）

2004/04 - 2006/03
ハードウェアアルゴリズムの進化的合成に関する研究 Competitive

本間尚文

Offer Organization: 科学技術振興事業団

System: 戦略的創造研究推進事業さきがけ

2002/11 - 2006/03
2値・多値融合論理に基づくナノエレクトロニクスの開拓

青木孝文, 本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 萌芽研究

Institution: 東北大学

2005 - 2006

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平成18年度は以下の2項目について研究を行った. 1.SET/CMOS混載回路による2値・多値融合論理システムの設計技術の開発(担当:青木および本間) 前年度に検討した方式により,SET/CMOS混載回路によって実現される2値・多値融合論理システムの設計技術を開発した.まず,本研究代表者らが提案するハードウェアアルゴリズム記述言語ARITHおよびハードウェアアルゴリズム合成用データ構造CTD (Counter Tree Diagram)を用いた上位設計フローを開発した.この設計フローでは,従来の2値論理ハードウェアアルゴリズムのみならず,多値論理に基づく新しいハードウェアアルゴリズムの記述と検証を可能にした.さらに,ここで記述された2値・多値融合論理ハードウェアアルゴリズムをSET/CMOS混載回路にマッピングすることを目的とした下位設計フローを開発した.SETの物理モデルをSmartSpiceあるいはHSPICEなどに組み込んだSET/CMOS混載回路シミュレーション手法を開発するとともに,これを用いた回路の詳細設計フローの実現を検討した.SET物理モデルの作成とパラメータのチューニングには,NTT物性科学基礎研究所の協力を得た. 2.各種応用システムの設計と総合的な性能評価(担当:青木) 前年度の主要機能モジュールの設計結果を踏まえ,比較的大規模な応用システムLSIの設計を試みた.具体的には,単電子連想メモリ(CAM)の設計を行った.ここではSETによる4値SRAMセルを使用し,時分割でマルチビット/セルのデータ読み出しを行うとともに,データの照合を多入力SET論理とCMOSプリチャージ論理で実現した.この他にも,ドントケア情報の保持・検索を可能とする単電子CAMを設計し,提案技術のインパクトを総合的に評価した.
High-speed subpixel image sensing technique and its applications

AOKI Takafumi, HONMA Naofumi, HIGUCHI Tatsuo

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

Institution: Tohoku University

2003 - 2005

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1. A high-accuracy image matching technique using Phase-Only Correlation (POC) function was developed. The newly developed technique can improve matching performance by fitting the closed-form analytical model of the correlation peak to actual two-dimensional numerical data. This technique can also be extended to a spectrum weighting POC technique, where we modify cross-phase spectrum with some weighting functions to enhance registration accuracy. We provided systematic experimental analysis of the matching performance of the proposed technique by evaluating the errors in estimating the translational displacements, the rotation angle and the scale factor. 2. Some applications of the POC-based image matching/registration technique to (i) high-accuracy scale estimation for electron microscopes, (ii) high-accuracy measurement for metal component inspection, (iii) super-resolution processing for video sequences, (iv) high-quality background sprite generation, (v) video object segmentation, and (vi) fingerprint/3D face recognition were studied. 3. System implementation techniques were investigated for developing the above applications. We studied the implementation of the application (i) on a general-purpose processor since it handles only 2D still images. On the other hand, we studied the implementations of the applications (ii)-(vi) on a digital signal processor and specific hardware.
ハードウェアアルゴリズムの進化的合成システムの開発 Competitive

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費補助金若手研究（B）

2002/04 - 2004/03
New Developments for Beyond-Binary Computing

HIGUCHI Tatsuo, AOKI Takafumi

Offer Organization: Japan Society for the Promotion of Science

System: Grants-in-Aid for Scientific Research

Category: Grant-in-Aid for Scientific Research (B)

2002 - 2004

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The present-day VLSI systems are designed on the basis of binary (radix-2) arithmetic algorithms combined with binary logic devices. As the VLSI technology scales down to deep sub-micron geometry, performance bottlenecks caused by increased wiring complexity and delay are becoming significantly severe. In order to overcome the performance bottlenecks, this research project investigates new developments based on a novel computing paradigm called "Beyond-Binary Computing". Listed below are major results of this project: 1.A prototype of Arithmetic Description Language ARITH was developed. We confirmed that the use of ARITH makes possible (i) formal description of arithmetic algorithms including those using unconventional number systems, (ii) formal verification of described arithmetic algorithms, and (iii) translation of arithmetic algorithms to equivalent HDL (Hardware Description Language) codes. Impacts of ARITH were demonstrated through the development of a multiplier module generator. Also, new CAD techniques based on Evolutionary Graph Generation system were developed for designing high-performance beyond-binary arithmetic algorithms. 2.Impacts of multiple-valued current-mode logic technology were demonstrated through the design of field-programmable digital filter ICs. Also, an experimental design environment for practical multiple-valued current -mode logic circuits was developed. 3.Some applications of beyond-binary computing to high-accuracy 2D/3D image measurement techniques were studied. 4.A redox microarray for wire-free circuit integration using artificial catalyst devices, such as enzyme transistors, was developed experimentally. The redox microarray was used to demonstrate some applications of molecular computing, including optimal path planning and image processing.
進化的グラフ生成手法に基づく算術演算回路設計に関する研究

本間尚文

Offer Organization: 日本学術振興会

System: 科学研究費助成事業

Category: 特別研究員奨励費

Institution: 東北大学

1999 - 2001

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Media Coverage 5

テラバイトスケールのコンピュータメモリを安全で高効率に暗号化できる新技術を開発 Myself

日本経済新聞，クラウドWatch，Yahooニュース他

2024/10
新概念の鍵変換で暗号の物理安全性を飛躍的に向上～さまざまな暗号ソフトウェア・ハードウェアに革新

日本経済新聞，クラウドWatchほか

2023/12
ハードウェアに挿入された不正な機能を高速かつ漏れなく検知する技術を開発

日本経済新聞，日経クロステック，日刊工業新聞ほか

2022/04
量子コンピュータにも耐性を持つ次世代暗号を安全に実現する技術を開発・実証 Myself

日本経済新聞，日刊工業新聞ほか

2022/02

Type: Newspaper, magazine
ハードウェア“指紋”認証の新方式を開発

日本経済新聞，日刊工業新聞，EE Times,ほか

2020/09

Type: Newspaper, magazine